210 lines
6.3 KiB
C
210 lines
6.3 KiB
C
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/********************************************************************
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* Copyright(c) 2006-2009 Broadcom Corporation.
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*
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* Name: bc_decoder_regs.h
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*
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* Description: Common definitions for all components. Only types
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* is allowed to be included from this file.
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*
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* AU
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*
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* HISTORY:
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*
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********************************************************************
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* This header is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published
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* by the Free Software Foundation, either version 2.1 of the License.
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*
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* This header is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public License
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* along with this header. If not, see <http://www.gnu.org/licenses/>.
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*******************************************************************/
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#ifndef _INCLUDE_DECO_REGS_H_
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#define _INCLUDE_DECO_REGS_H_
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#include "bc_dts_types.h"
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// These are SDRAM specific registers
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#define SDRAM_PARAM 0x00040804
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#define SDRAM_REF_PARAM 0x00040808
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#define SDRAM_REFRESH 0x00040890
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#define SDRAM_MODE 0x000408A0
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#define SDRAM_EXT_MODE 0x000408A4
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#define SDRAM_PRECHARGE 0x000408B0
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#define SDRAM_INC 0x00040800
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// Registers to access the DRAM
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#define TOTAL_DRAM_SIZE (64 * 1024 * 1024) // We are using 64MB of DRAM
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#define DRAM_ACCESS_GRANUALITY 4 // We will always access DRAM ULONG by ULONG.
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#define DRAM_WINDOW_SIZE (512 * 1024) // 512 K.
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#define DRAM_WINDOW_BASE 0x00340020 // DRAM Address to access 512K Size of data.
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#define DRAM_SHADOW_DATA_START 0x00380000 // Start of 512 K of window for shadow data.
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#define DRAM_SHADOW_DATA_END 0x003FFFFF // End of 512 K of window for shadow data.
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#define AUD_DSP_MISC_SOFT_RESET 0x00240104
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#define AIO_MISC_PLL_RESET 0x0026000C
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//
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// To Reset the controller
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//
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#define DEC_HOST_SW_RESET 0x00340000
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/* Register Map */
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#define TS_Host2CpuSnd 0x00000100
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#define Hst2CpuMbx1 0x00100F00
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#define Cpu2HstMbx1 0x00100F04
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#define MbxStat1 0x00100F08
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#define Stream2Host_Intr_Sts 0x00100F24
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typedef union _STREAM_TO_HOST_INTR_STS_{
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struct {
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ULONG Res1:1; /* Reserved */
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ULONG VideoSetupOut0:1; /* Video Setup Intr Occured at port0. This means that the picture is ready to be displayed */
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ULONG VideoReleaseOut0:1; /* Video Release Intr Occured at port0. This means that picture is almost Done */
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ULONG AsynchEvent:1; /* Video Setup Intr Occured at port1. This means that the picture is ready to be displayed */
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ULONG Res2:1; /* Reserved */
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ULONG PicAvailIn0:1; /* PIC Avail Interrupt at port 0*/
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ULONG PicAvailIn1:1; /* PIC Avail Interrupt at port 1*/
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ULONG CRCDataAvail0:1; /* Intr Occured from Stream Entering at port 0*/
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ULONG Res3:1; /* Reserved */
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ULONG UserDataAvail0:1; /* User Data Intr occured for stream entring at port 0*/
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ULONG NewPCROffset:1; /* New PCR offset Intr Occured*/
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ULONG ErrNotify:1; /* An Err Notify Intr Occured*/
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ULONG HostDMAComplete:1; /* PCI Host Dma Interrupt occured*/
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ULONG AudioDecService:1; /* Audio Decoder Intr Occured*/
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ULONG InitalPTS:1; /* First Presentation Time Stamp recieved. Host should then write a new STC when in playback mode*/
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ULONG PTSDisc:1; /* A PTS discontinuity has occured*/
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ULONG Resv4:15; /* Reserved*/
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ULONG MailboxIntr:1; /* A Command Respose Mailbox interrupt occured */
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};
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ULONG WholeReg; /* If you want to access whole register without the bitmap*/
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}STRTOHOST_INTR_STS,*PSTRTOHOST_INTR_STS;
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#define REG_DecCA_RegCinBase 0xa0c
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#define REG_DecCA_RegCinEnd 0xa10
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#define REG_DecCA_RegCinWrPtr 0xa04
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#define REG_DecCA_RegCinRdPtr 0xa08
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/* TS case.. */
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#define REG_Dec_TsUser0Base 0x100864
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#define REG_Dec_TsUser0Rdptr 0x100868
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#define REG_Dec_TsUser0Wrptr 0x10086C
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#define REG_Dec_TsUser0Len 0x100870
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#define REG_Dec_TsUser0End 0x100874
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#define REG_Dec_TsUser0Empty 0x100878
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/* ASF Case ...*/
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#define REG_Dec_TsAudCDB2Base 0x10036c
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#define REG_Dec_TsAudCDB2Rdptr 0x100378
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#define REG_Dec_TsAudCDB2Wrptr 0x100374
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#define REG_Dec_TsAudCDB2End 0x100370
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// ----------- registers and bits for master mode DMA bursts into
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// ----------- block mode code-in port
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// -- code in block addresses
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#define BCMPCI_HOST_STREAMA_WINDOW_BASE 0x340200
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#define BCMPVI_HOST_STREAMA_WINDOW_END 0x34023f
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// -- DMA registers
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#define BCMPCI_DMA_CHAN0_SRC 0x340100
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#define BCMPCI_DMA_CHAN0_DEST 0x340104
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#define BCMPCI_DMA_CHAN0_CTL 0x340108
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#define BCMPCI_ICR 0x0001ec
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// -- bits in control register
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// read only status
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#define BCMPCI_IS_DMA_ACTIVE 0x80000000
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#define BCMPCI_IS_DMA_ERROR 0x40000000
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#define BCMPCI_IS_DMA_INT 0x20000000
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// control bits
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#define BCMPCI_IS_LOCAL_SDRAM 0x400000
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#define BCMPCI_INC_DST 0x200000
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#define BCMPCI_INC_SRC 0x100000
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// bit mask denoting area containing number of bytes to transfer
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#define BCMPCI_DMA_BYTES_MASK 0xfffff
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#define VectorTbl1 (UINT32) 0x00100F0C
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#define CpuDbg1 (UINT32) 0x00141010
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#define AuxRegs1 (UINT32) 0x00145000
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#define INIT_VEC1 (UINT32) 0x00000000
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#define UartSelectA (UINT32) 0x00100300
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#define UartSelectB (UINT32) 0x00100304
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#define DecHt_HostSwReset (UINT32) 0x340000
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#define TSHostStreamA 0x34002c
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#define StrTRA_TsFifoStatus 0x10044c
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#define DecHt_PllACtl 0x34000C
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#define DecHt_PllBCtl 0x340010
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#define DecHt_PllCCtl 0x340014
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#define DecHt_PllDCtl 0x340034
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#define DecHt_PllECtl 0x340038
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#define DQS_CTL_REGISTER 0x00040700
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#define DDR_DRIVER_CTL_REGISTER 0x00040704
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typedef union _DQS_CTL_REG_
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{
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struct{
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ULONG DQS0_DELAY:4;
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ULONG DQS1_DELAY:4;
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ULONG DQS2_DELAY:4;
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ULONG DQS3_DELAY:4;
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ULONG PULSE_WIDTH:4;
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ULONG MHZ:4;
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ULONG OV:1;
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ULONG SEN:1;
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ULONG CL25:1;
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ULONG RSV:5;
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};
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ULONG WholeReg;
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} DQS_CTL_REG;
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typedef union _DDR_DRIVER_CTL_REG_
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{
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struct{
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ULONG DDQ:2;
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ULONG SDQ:2;
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ULONG CL2DQ:1;
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ULONG RSV:3;
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ULONG DCTL:2;
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ULONG SCTL:2;
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ULONG CL2CTL:1;
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ULONG RSV1:3;
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ULONG RSV2:16;
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};
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ULONG WholeReg;
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} DDR_DRIVER_CTL_REG;
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#define HALF_EMPTY_BIT 0x80
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#define FIFO_HALF_EMPTY(a)\
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(a & HALF_EMPTY_BIT )
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#define FULL_BIT 0x20
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#define FIFO_FULL(a)\
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(a & FULL_BIT)
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#endif
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