74 lines
2.1 KiB
C
74 lines
2.1 KiB
C
/***************************************************************************
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* Copyright (c) 2005-2010, Broadcom Corporation.
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*
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* Name: crystalhd_flea_ddr . h
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*
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* Description:
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* BCM70015 generic DDR routines
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*
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* HISTORY:
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*
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**********************************************************************
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* This file is part of the crystalhd device driver.
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*
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* This driver is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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*
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* This driver is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this driver. If not, see <http://www.gnu.org/licenses/>.
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**********************************************************************/
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#undef BRCM_ALIGN
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#define BRCM_ALIGN(c,r,f) 0
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#define MEM_SYS_NUM_DDR_PLLS 2;
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/*extern uint32_t rts_prog_vals[][5]; */
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enum eDDR2_SPEED_GRADE {
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DDR2_400MHZ = 0x0,
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DDR2_333MHZ = 0x1,
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DDR2_266MHZ = 0x2,
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DDR2_200MHZ = 0x3,
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DDR2_533MHZ = 0x4,
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DDR2_667MHZ = 0x5
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};
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enum eSD_COL_SIZE {
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COL_BITS_9 = 0x0,
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COL_BITS_10 = 0x1,
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COL_BITS_11 = 0x2,
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};
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enum eSD_BANK_SIZE {
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BANK_SIZE_4 = 0x0,
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BANK_SIZE_8 = 0x1,
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};
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enum eSD_ROW_SIZE {
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ROW_SIZE_8K = 0x0,
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ROW_SIZE_16K = 0x1,
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};
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/*DDR PHY PLL init routine */
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void crystalhd_flea_ddr_pll_config(struct crystalhd_hw* hw, int32_t *speed_grade, int32_t num_plls, uint32_t tmode);
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/*DDR controller init routine */
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void crystalhd_flea_ddr_ctrl_init(struct crystalhd_hw *hw,
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int32_t port,
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int32_t ddr3,
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int32_t speed_grade,
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int32_t col,
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int32_t bank,
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int32_t row,
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uint32_t tmode );
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/*RTS Init routines */
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void crystalhd_flea_ddr_arb_rts_init(struct crystalhd_hw *hw);
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