diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c
index c081e84006..748ec3160b 100644
--- a/src/qemu/qemu_capabilities.c
+++ b/src/qemu/qemu_capabilities.c
@@ -326,6 +326,7 @@ VIR_ENUM_IMPL(virQEMUCaps, QEMU_CAPS_LAST,
"pxb-pcie", /* 220 */
"device-tray-moved-event",
+ "nec-usb-xhci-ports",
);
@@ -1685,6 +1686,10 @@ static struct virQEMUCapsStringFlags virQEMUCapsObjectPropsICH9[] = {
{ "disable_s4", QEMU_CAPS_ICH9_DISABLE_S4 },
};
+static struct virQEMUCapsStringFlags virQEMUCapsObjectPropsUSBNECXHCI[] = {
+ { "p3", QEMU_CAPS_NEC_USB_XHCI_PORTS },
+};
+
struct virQEMUCapsObjectTypeProps {
const char *type;
struct virQEMUCapsStringFlags *props;
@@ -1748,6 +1753,8 @@ static struct virQEMUCapsObjectTypeProps virQEMUCapsObjectProps[] = {
ARRAY_CARDINALITY(virQEMUCapsObjectPropsVirtioBalloon) },
{ "virtio-balloon-device", virQEMUCapsObjectPropsVirtioBalloon,
ARRAY_CARDINALITY(virQEMUCapsObjectPropsVirtioBalloon) },
+ { "nec-usb-xhci", virQEMUCapsObjectPropsUSBNECXHCI,
+ ARRAY_CARDINALITY(virQEMUCapsObjectPropsUSBNECXHCI) },
};
diff --git a/src/qemu/qemu_capabilities.h b/src/qemu/qemu_capabilities.h
index 705dfb11c4..d747fa9a73 100644
--- a/src/qemu/qemu_capabilities.h
+++ b/src/qemu/qemu_capabilities.h
@@ -357,6 +357,7 @@ typedef enum {
/* 220 */
QEMU_CAPS_DEVICE_PXB_PCIE, /* -device pxb-pcie */
QEMU_CAPS_DEVICE_TRAY_MOVED, /* DEVICE_TRAY_MOVED event */
+ QEMU_CAPS_NEC_USB_XHCI_PORTS, /* -device nec-usb-xhci.p3 ports setting */
QEMU_CAPS_LAST /* this must always be the last item */
} virQEMUCapsFlags;
diff --git a/tests/qemucapabilitiesdata/caps_1.2.2-1.replies b/tests/qemucapabilitiesdata/caps_1.2.2-1.replies
index fbddf3db30..2aa13f1030 100644
--- a/tests/qemucapabilitiesdata/caps_1.2.2-1.replies
+++ b/tests/qemucapabilitiesdata/caps_1.2.2-1.replies
@@ -1668,6 +1668,17 @@
}
}
+
+{
+ "return": [
+ {
+ "name": "msi",
+ "type": "uint32"
+ }
+ ]
+}
+
+
{
"return": [
{
diff --git a/tests/qemucapabilitiesdata/caps_1.3.1-1.caps b/tests/qemucapabilitiesdata/caps_1.3.1-1.caps
index de4ee0156a..fff215dcd0 100644
--- a/tests/qemucapabilitiesdata/caps_1.3.1-1.caps
+++ b/tests/qemucapabilitiesdata/caps_1.3.1-1.caps
@@ -129,4 +129,5 @@
+
diff --git a/tests/qemucapabilitiesdata/caps_1.3.1-1.replies b/tests/qemucapabilitiesdata/caps_1.3.1-1.replies
index 2542b67b49..d130ad7811 100644
--- a/tests/qemucapabilitiesdata/caps_1.3.1-1.replies
+++ b/tests/qemucapabilitiesdata/caps_1.3.1-1.replies
@@ -1846,6 +1846,35 @@
}
}
+{
+ "return": [
+ {
+ "name": "msi",
+ "type": "on/off"
+ },
+ {
+ "name": "msix",
+ "type": "on/off"
+ },
+ {
+ "name": "intrs",
+ "type": "uint32"
+ },
+ {
+ "name": "slots",
+ "type": "uint32"
+ },
+ {
+ "name": "2",
+ "type": "uint32"
+ },
+ {
+ "name": "p3",
+ "type": "uint32"
+ }
+ ]
+}
+
{
"return": [
{
diff --git a/tests/qemucapabilitiesdata/caps_1.4.2-1.caps b/tests/qemucapabilitiesdata/caps_1.4.2-1.caps
index 1dcf2fa67c..5aec5254d5 100644
--- a/tests/qemucapabilitiesdata/caps_1.4.2-1.caps
+++ b/tests/qemucapabilitiesdata/caps_1.4.2-1.caps
@@ -130,4 +130,5 @@
+
diff --git a/tests/qemucapabilitiesdata/caps_1.4.2-1.replies b/tests/qemucapabilitiesdata/caps_1.4.2-1.replies
index 46c329272f..93e705f348 100644
--- a/tests/qemucapabilitiesdata/caps_1.4.2-1.replies
+++ b/tests/qemucapabilitiesdata/caps_1.4.2-1.replies
@@ -1894,6 +1894,35 @@
}
}
+{
+ "return": [
+ {
+ "name": "msi",
+ "type": "on/off"
+ },
+ {
+ "name": "msix",
+ "type": "on/off"
+ },
+ {
+ "name": "intrs",
+ "type": "uint32"
+ },
+ {
+ "name": "slots",
+ "type": "uint32"
+ },
+ {
+ "name": "2",
+ "type": "uint32"
+ },
+ {
+ "name": "p3",
+ "type": "uint32"
+ }
+ ]
+}
+
{
"return": [
{
diff --git a/tests/qemucapabilitiesdata/caps_1.5.3-1.caps b/tests/qemucapabilitiesdata/caps_1.5.3-1.caps
index 67ea419d1f..5a97958e97 100644
--- a/tests/qemucapabilitiesdata/caps_1.5.3-1.caps
+++ b/tests/qemucapabilitiesdata/caps_1.5.3-1.caps
@@ -139,4 +139,5 @@
+
diff --git a/tests/qemucapabilitiesdata/caps_1.5.3-1.replies b/tests/qemucapabilitiesdata/caps_1.5.3-1.replies
index 37a735f6c1..878d5efec4 100644
--- a/tests/qemucapabilitiesdata/caps_1.5.3-1.replies
+++ b/tests/qemucapabilitiesdata/caps_1.5.3-1.replies
@@ -1965,6 +1965,35 @@
"id": "libvirt-36"
}
+{
+ "return": [
+ {
+ "name": "msi",
+ "type": "on/off"
+ },
+ {
+ "name": "msix",
+ "type": "on/off"
+ },
+ {
+ "name": "intrs",
+ "type": "uint32"
+ },
+ {
+ "name": "slots",
+ "type": "uint32"
+ },
+ {
+ "name": "2",
+ "type": "uint32"
+ },
+ {
+ "name": "p3",
+ "type": "uint32"
+ }
+ ]
+}
+
{
"return": [
{
diff --git a/tests/qemucapabilitiesdata/caps_1.6.0-1.caps b/tests/qemucapabilitiesdata/caps_1.6.0-1.caps
index fb91111a61..ac32825762 100644
--- a/tests/qemucapabilitiesdata/caps_1.6.0-1.caps
+++ b/tests/qemucapabilitiesdata/caps_1.6.0-1.caps
@@ -145,4 +145,5 @@
+
diff --git a/tests/qemucapabilitiesdata/caps_1.6.0-1.replies b/tests/qemucapabilitiesdata/caps_1.6.0-1.replies
index 89327022ba..070bc62054 100644
--- a/tests/qemucapabilitiesdata/caps_1.6.0-1.replies
+++ b/tests/qemucapabilitiesdata/caps_1.6.0-1.replies
@@ -2027,6 +2027,35 @@
"id": "libvirt-36"
}
+{
+ "return": [
+ {
+ "name": "msi",
+ "type": "on/off"
+ },
+ {
+ "name": "msix",
+ "type": "on/off"
+ },
+ {
+ "name": "intrs",
+ "type": "uint32"
+ },
+ {
+ "name": "slots",
+ "type": "uint32"
+ },
+ {
+ "name": "2",
+ "type": "uint32"
+ },
+ {
+ "name": "p3",
+ "type": "uint32"
+ }
+ ]
+}
+
{
"return": [
{
diff --git a/tests/qemucapabilitiesdata/caps_1.6.50-1.caps b/tests/qemucapabilitiesdata/caps_1.6.50-1.caps
index 60dbe52fa0..7bf94e7fe2 100644
--- a/tests/qemucapabilitiesdata/caps_1.6.50-1.caps
+++ b/tests/qemucapabilitiesdata/caps_1.6.50-1.caps
@@ -145,4 +145,5 @@
+
diff --git a/tests/qemucapabilitiesdata/caps_1.6.50-1.replies b/tests/qemucapabilitiesdata/caps_1.6.50-1.replies
index b9bb9a327d..0a37e12db6 100644
--- a/tests/qemucapabilitiesdata/caps_1.6.50-1.replies
+++ b/tests/qemucapabilitiesdata/caps_1.6.50-1.replies
@@ -1991,6 +1991,35 @@
"id": "libvirt-36"
}
+{
+ "return": [
+ {
+ "name": "msi",
+ "type": "on/off"
+ },
+ {
+ "name": "msix",
+ "type": "on/off"
+ },
+ {
+ "name": "intrs",
+ "type": "uint32"
+ },
+ {
+ "name": "slots",
+ "type": "uint32"
+ },
+ {
+ "name": "2",
+ "type": "uint32"
+ },
+ {
+ "name": "p3",
+ "type": "uint32"
+ }
+ ]
+}
+
{
"return": [
{
diff --git a/tests/qemucapabilitiesdata/caps_2.1.1-1.caps b/tests/qemucapabilitiesdata/caps_2.1.1-1.caps
index 9221674390..729000f3e8 100644
--- a/tests/qemucapabilitiesdata/caps_2.1.1-1.caps
+++ b/tests/qemucapabilitiesdata/caps_2.1.1-1.caps
@@ -163,4 +163,5 @@
+
diff --git a/tests/qemucapabilitiesdata/caps_2.1.1-1.replies b/tests/qemucapabilitiesdata/caps_2.1.1-1.replies
index fabda5572f..02f1f4eefa 100644
--- a/tests/qemucapabilitiesdata/caps_2.1.1-1.replies
+++ b/tests/qemucapabilitiesdata/caps_2.1.1-1.replies
@@ -2449,6 +2449,39 @@
"id": "libvirt-36"
}
+{
+ "return": [
+ {
+ "name": "msi",
+ "type": "on/off"
+ },
+ {
+ "name": "msix",
+ "type": "on/off"
+ },
+ {
+ "name": "superspeed-ports-first",
+ "type": "on/off"
+ },
+ {
+ "name": "intrs",
+ "type": "uint32"
+ },
+ {
+ "name": "slots",
+ "type": "uint32"
+ },
+ {
+ "name": "2",
+ "type": "uint32"
+ },
+ {
+ "name": "p3",
+ "type": "uint32"
+ }
+ ]
+}
+
{
"return": [
{
diff --git a/tests/qemucapabilitiesdata/caps_2.4.0-1.caps b/tests/qemucapabilitiesdata/caps_2.4.0-1.caps
index d52f7f3a5a..ad99957063 100644
--- a/tests/qemucapabilitiesdata/caps_2.4.0-1.caps
+++ b/tests/qemucapabilitiesdata/caps_2.4.0-1.caps
@@ -175,4 +175,5 @@
+
diff --git a/tests/qemucapabilitiesdata/caps_2.4.0-1.replies b/tests/qemucapabilitiesdata/caps_2.4.0-1.replies
index 299fdfc58c..fd17a0b4eb 100644
--- a/tests/qemucapabilitiesdata/caps_2.4.0-1.replies
+++ b/tests/qemucapabilitiesdata/caps_2.4.0-1.replies
@@ -2968,6 +2968,47 @@
"id": "libvirt-36"
}
+{
+ "return": [
+ {
+ "name": "msi",
+ "type": "on/off"
+ },
+ {
+ "name": "msix",
+ "type": "on/off"
+ },
+ {
+ "name": "superspeed-ports-first",
+ "type": "on/off"
+ },
+ {
+ "name": "force-pcie-endcap",
+ "type": "on/off"
+ },
+ {
+ "name": "streams",
+ "type": "on/off"
+ },
+ {
+ "name": "intrs",
+ "type": "uint32"
+ },
+ {
+ "name": "slots",
+ "type": "uint32"
+ },
+ {
+ "name": "2",
+ "type": "uint32"
+ },
+ {
+ "name": "p3",
+ "type": "uint32"
+ }
+ ]
+}
+
{
"return": [
{
diff --git a/tests/qemucapabilitiesdata/caps_2.5.0-1.caps b/tests/qemucapabilitiesdata/caps_2.5.0-1.caps
index e9750e42a1..8de8395d12 100644
--- a/tests/qemucapabilitiesdata/caps_2.5.0-1.caps
+++ b/tests/qemucapabilitiesdata/caps_2.5.0-1.caps
@@ -176,4 +176,5 @@
+
diff --git a/tests/qemucapabilitiesdata/caps_2.5.0-1.replies b/tests/qemucapabilitiesdata/caps_2.5.0-1.replies
index 7b692b5017..f25b105303 100644
--- a/tests/qemucapabilitiesdata/caps_2.5.0-1.replies
+++ b/tests/qemucapabilitiesdata/caps_2.5.0-1.replies
@@ -2988,6 +2988,47 @@
"id": "libvirt-36"
}
+{
+ "return": [
+ {
+ "name": "msi",
+ "type": "on/off"
+ },
+ {
+ "name": "msix",
+ "type": "on/off"
+ },
+ {
+ "name": "superspeed-ports-first",
+ "type": "on/off"
+ },
+ {
+ "name": "force-pcie-endcap",
+ "type": "on/off"
+ },
+ {
+ "name": "streams",
+ "type": "on/off"
+ },
+ {
+ "name": "intrs",
+ "type": "uint32"
+ },
+ {
+ "name": "slots",
+ "type": "uint32"
+ },
+ {
+ "name": "2",
+ "type": "uint32"
+ },
+ {
+ "name": "p3",
+ "type": "uint32"
+ }
+ ]
+}
+
{
"return": [
{
diff --git a/tests/qemucapabilitiesdata/caps_2.6.0-1.caps b/tests/qemucapabilitiesdata/caps_2.6.0-1.caps
index 208f06364b..84b96c7779 100644
--- a/tests/qemucapabilitiesdata/caps_2.6.0-1.caps
+++ b/tests/qemucapabilitiesdata/caps_2.6.0-1.caps
@@ -181,4 +181,5 @@
+
diff --git a/tests/qemucapabilitiesdata/caps_2.6.0-1.replies b/tests/qemucapabilitiesdata/caps_2.6.0-1.replies
index 8a4c3fe3c8..d80fe31ff6 100644
--- a/tests/qemucapabilitiesdata/caps_2.6.0-1.replies
+++ b/tests/qemucapabilitiesdata/caps_2.6.0-1.replies
@@ -2994,6 +2994,47 @@
"id": "libvirt-36"
}
+{
+ "return": [
+ {
+ "name": "msi",
+ "type": "on/off"
+ },
+ {
+ "name": "msix",
+ "type": "on/off"
+ },
+ {
+ "name": "superspeed-ports-first",
+ "type": "on/off"
+ },
+ {
+ "name": "force-pcie-endcap",
+ "type": "on/off"
+ },
+ {
+ "name": "streams",
+ "type": "on/off"
+ },
+ {
+ "name": "intrs",
+ "type": "uint32"
+ },
+ {
+ "name": "slots",
+ "type": "uint32"
+ },
+ {
+ "name": "2",
+ "type": "uint32"
+ },
+ {
+ "name": "p3",
+ "type": "uint32"
+ }
+ ]
+}
+
{
"return": [
{