2010-11-06 05:23:30 +08:00
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/*
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* Copyright © 2010 Daniel Vetter
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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2012-10-03 01:01:07 +08:00
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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2010-11-06 05:23:30 +08:00
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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2012-10-23 02:44:43 +08:00
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typedef uint32_t gtt_pte_t;
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2012-11-05 01:21:31 +08:00
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/* PPGTT stuff */
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#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
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#define GEN6_PDE_VALID (1 << 0)
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/* gen6+ has bit 11-4 for physical addr bit 39-32 */
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#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define GEN6_PTE_VALID (1 << 0)
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#define GEN6_PTE_UNCACHED (1 << 1)
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#define HSW_PTE_UNCACHED (0)
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#define GEN6_PTE_CACHE_LLC (2 << 1)
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#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
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#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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2012-09-25 07:44:32 +08:00
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static inline gtt_pte_t pte_encode(struct drm_device *dev,
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dma_addr_t addr,
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2012-10-20 00:33:22 +08:00
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enum i915_cache_level level)
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2012-09-25 07:44:32 +08:00
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{
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gtt_pte_t pte = GEN6_PTE_VALID;
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pte |= GEN6_PTE_ADDR_ENCODE(addr);
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2012-10-20 00:33:22 +08:00
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switch (level) {
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case I915_CACHE_LLC_MLC:
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/* Haswell doesn't set L3 this way */
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if (IS_HASWELL(dev))
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pte |= GEN6_PTE_CACHE_LLC;
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else
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pte |= GEN6_PTE_CACHE_LLC_MLC;
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break;
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case I915_CACHE_LLC:
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pte |= GEN6_PTE_CACHE_LLC;
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break;
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case I915_CACHE_NONE:
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if (IS_HASWELL(dev))
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pte |= HSW_PTE_UNCACHED;
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else
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pte |= GEN6_PTE_UNCACHED;
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break;
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default:
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BUG();
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}
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2012-09-25 07:44:32 +08:00
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return pte;
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}
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2012-02-10 00:15:46 +08:00
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/* PPGTT support for Sandybdrige/Gen6 and later */
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static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
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unsigned first_entry,
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unsigned num_entries)
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{
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2012-10-23 02:44:43 +08:00
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gtt_pte_t *pt_vaddr;
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gtt_pte_t scratch_pte;
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2012-02-10 00:15:47 +08:00
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unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
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unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
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unsigned last_pte, i;
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2012-02-10 00:15:46 +08:00
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2012-09-25 07:44:32 +08:00
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scratch_pte = pte_encode(ppgtt->dev, ppgtt->scratch_page_dma_addr,
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2012-10-20 00:33:22 +08:00
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I915_CACHE_LLC);
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2012-02-10 00:15:46 +08:00
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2012-02-10 00:15:47 +08:00
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while (num_entries) {
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last_pte = first_pte + num_entries;
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if (last_pte > I915_PPGTT_PT_ENTRIES)
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last_pte = I915_PPGTT_PT_ENTRIES;
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pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
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2012-02-10 00:15:46 +08:00
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2012-02-10 00:15:47 +08:00
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for (i = first_pte; i < last_pte; i++)
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pt_vaddr[i] = scratch_pte;
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2012-02-10 00:15:46 +08:00
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kunmap_atomic(pt_vaddr);
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2012-02-10 00:15:47 +08:00
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num_entries -= last_pte - first_pte;
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first_pte = 0;
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act_pd++;
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}
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2012-02-10 00:15:46 +08:00
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}
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int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_hw_ppgtt *ppgtt;
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unsigned first_pd_entry_in_global_pt;
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int i;
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int ret = -ENOMEM;
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/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
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* entries. For aliasing ppgtt support we just steal them at the end for
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* now. */
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2012-08-24 16:12:22 +08:00
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first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
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2012-02-10 00:15:46 +08:00
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ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
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if (!ppgtt)
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return ret;
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2012-09-24 23:55:51 +08:00
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ppgtt->dev = dev;
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2012-02-10 00:15:46 +08:00
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ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
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ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
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GFP_KERNEL);
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if (!ppgtt->pt_pages)
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goto err_ppgtt;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
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if (!ppgtt->pt_pages[i])
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goto err_pt_alloc;
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}
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if (dev_priv->mm.gtt->needs_dmar) {
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ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t)
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*ppgtt->num_pd_entries,
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GFP_KERNEL);
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if (!ppgtt->pt_dma_addr)
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goto err_pt_alloc;
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2012-04-10 23:29:17 +08:00
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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dma_addr_t pt_addr;
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2012-02-10 00:15:46 +08:00
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pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i],
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0, 4096,
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PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev,
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pt_addr)) {
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ret = -EIO;
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goto err_pd_pin;
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}
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ppgtt->pt_dma_addr[i] = pt_addr;
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2012-04-10 23:29:17 +08:00
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}
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2012-02-10 00:15:46 +08:00
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}
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ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;
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i915_ppgtt_clear_range(ppgtt, 0,
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ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
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2012-10-23 02:44:43 +08:00
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ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t);
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2012-02-10 00:15:46 +08:00
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dev_priv->mm.aliasing_ppgtt = ppgtt;
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return 0;
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err_pd_pin:
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if (ppgtt->pt_dma_addr) {
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for (i--; i >= 0; i--)
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pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
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4096, PCI_DMA_BIDIRECTIONAL);
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}
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err_pt_alloc:
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kfree(ppgtt->pt_dma_addr);
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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if (ppgtt->pt_pages[i])
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__free_page(ppgtt->pt_pages[i]);
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}
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kfree(ppgtt->pt_pages);
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err_ppgtt:
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kfree(ppgtt);
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return ret;
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}
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void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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int i;
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if (!ppgtt)
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return;
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if (ppgtt->pt_dma_addr) {
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for (i = 0; i < ppgtt->num_pd_entries; i++)
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pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
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4096, PCI_DMA_BIDIRECTIONAL);
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}
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kfree(ppgtt->pt_dma_addr);
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for (i = 0; i < ppgtt->num_pd_entries; i++)
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__free_page(ppgtt->pt_pages[i]);
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kfree(ppgtt->pt_pages);
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kfree(ppgtt);
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}
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2012-02-10 00:15:47 +08:00
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static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt,
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2012-06-01 22:20:22 +08:00
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const struct sg_table *pages,
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2012-02-10 00:15:47 +08:00
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unsigned first_entry,
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2012-10-20 00:33:22 +08:00
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enum i915_cache_level cache_level)
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2012-02-10 00:15:47 +08:00
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{
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2012-09-25 07:44:32 +08:00
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gtt_pte_t *pt_vaddr;
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2012-02-10 00:15:47 +08:00
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unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
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unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
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unsigned i, j, m, segment_len;
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dma_addr_t page_addr;
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struct scatterlist *sg;
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/* init sg walking */
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2012-06-01 22:20:22 +08:00
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sg = pages->sgl;
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2012-02-10 00:15:47 +08:00
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i = 0;
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segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
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m = 0;
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2012-06-01 22:20:22 +08:00
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while (i < pages->nents) {
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2012-02-10 00:15:47 +08:00
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pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
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for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
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page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
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2012-09-25 07:44:32 +08:00
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pt_vaddr[j] = pte_encode(ppgtt->dev, page_addr,
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2012-10-20 00:33:22 +08:00
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cache_level);
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2012-02-10 00:15:47 +08:00
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/* grab the next page */
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2012-06-01 22:20:22 +08:00
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if (++m == segment_len) {
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if (++i == pages->nents)
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2012-02-10 00:15:47 +08:00
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break;
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2012-06-01 22:20:22 +08:00
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sg = sg_next(sg);
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2012-02-10 00:15:47 +08:00
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segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
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m = 0;
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}
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}
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kunmap_atomic(pt_vaddr);
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first_pte = 0;
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act_pd++;
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}
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}
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void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
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struct drm_i915_gem_object *obj,
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enum i915_cache_level cache_level)
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{
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2012-06-01 22:20:22 +08:00
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i915_ppgtt_insert_sg_entries(ppgtt,
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2012-09-05 04:02:58 +08:00
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obj->pages,
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2012-06-01 22:20:22 +08:00
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obj->gtt_space->start >> PAGE_SHIFT,
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2012-10-20 00:33:22 +08:00
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cache_level);
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2012-02-10 00:15:47 +08:00
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}
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void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
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struct drm_i915_gem_object *obj)
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{
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i915_ppgtt_clear_range(ppgtt,
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obj->gtt_space->start >> PAGE_SHIFT,
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obj->base.size >> PAGE_SHIFT);
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}
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2012-11-05 01:21:31 +08:00
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void i915_gem_init_ppgtt(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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uint32_t pd_offset;
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struct intel_ring_buffer *ring;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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2012-12-19 02:31:24 +08:00
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gtt_pte_t __iomem *pd_addr;
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2012-11-05 01:21:31 +08:00
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uint32_t pd_entry;
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int i;
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if (!dev_priv->mm.aliasing_ppgtt)
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return;
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2012-12-19 02:31:27 +08:00
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pd_addr = (gtt_pte_t __iomem*)dev_priv->mm.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t);
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2012-11-05 01:21:31 +08:00
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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dma_addr_t pt_addr;
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if (dev_priv->mm.gtt->needs_dmar)
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pt_addr = ppgtt->pt_dma_addr[i];
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else
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pt_addr = page_to_phys(ppgtt->pt_pages[i]);
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pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
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pd_entry |= GEN6_PDE_VALID;
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writel(pd_entry, pd_addr + i);
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}
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readl(pd_addr);
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pd_offset = ppgtt->pd_offset;
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pd_offset /= 64; /* in cachelines, */
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pd_offset <<= 16;
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if (INTEL_INFO(dev)->gen == 6) {
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uint32_t ecochk, gab_ctl, ecobits;
|
|
|
|
|
|
|
|
ecobits = I915_READ(GAC_ECO_BITS);
|
|
|
|
I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
|
|
|
|
|
|
|
|
gab_ctl = I915_READ(GAB_CTL);
|
|
|
|
I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
|
|
|
|
|
|
|
|
ecochk = I915_READ(GAM_ECOCHK);
|
|
|
|
I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
|
|
|
|
ECOCHK_PPGTT_CACHE64B);
|
|
|
|
I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
|
|
|
|
} else if (INTEL_INFO(dev)->gen >= 7) {
|
|
|
|
I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
|
|
|
|
/* GFX_MODE is per-ring on gen7+ */
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_ring(ring, dev_priv, i) {
|
|
|
|
if (INTEL_INFO(dev)->gen >= 7)
|
|
|
|
I915_WRITE(RING_MODE_GEN7(ring),
|
|
|
|
_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
|
|
|
|
|
|
|
|
I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
|
|
|
|
I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-10-18 06:51:55 +08:00
|
|
|
static bool do_idling(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
bool ret = dev_priv->mm.interruptible;
|
|
|
|
|
|
|
|
if (unlikely(dev_priv->mm.gtt->do_idle_maps)) {
|
|
|
|
dev_priv->mm.interruptible = false;
|
2012-04-27 07:02:58 +08:00
|
|
|
if (i915_gpu_idle(dev_priv->dev)) {
|
2011-10-18 06:51:55 +08:00
|
|
|
DRM_ERROR("Couldn't idle GPU\n");
|
|
|
|
/* Wait a bit, in hopes it avoids the hang */
|
|
|
|
udelay(10);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
|
|
|
|
{
|
|
|
|
if (unlikely(dev_priv->mm.gtt->do_idle_maps))
|
|
|
|
dev_priv->mm.interruptible = interruptible;
|
|
|
|
}
|
|
|
|
|
2012-11-05 01:21:27 +08:00
|
|
|
|
|
|
|
static void i915_ggtt_clear_range(struct drm_device *dev,
|
|
|
|
unsigned first_entry,
|
|
|
|
unsigned num_entries)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
gtt_pte_t scratch_pte;
|
2012-12-19 02:31:26 +08:00
|
|
|
gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->mm.gsm + first_entry;
|
2012-11-05 01:21:27 +08:00
|
|
|
const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;
|
2012-11-27 13:52:54 +08:00
|
|
|
int i;
|
2012-11-05 01:21:27 +08:00
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen < 6) {
|
|
|
|
intel_gtt_clear_range(first_entry, num_entries);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (WARN(num_entries > max_entries,
|
|
|
|
"First entry = %d; Num entries = %d (max=%d)\n",
|
|
|
|
first_entry, num_entries, max_entries))
|
|
|
|
num_entries = max_entries;
|
|
|
|
|
|
|
|
scratch_pte = pte_encode(dev, dev_priv->mm.gtt->scratch_page_dma, I915_CACHE_LLC);
|
2012-11-27 13:52:54 +08:00
|
|
|
for (i = 0; i < num_entries; i++)
|
|
|
|
iowrite32(scratch_pte, >t_base[i]);
|
2012-11-05 01:21:27 +08:00
|
|
|
readl(gtt_base);
|
|
|
|
}
|
|
|
|
|
2010-11-06 05:23:30 +08:00
|
|
|
void i915_gem_restore_gtt_mappings(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-11-09 03:18:58 +08:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-11-06 05:23:30 +08:00
|
|
|
|
2011-01-21 18:54:32 +08:00
|
|
|
/* First fill our portion of the GTT with scratch pages */
|
2012-11-05 01:21:27 +08:00
|
|
|
i915_ggtt_clear_range(dev, dev_priv->mm.gtt_start / PAGE_SIZE,
|
2013-01-18 04:45:12 +08:00
|
|
|
dev_priv->mm.gtt_total / PAGE_SIZE);
|
2011-01-21 18:54:32 +08:00
|
|
|
|
drm/i915: Track unbound pages
When dealing with a working set larger than the GATT, or even the
mappable aperture when touching through the GTT, we end up with evicting
objects only to rebind them at a new offset again later. Moving an
object into and out of the GTT requires clflushing the pages, thus
causing a double-clflush penalty for rebinding.
To avoid having to clflush on rebinding, we can track the pages as they
are evicted from the GTT and only relinquish those pages on memory
pressure.
As usual, if it were not for the handling of out-of-memory condition and
having to manually shrink our own bo caches, it would be a net reduction
of code. Alas.
Note: The patch also contains a few changes to the last-hope
evict_everything logic in i916_gem_execbuffer.c - we no longer try to
only evict the purgeable stuff in a first try (since that's superflous
and only helps in OOM corner-cases, not fragmented-gtt trashing
situations).
Also, the extraction of the get_pages retry loop from bind_to_gtt (and
other callsites) to get_pages should imo have been a separate patch.
v2: Ditch the newly added put_pages (for unbound objects only) in
i915_gem_reset. A quick irc discussion hasn't revealed any important
reason for this, so if we need this, I'd like to have a git blame'able
explanation for it.
v3: Undo the s/drm_malloc_ab/kmalloc/ in get_pages that Chris noticed.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Split out code movements and rant a bit in the commit message
with a few Notes. Done v2]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-20 17:40:46 +08:00
|
|
|
list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
|
2010-12-08 22:28:54 +08:00
|
|
|
i915_gem_clflush_object(obj);
|
2012-02-16 06:50:21 +08:00
|
|
|
i915_gem_gtt_bind_object(obj, obj->cache_level);
|
2010-11-06 05:23:30 +08:00
|
|
|
}
|
|
|
|
|
2012-11-05 01:21:27 +08:00
|
|
|
i915_gem_chipset_flush(dev);
|
2010-11-06 05:23:30 +08:00
|
|
|
}
|
2010-11-06 17:10:47 +08:00
|
|
|
|
2012-02-16 06:50:21 +08:00
|
|
|
int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
|
2010-11-06 17:10:47 +08:00
|
|
|
{
|
2012-06-01 22:20:22 +08:00
|
|
|
if (obj->has_dma_mapping)
|
2012-02-16 06:50:21 +08:00
|
|
|
return 0;
|
2012-06-01 22:20:22 +08:00
|
|
|
|
|
|
|
if (!dma_map_sg(&obj->base.dev->pdev->dev,
|
|
|
|
obj->pages->sgl, obj->pages->nents,
|
|
|
|
PCI_DMA_BIDIRECTIONAL))
|
|
|
|
return -ENOSPC;
|
|
|
|
|
|
|
|
return 0;
|
2010-11-06 17:10:47 +08:00
|
|
|
}
|
|
|
|
|
2012-11-05 01:21:27 +08:00
|
|
|
/*
|
|
|
|
* Binds an object into the global gtt with the specified cache level. The object
|
|
|
|
* will be accessible to the GPU via commands whose operands reference offsets
|
|
|
|
* within the global GTT as well as accessible by the GPU through the GMADR
|
|
|
|
* mapped BAR (dev_priv->mm.gtt->gtt).
|
|
|
|
*/
|
|
|
|
static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj,
|
|
|
|
enum i915_cache_level level)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = obj->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct sg_table *st = obj->pages;
|
|
|
|
struct scatterlist *sg = st->sgl;
|
|
|
|
const int first_entry = obj->gtt_space->start >> PAGE_SHIFT;
|
|
|
|
const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;
|
2012-12-19 02:31:27 +08:00
|
|
|
gtt_pte_t __iomem *gtt_entries =
|
|
|
|
(gtt_pte_t __iomem *)dev_priv->mm.gsm + first_entry;
|
2012-11-05 01:21:27 +08:00
|
|
|
int unused, i = 0;
|
|
|
|
unsigned int len, m = 0;
|
|
|
|
dma_addr_t addr;
|
|
|
|
|
|
|
|
for_each_sg(st->sgl, sg, st->nents, unused) {
|
|
|
|
len = sg_dma_len(sg) >> PAGE_SHIFT;
|
|
|
|
for (m = 0; m < len; m++) {
|
|
|
|
addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
|
2012-11-06 17:50:16 +08:00
|
|
|
iowrite32(pte_encode(dev, addr, level), >t_entries[i]);
|
2012-11-05 01:21:27 +08:00
|
|
|
i++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
BUG_ON(i > max_entries);
|
|
|
|
BUG_ON(i != obj->base.size / PAGE_SIZE);
|
|
|
|
|
|
|
|
/* XXX: This serves as a posting read to make sure that the PTE has
|
|
|
|
* actually been updated. There is some concern that even though
|
|
|
|
* registers and PTEs are within the same BAR that they are potentially
|
|
|
|
* of NUMA access patterns. Therefore, even with the way we assume
|
|
|
|
* hardware should work, we must keep this posting read for paranoia.
|
|
|
|
*/
|
|
|
|
if (i != 0)
|
|
|
|
WARN_ON(readl(>t_entries[i-1]) != pte_encode(dev, addr, level));
|
2012-11-05 01:21:30 +08:00
|
|
|
|
|
|
|
/* This next bit makes the above posting read even more important. We
|
|
|
|
* want to flush the TLBs only after we're certain all the PTE updates
|
|
|
|
* have finished.
|
|
|
|
*/
|
|
|
|
I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
|
|
|
|
POSTING_READ(GFX_FLSH_CNTL_GEN6);
|
2012-11-05 01:21:27 +08:00
|
|
|
}
|
|
|
|
|
2012-02-16 06:50:21 +08:00
|
|
|
void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
|
|
|
|
enum i915_cache_level cache_level)
|
2011-04-14 13:48:26 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = obj->base.dev;
|
2012-11-05 01:21:27 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 6) {
|
|
|
|
unsigned int flags = (cache_level == I915_CACHE_NONE) ?
|
|
|
|
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
|
|
|
|
intel_gtt_insert_sg_entries(obj->pages,
|
|
|
|
obj->gtt_space->start >> PAGE_SHIFT,
|
|
|
|
flags);
|
|
|
|
} else {
|
|
|
|
gen6_ggtt_bind_object(obj, cache_level);
|
|
|
|
}
|
2011-04-14 13:48:26 +08:00
|
|
|
|
2012-02-16 06:50:22 +08:00
|
|
|
obj->has_global_gtt_mapping = 1;
|
2011-04-14 13:48:26 +08:00
|
|
|
}
|
|
|
|
|
2010-11-09 03:18:58 +08:00
|
|
|
void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
|
2012-02-16 06:50:21 +08:00
|
|
|
{
|
2012-11-05 01:21:27 +08:00
|
|
|
i915_ggtt_clear_range(obj->base.dev,
|
|
|
|
obj->gtt_space->start >> PAGE_SHIFT,
|
2012-02-16 06:50:21 +08:00
|
|
|
obj->base.size >> PAGE_SHIFT);
|
2012-02-16 06:50:22 +08:00
|
|
|
|
|
|
|
obj->has_global_gtt_mapping = 0;
|
2012-02-16 06:50:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
|
2010-11-06 17:10:47 +08:00
|
|
|
{
|
2011-10-18 06:51:55 +08:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
bool interruptible;
|
|
|
|
|
|
|
|
interruptible = do_idling(dev_priv);
|
|
|
|
|
2012-06-01 22:20:22 +08:00
|
|
|
if (!obj->has_dma_mapping)
|
|
|
|
dma_unmap_sg(&dev->pdev->dev,
|
|
|
|
obj->pages->sgl, obj->pages->nents,
|
|
|
|
PCI_DMA_BIDIRECTIONAL);
|
2011-10-18 06:51:55 +08:00
|
|
|
|
|
|
|
undo_idling(dev_priv, interruptible);
|
2010-11-06 17:10:47 +08:00
|
|
|
}
|
2012-03-26 15:45:40 +08:00
|
|
|
|
2012-07-26 18:49:32 +08:00
|
|
|
static void i915_gtt_color_adjust(struct drm_mm_node *node,
|
|
|
|
unsigned long color,
|
|
|
|
unsigned long *start,
|
|
|
|
unsigned long *end)
|
|
|
|
{
|
|
|
|
if (node->color != color)
|
|
|
|
*start += 4096;
|
|
|
|
|
|
|
|
if (!list_empty(&node->node_list)) {
|
|
|
|
node = list_entry(node->node_list.next,
|
|
|
|
struct drm_mm_node,
|
|
|
|
node_list);
|
|
|
|
if (node->allocated && node->color != color)
|
|
|
|
*end -= 4096;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-12-19 02:31:25 +08:00
|
|
|
void i915_gem_setup_global_gtt(struct drm_device *dev,
|
|
|
|
unsigned long start,
|
|
|
|
unsigned long mappable_end,
|
|
|
|
unsigned long end)
|
2012-03-26 15:45:40 +08:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2012-11-15 19:32:19 +08:00
|
|
|
struct drm_mm_node *entry;
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
unsigned long hole_start, hole_end;
|
2012-03-26 15:45:40 +08:00
|
|
|
|
2013-01-18 04:45:13 +08:00
|
|
|
BUG_ON(mappable_end > end);
|
|
|
|
|
2012-11-15 19:32:19 +08:00
|
|
|
/* Subtract the guard page ... */
|
2012-03-26 15:45:42 +08:00
|
|
|
drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
|
2012-07-26 18:49:32 +08:00
|
|
|
if (!HAS_LLC(dev))
|
|
|
|
dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
|
2012-03-26 15:45:40 +08:00
|
|
|
|
2012-11-15 19:32:19 +08:00
|
|
|
/* Mark any preallocated objects as occupied */
|
|
|
|
list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
|
|
|
|
DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
|
|
|
|
obj->gtt_offset, obj->base.size);
|
|
|
|
|
|
|
|
BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
|
|
|
|
obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
|
|
|
|
obj->gtt_offset,
|
|
|
|
obj->base.size,
|
|
|
|
false);
|
|
|
|
obj->has_global_gtt_mapping = 1;
|
|
|
|
}
|
|
|
|
|
2012-03-26 15:45:40 +08:00
|
|
|
dev_priv->mm.gtt_start = start;
|
|
|
|
dev_priv->mm.gtt_mappable_end = mappable_end;
|
|
|
|
dev_priv->mm.gtt_total = end - start;
|
|
|
|
|
2012-11-15 19:32:19 +08:00
|
|
|
/* Clear any non-preallocated blocks */
|
|
|
|
drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
|
|
|
|
hole_start, hole_end) {
|
|
|
|
DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
|
|
|
|
hole_start, hole_end);
|
|
|
|
i915_ggtt_clear_range(dev,
|
|
|
|
hole_start / PAGE_SIZE,
|
|
|
|
(hole_end-hole_start) / PAGE_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* And finally clear the reserved guard page */
|
|
|
|
i915_ggtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
|
2012-11-05 01:21:27 +08:00
|
|
|
}
|
|
|
|
|
2012-12-19 02:31:25 +08:00
|
|
|
static bool
|
|
|
|
intel_enable_ppgtt(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
if (i915_enable_ppgtt >= 0)
|
|
|
|
return i915_enable_ppgtt;
|
|
|
|
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
|
|
/* Disable ppgtt on SNB if VT-d is on. */
|
|
|
|
if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
|
|
|
|
return false;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_gem_init_global_gtt(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
unsigned long gtt_size, mappable_size;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
|
|
|
|
mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
|
|
|
|
|
|
|
|
if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
|
|
|
|
/* PPGTT pdes are stolen from global gtt ptes, so shrink the
|
|
|
|
* aperture accordingly when using aliasing ppgtt. */
|
|
|
|
gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
|
|
|
|
|
|
|
|
i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
|
|
|
|
|
|
|
|
ret = i915_gem_init_aliasing_ppgtt(dev);
|
|
|
|
if (ret) {
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Let GEM Manage all of the aperture.
|
|
|
|
*
|
|
|
|
* However, leave one page at the end still bound to the scratch
|
|
|
|
* page. There are a number of places where the hardware
|
|
|
|
* apparently prefetches past the end of the object, and we've
|
|
|
|
* seen multiple hangs with the GPU head pointer stuck in a
|
|
|
|
* batchbuffer bound at the last page of the aperture. One page
|
|
|
|
* should be enough to keep any prefetching inside of the
|
|
|
|
* aperture.
|
|
|
|
*/
|
|
|
|
i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
|
|
|
|
}
|
2012-11-05 01:21:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int setup_scratch_page(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct page *page;
|
|
|
|
dma_addr_t dma_addr;
|
|
|
|
|
|
|
|
page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
|
|
|
|
if (page == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
get_page(page);
|
|
|
|
set_pages_uc(page, 1);
|
|
|
|
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
|
|
dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
|
|
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
|
|
if (pci_dma_mapping_error(dev->pdev, dma_addr))
|
|
|
|
return -EINVAL;
|
|
|
|
#else
|
|
|
|
dma_addr = page_to_phys(page);
|
|
|
|
#endif
|
|
|
|
dev_priv->mm.gtt->scratch_page = page;
|
|
|
|
dev_priv->mm.gtt->scratch_page_dma = dma_addr;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void teardown_scratch_page(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
set_pages_wb(dev_priv->mm.gtt->scratch_page, 1);
|
|
|
|
pci_unmap_page(dev->pdev, dev_priv->mm.gtt->scratch_page_dma,
|
|
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
|
|
put_page(dev_priv->mm.gtt->scratch_page);
|
|
|
|
__free_page(dev_priv->mm.gtt->scratch_page);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
|
|
|
|
{
|
|
|
|
snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
|
|
|
|
snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
|
|
|
|
return snb_gmch_ctl << 20;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl)
|
|
|
|
{
|
|
|
|
snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
|
|
|
|
snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
|
|
|
|
return snb_gmch_ctl << 25; /* 32 MB units */
|
|
|
|
}
|
|
|
|
|
2012-11-05 01:21:28 +08:00
|
|
|
static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl)
|
|
|
|
{
|
|
|
|
static const int stolen_decoder[] = {
|
|
|
|
0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
|
|
|
|
snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
|
|
|
|
snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
|
|
|
|
return stolen_decoder[snb_gmch_ctl] << 20;
|
|
|
|
}
|
|
|
|
|
2012-11-05 01:21:27 +08:00
|
|
|
int i915_gem_gtt_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
phys_addr_t gtt_bus_addr;
|
|
|
|
u16 snb_gmch_ctl;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* On modern platforms we need not worry ourself with the legacy
|
|
|
|
* hostbridge query stuff. Skip it entirely
|
|
|
|
*/
|
|
|
|
if (INTEL_INFO(dev)->gen < 6) {
|
|
|
|
ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL);
|
|
|
|
if (!ret) {
|
|
|
|
DRM_ERROR("failed to set up gmch\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_priv->mm.gtt = intel_gtt_get();
|
|
|
|
if (!dev_priv->mm.gtt) {
|
|
|
|
DRM_ERROR("Failed to initialize GTT\n");
|
|
|
|
intel_gmch_remove();
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_priv->mm.gtt = kzalloc(sizeof(*dev_priv->mm.gtt), GFP_KERNEL);
|
|
|
|
if (!dev_priv->mm.gtt)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
|
|
|
|
pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
|
|
|
|
|
2012-12-13 23:47:47 +08:00
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
|
|
dev_priv->mm.gtt->needs_dmar = 1;
|
|
|
|
#endif
|
|
|
|
|
2012-11-05 01:21:27 +08:00
|
|
|
/* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
|
2012-11-20 04:23:44 +08:00
|
|
|
gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20);
|
|
|
|
dev_priv->mm.gtt->gma_bus_addr = pci_resource_start(dev->pdev, 2);
|
2012-11-05 01:21:27 +08:00
|
|
|
|
|
|
|
/* i9xx_setup */
|
|
|
|
pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
|
|
|
|
dev_priv->mm.gtt->gtt_total_entries =
|
|
|
|
gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t);
|
2012-11-05 01:21:28 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 7)
|
|
|
|
dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
|
|
|
|
else
|
|
|
|
dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl);
|
2012-11-05 01:21:27 +08:00
|
|
|
|
|
|
|
dev_priv->mm.gtt->gtt_mappable_entries = pci_resource_len(dev->pdev, 2) >> PAGE_SHIFT;
|
|
|
|
/* 64/512MB is the current min/max we actually know of, but this is just a
|
|
|
|
* coarse sanity check.
|
|
|
|
*/
|
|
|
|
if ((dev_priv->mm.gtt->gtt_mappable_entries >> 8) < 64 ||
|
|
|
|
dev_priv->mm.gtt->gtt_mappable_entries > dev_priv->mm.gtt->gtt_total_entries) {
|
|
|
|
DRM_ERROR("Unknown GMADR entries (%d)\n",
|
|
|
|
dev_priv->mm.gtt->gtt_mappable_entries);
|
|
|
|
ret = -ENXIO;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = setup_scratch_page(dev);
|
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("Scratch setup failed\n");
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
2012-12-19 02:31:26 +08:00
|
|
|
dev_priv->mm.gsm = ioremap_wc(gtt_bus_addr,
|
|
|
|
dev_priv->mm.gtt->gtt_total_entries * sizeof(gtt_pte_t));
|
|
|
|
if (!dev_priv->mm.gsm) {
|
2012-11-05 01:21:27 +08:00
|
|
|
DRM_ERROR("Failed to map the gtt page table\n");
|
|
|
|
teardown_scratch_page(dev);
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */
|
2012-11-11 17:34:45 +08:00
|
|
|
DRM_INFO("Memory usable by graphics device = %dM\n", dev_priv->mm.gtt->gtt_total_entries >> 8);
|
2012-11-05 01:21:27 +08:00
|
|
|
DRM_DEBUG_DRIVER("GMADR size = %dM\n", dev_priv->mm.gtt->gtt_mappable_entries >> 8);
|
|
|
|
DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv->mm.gtt->stolen_size >> 20);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out:
|
|
|
|
kfree(dev_priv->mm.gtt);
|
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
|
|
|
intel_gmch_remove();
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_gem_gtt_fini(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-12-19 02:31:26 +08:00
|
|
|
iounmap(dev_priv->mm.gsm);
|
2012-11-05 01:21:27 +08:00
|
|
|
teardown_scratch_page(dev);
|
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
|
|
|
intel_gmch_remove();
|
|
|
|
kfree(dev_priv->mm.gtt);
|
2012-03-26 15:45:40 +08:00
|
|
|
}
|