openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity
linux/arch/arm/mach-tegra/sleep.S

63 lines
1.6 KiB
ArmAsm
Raw Normal View History

ARM: tegra: assembler code for LP3 Configure the flow controller for clockgating and enter WFI Based on work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-01-27 00:22:02 +08:00
/*
* arch/arm/mach-tegra/sleep.S
*
* Copyright (c) 2010-2011, NVIDIA Corporation.
* Copyright (c) 2011, Google, Inc.
*
* Author: Colin Cross <ccross@android.com>
* Gary King <gking@nvidia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <linux/linkage.h>
ARM: tegra: Include assembler.h in sleep.S to fix build break Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's sleep.S to do so. This fixes: arch/arm/mach-tegra/sleep.S: Assembler messages: arch/arm/mach-tegra/sleep.S:77: Error: missing ')' arch/arm/mach-tegra/sleep.S:77: Error: garbage following instruction -- `movw r0,#:lower16:(0x60007000-0x60000000+IOMEM(0xFE200000))' Note: This only shows up after 0a25893 "ARM: tegra: update defconfig" Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2012-03-19 23:55:12 +08:00
#include <asm/assembler.h>
ARM: tegra30: cpuidle: add powered-down state for secondary CPUs This supports power-gated idle on secondary CPUs for Tegra30. The secondary CPUs can go into powered-down state independently. When CPU goes into this state, it saves it's contexts and puts itself to flow controlled WFI state. After that, it will been power gated. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 17:41:17 +08:00
#include <asm/cp15.h>
ARM: tegra: Include assembler.h in sleep.S to fix build break Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's sleep.S to do so. This fixes: arch/arm/mach-tegra/sleep.S: Assembler messages: arch/arm/mach-tegra/sleep.S:77: Error: missing ')' arch/arm/mach-tegra/sleep.S:77: Error: garbage following instruction -- `movw r0,#:lower16:(0x60007000-0x60000000+IOMEM(0xFE200000))' Note: This only shows up after 0a25893 "ARM: tegra: update defconfig" Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2012-03-19 23:55:12 +08:00
ARM: tegra: move iomap.h to mach-tegra Nothing outside mach-tegra uses this file, so there's no need for it to be in <mach/>. Since uncompress.h and debug-macro.S remain in include/mach, they need to include "../../iomap.h" becaue of this change. uncompress.h will soon be deleted in later multi-platform/single-zImage patches. debug-macro.S will need to continue to include this header using an explicit relative path, to avoid duplicating the physical->virtual address mapping that iomap.h dictates. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-05 04:24:09 +08:00
#include "iomap.h"
ARM: tegra: assembler code for LP3 Configure the flow controller for clockgating and enter WFI Based on work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-01-27 00:22:02 +08:00
#include "flowctrl.h"
ARM: tegra: clean up the common assembly macros into sleep.h There are some common macros for Tegra low-level assembly code. Clean up them into one header file and move the definitions that will be re-used into it as well. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-08-16 17:31:50 +08:00
#include "sleep.h"
ARM: tegra: assembler code for LP3 Configure the flow controller for clockgating and enter WFI Based on work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-01-27 00:22:02 +08:00
ARM: tegra30: cpuidle: add powered-down state for secondary CPUs This supports power-gated idle on secondary CPUs for Tegra30. The secondary CPUs can go into powered-down state independently. When CPU goes into this state, it saves it's contexts and puts itself to flow controlled WFI state. After that, it will been power gated. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 17:41:17 +08:00
#ifdef CONFIG_PM_SLEEP
/*
* tegra_disable_clean_inv_dcache
*
* disable, clean & invalidate the D-cache
*
* Corrupted registers: r1-r3, r6, r8, r9-r11
*/
ENTRY(tegra_disable_clean_inv_dcache)
stmfd sp!, {r0, r4-r5, r7, r9-r11, lr}
dmb @ ensure ordering
/* Disable the D-cache */
mrc p15, 0, r2, c1, c0, 0
bic r2, r2, #CR_C
mcr p15, 0, r2, c1, c0, 0
isb
/* Flush the D-cache */
bl v7_flush_dcache_louis
/* Trun off coherency */
exit_smp r4, r5
ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
ENDPROC(tegra_disable_clean_inv_dcache)
#endif