mirror of https://gitee.com/openkylin/linux.git
290 lines
6.3 KiB
ArmAsm
290 lines
6.3 KiB
ArmAsm
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/* MN10300 CPU core caching routines
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/smp.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#define mn10300_dcache_inv_range_intr_interval \
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+((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1)
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#if mn10300_dcache_inv_range_intr_interval > 0xff
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#error MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL must be 8 or less
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#endif
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.am33_2
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.globl mn10300_icache_inv
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.globl mn10300_dcache_inv
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.globl mn10300_dcache_inv_range
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.globl mn10300_dcache_inv_range2
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.globl mn10300_dcache_inv_page
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###############################################################################
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#
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# void mn10300_icache_inv(void)
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# Invalidate the entire icache
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#
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###############################################################################
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ALIGN
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mn10300_icache_inv:
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mov CHCTR,a0
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movhu (a0),d0
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btst CHCTR_ICEN,d0
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beq mn10300_icache_inv_end
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mov epsw,d1
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and ~EPSW_IE,epsw
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nop
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nop
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# disable the icache
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and ~CHCTR_ICEN,d0
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movhu d0,(a0)
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# and wait for it to calm down
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setlb
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movhu (a0),d0
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btst CHCTR_ICBUSY,d0
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lne
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# invalidate
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or CHCTR_ICINV,d0
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movhu d0,(a0)
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# wait for the cache to finish
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mov CHCTR,a0
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setlb
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movhu (a0),d0
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btst CHCTR_ICBUSY,d0
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lne
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# and reenable it
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and ~CHCTR_ICINV,d0
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or CHCTR_ICEN,d0
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movhu d0,(a0)
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movhu (a0),d0
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mov d1,epsw
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mn10300_icache_inv_end:
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ret [],0
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###############################################################################
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#
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# void mn10300_dcache_inv(void)
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# Invalidate the entire dcache
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#
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###############################################################################
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ALIGN
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mn10300_dcache_inv:
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mov CHCTR,a0
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movhu (a0),d0
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btst CHCTR_DCEN,d0
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beq mn10300_dcache_inv_end
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mov epsw,d1
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and ~EPSW_IE,epsw
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nop
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nop
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# disable the dcache
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and ~CHCTR_DCEN,d0
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movhu d0,(a0)
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# and wait for it to calm down
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setlb
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movhu (a0),d0
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btst CHCTR_DCBUSY,d0
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lne
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# invalidate
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or CHCTR_DCINV,d0
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movhu d0,(a0)
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# wait for the cache to finish
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mov CHCTR,a0
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setlb
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movhu (a0),d0
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btst CHCTR_DCBUSY,d0
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lne
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# and reenable it
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and ~CHCTR_DCINV,d0
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or CHCTR_DCEN,d0
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movhu d0,(a0)
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movhu (a0),d0
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mov d1,epsw
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mn10300_dcache_inv_end:
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ret [],0
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###############################################################################
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#
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# void mn10300_dcache_inv_range(unsigned start, unsigned end)
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# void mn10300_dcache_inv_range2(unsigned start, unsigned size)
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# void mn10300_dcache_inv_page(unsigned start)
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# Invalidate a range of addresses on a page in the dcache
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#
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###############################################################################
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ALIGN
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mn10300_dcache_inv_page:
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mov PAGE_SIZE,d1
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mn10300_dcache_inv_range2:
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add d0,d1
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mn10300_dcache_inv_range:
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movm [d2,d3,a2],(sp)
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mov CHCTR,a2
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movhu (a2),d2
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btst CHCTR_DCEN,d2
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beq mn10300_dcache_inv_range_end
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and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start
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# addr down
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mov d0,a1
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add L1_CACHE_BYTES,d1 # round end addr up
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and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1
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clr d2 # we're going to clear tag ram
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# entries
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# read the tags from the tag RAM, and if they indicate a valid dirty
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# cache line then invalidate that line
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mov DCACHE_TAG(0,0),a0
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mov a1,d0
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and L1_CACHE_TAG_ENTRY,d0
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add d0,a0 # starting dcache tag RAM
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# access address
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sub a1,d1
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lsr L1_CACHE_SHIFT,d1 # total number of entries to
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# examine
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and ~(L1_CACHE_DISPARITY-1),a1 # determine comparator base
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mn10300_dcache_inv_range_outer_loop:
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# disable interrupts
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mov epsw,d3
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and ~EPSW_IE,epsw
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nop # note that reading CHCTR and
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# AND'ing D0 occupy two delay
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# slots after disabling
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# interrupts
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# disable the dcache
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movhu (a2),d0
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and ~CHCTR_DCEN,d0
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movhu d0,(a2)
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# and wait for it to calm down
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setlb
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movhu (a2),d0
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btst CHCTR_DCBUSY,d0
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lne
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mn10300_dcache_inv_range_loop:
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# process the way 0 slot
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mov (L1_CACHE_WAYDISP*0,a0),d0 # read the tag in the way 0 slot
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btst L1_CACHE_TAG_VALID,d0
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beq mn10300_dcache_inv_range_skip_0 # jump if this cacheline is not
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# valid
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xor a1,d0
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lsr 12,d0
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bne mn10300_dcache_inv_range_skip_0 # jump if not this cacheline
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mov d2,(a0) # kill the tag
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mn10300_dcache_inv_range_skip_0:
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# process the way 1 slot
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mov (L1_CACHE_WAYDISP*1,a0),d0 # read the tag in the way 1 slot
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btst L1_CACHE_TAG_VALID,d0
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beq mn10300_dcache_inv_range_skip_1 # jump if this cacheline is not
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# valid
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xor a1,d0
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lsr 12,d0
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bne mn10300_dcache_inv_range_skip_1 # jump if not this cacheline
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mov d2,(a0) # kill the tag
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mn10300_dcache_inv_range_skip_1:
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# process the way 2 slot
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mov (L1_CACHE_WAYDISP*2,a0),d0 # read the tag in the way 2 slot
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btst L1_CACHE_TAG_VALID,d0
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beq mn10300_dcache_inv_range_skip_2 # jump if this cacheline is not
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# valid
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xor a1,d0
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lsr 12,d0
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bne mn10300_dcache_inv_range_skip_2 # jump if not this cacheline
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mov d2,(a0) # kill the tag
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mn10300_dcache_inv_range_skip_2:
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# process the way 3 slot
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mov (L1_CACHE_WAYDISP*3,a0),d0 # read the tag in the way 3 slot
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btst L1_CACHE_TAG_VALID,d0
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beq mn10300_dcache_inv_range_skip_3 # jump if this cacheline is not
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# valid
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xor a1,d0
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lsr 12,d0
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bne mn10300_dcache_inv_range_skip_3 # jump if not this cacheline
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mov d2,(a0) # kill the tag
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mn10300_dcache_inv_range_skip_3:
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# approx every N steps we re-enable the cache and see if there are any
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# interrupts to be processed
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# we also break out if we've reached the end of the loop
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# (the bottom nibble of the count is zero in both cases)
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add L1_CACHE_BYTES,a0
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add L1_CACHE_BYTES,a1
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add -1,d1
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btst mn10300_dcache_inv_range_intr_interval,d1
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bne mn10300_dcache_inv_range_loop
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# wait for the cache to finish what it's doing
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setlb
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movhu (a2),d0
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btst CHCTR_DCBUSY,d0
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lne
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# and reenable it
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or CHCTR_DCEN,d0
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movhu d0,(a2)
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movhu (a2),d0
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# re-enable interrupts
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# - we don't bother with delay NOPs as we'll have enough instructions
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# before we disable interrupts again to give the interrupts a chance
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# to happen
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mov d3,epsw
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# go around again if the counter hasn't yet reached zero
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add 0,d1
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bne mn10300_dcache_inv_range_outer_loop
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mn10300_dcache_inv_range_end:
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ret [d2,d3,a2],12
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