2013-12-21 03:09:15 +08:00
|
|
|
/dts-v1/;
|
|
|
|
|
|
|
|
#include "skeleton.dtsi"
|
|
|
|
|
2014-01-17 09:25:03 +08:00
|
|
|
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
|
|
|
|
|
2013-12-21 03:09:15 +08:00
|
|
|
/ {
|
|
|
|
model = "Qualcomm MSM8974";
|
|
|
|
compatible = "qcom,msm8974";
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
|
|
|
|
soc: soc {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
ranges;
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
|
|
|
intc: interrupt-controller@f9000000 {
|
|
|
|
compatible = "qcom,msm-qgic2";
|
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <3>;
|
|
|
|
reg = <0xf9000000 0x1000>,
|
|
|
|
<0xf9002000 0x1000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
timer {
|
|
|
|
compatible = "arm,armv7-timer";
|
|
|
|
interrupts = <1 2 0xf08>,
|
|
|
|
<1 3 0xf08>,
|
|
|
|
<1 4 0xf08>,
|
|
|
|
<1 1 0xf08>;
|
|
|
|
clock-frequency = <19200000>;
|
|
|
|
};
|
2013-12-21 03:09:18 +08:00
|
|
|
|
2013-12-21 03:09:19 +08:00
|
|
|
timer@f9020000 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
ranges;
|
|
|
|
compatible = "arm,armv7-timer-mem";
|
|
|
|
reg = <0xf9020000 0x1000>;
|
|
|
|
clock-frequency = <19200000>;
|
|
|
|
|
|
|
|
frame@f9021000 {
|
|
|
|
frame-number = <0>;
|
|
|
|
interrupts = <0 8 0x4>,
|
|
|
|
<0 7 0x4>;
|
|
|
|
reg = <0xf9021000 0x1000>,
|
|
|
|
<0xf9022000 0x1000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
frame@f9023000 {
|
|
|
|
frame-number = <1>;
|
|
|
|
interrupts = <0 9 0x4>;
|
|
|
|
reg = <0xf9023000 0x1000>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
frame@f9024000 {
|
|
|
|
frame-number = <2>;
|
|
|
|
interrupts = <0 10 0x4>;
|
|
|
|
reg = <0xf9024000 0x1000>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
frame@f9025000 {
|
|
|
|
frame-number = <3>;
|
|
|
|
interrupts = <0 11 0x4>;
|
|
|
|
reg = <0xf9025000 0x1000>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
frame@f9026000 {
|
|
|
|
frame-number = <4>;
|
|
|
|
interrupts = <0 12 0x4>;
|
|
|
|
reg = <0xf9026000 0x1000>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
frame@f9027000 {
|
|
|
|
frame-number = <5>;
|
|
|
|
interrupts = <0 13 0x4>;
|
|
|
|
reg = <0xf9027000 0x1000>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
frame@f9028000 {
|
|
|
|
frame-number = <6>;
|
|
|
|
interrupts = <0 14 0x4>;
|
|
|
|
reg = <0xf9028000 0x1000>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2013-12-21 03:09:18 +08:00
|
|
|
restart@fc4ab000 {
|
|
|
|
compatible = "qcom,pshold";
|
|
|
|
reg = <0xfc4ab000 0x4>;
|
|
|
|
};
|
2014-01-17 09:25:03 +08:00
|
|
|
|
|
|
|
gcc: clock-controller@fc400000 {
|
|
|
|
compatible = "qcom,gcc-msm8974";
|
|
|
|
#clock-cells = <1>;
|
|
|
|
#reset-cells = <1>;
|
|
|
|
reg = <0xfc400000 0x4000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
mmcc: clock-controller@fd8c0000 {
|
|
|
|
compatible = "qcom,mmcc-msm8974";
|
|
|
|
#clock-cells = <1>;
|
|
|
|
#reset-cells = <1>;
|
|
|
|
reg = <0xfd8c0000 0x6000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
serial@f991e000 {
|
|
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
|
|
reg = <0xf991e000 0x1000>;
|
|
|
|
interrupts = <0 108 0x0>;
|
|
|
|
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
|
|
|
clock-names = "core", "iface";
|
|
|
|
};
|
2013-12-21 03:09:15 +08:00
|
|
|
};
|
|
|
|
};
|