2013-02-04 13:46:29 +08:00
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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2013-09-11 01:59:47 +08:00
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#include <linux/cpu.h>
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2013-02-04 13:46:29 +08:00
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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2013-09-20 05:03:52 +08:00
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#include <linux/pm_opp.h>
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2013-02-04 13:46:29 +08:00
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#define PU_SOC_VOLTAGE_NORMAL 1250000
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#define PU_SOC_VOLTAGE_HIGH 1275000
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#define FREQ_1P2_GHZ 1200000000
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static struct regulator *arm_reg;
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static struct regulator *pu_reg;
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static struct regulator *soc_reg;
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static struct clk *arm_clk;
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static struct clk *pll1_sys_clk;
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static struct clk *pll1_sw_clk;
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static struct clk *step_clk;
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static struct clk *pll2_pfd2_396m_clk;
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2015-09-11 23:41:05 +08:00
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/* clk used by i.MX6UL */
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static struct clk *pll2_bus_clk;
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static struct clk *secondary_sel_clk;
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2013-02-04 13:46:29 +08:00
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static struct device *cpu_dev;
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2014-11-25 18:34:23 +08:00
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static bool free_opp;
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2013-02-04 13:46:29 +08:00
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static struct cpufreq_frequency_table *freq_table;
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static unsigned int transition_latency;
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cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 22:16:47 +08:00
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static u32 *imx6_soc_volt;
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static u32 soc_opp_count;
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2013-10-25 22:15:48 +08:00
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static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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2013-02-04 13:46:29 +08:00
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{
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2013-09-20 05:03:51 +08:00
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struct dev_pm_opp *opp;
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2013-02-04 13:46:29 +08:00
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unsigned long freq_hz, volt, volt_old;
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2013-08-14 22:08:24 +08:00
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unsigned int old_freq, new_freq;
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2017-08-28 19:05:18 +08:00
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bool pll1_sys_temp_enabled = false;
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2013-02-04 13:46:29 +08:00
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int ret;
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2013-08-14 22:08:24 +08:00
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new_freq = freq_table[index].frequency;
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freq_hz = new_freq * 1000;
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old_freq = clk_get_rate(arm_clk) / 1000;
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2013-02-04 13:46:29 +08:00
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2013-09-20 05:03:50 +08:00
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
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2013-02-04 13:46:29 +08:00
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if (IS_ERR(opp)) {
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dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
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return PTR_ERR(opp);
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}
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2013-09-20 05:03:50 +08:00
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volt = dev_pm_opp_get_voltage(opp);
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2017-01-23 12:41:47 +08:00
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dev_pm_opp_put(opp);
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2013-02-04 13:46:29 +08:00
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volt_old = regulator_get_voltage(arm_reg);
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dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
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2013-08-14 22:08:24 +08:00
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old_freq / 1000, volt_old / 1000,
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new_freq / 1000, volt / 1000);
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2013-06-19 13:48:20 +08:00
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2013-02-04 13:46:29 +08:00
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/* scaling up? scale voltage before frequency */
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2013-08-14 22:08:24 +08:00
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if (new_freq > old_freq) {
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2014-06-20 15:42:18 +08:00
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if (!IS_ERR(pu_reg)) {
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ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
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if (ret) {
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dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
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return ret;
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}
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cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 22:16:47 +08:00
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}
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ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
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if (ret) {
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dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
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return ret;
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}
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2013-02-04 13:46:29 +08:00
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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if (ret) {
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dev_err(cpu_dev,
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"failed to scale vddarm up: %d\n", ret);
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2013-08-14 22:08:24 +08:00
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return ret;
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2013-02-04 13:46:29 +08:00
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}
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}
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/*
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* The setpoints are selected per PLL/PDF frequencies, so we need to
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* reprogram PLL for frequency scaling. The procedure of reprogramming
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* PLL1 is as below.
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2015-09-11 23:41:05 +08:00
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* For i.MX6UL, it has a secondary clk mux, the cpu frequency change
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* flow is slightly different from other i.MX6 OSC.
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* The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
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2013-02-04 13:46:29 +08:00
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* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
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* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
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* - Disable pll2_pfd2_396m_clk
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*/
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2017-05-30 23:57:18 +08:00
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if (of_machine_is_compatible("fsl,imx6ul") ||
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of_machine_is_compatible("fsl,imx6ull")) {
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2015-09-11 23:41:05 +08:00
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/*
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* When changing pll1_sw_clk's parent to pll1_sys_clk,
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* CPU may run at higher than 528MHz, this will lead to
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* the system unstable if the voltage is lower than the
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* voltage of 528MHz, so lower the CPU frequency to one
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* half before changing CPU frequency.
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*/
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clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
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2013-02-04 13:46:29 +08:00
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clk_set_parent(pll1_sw_clk, pll1_sys_clk);
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2015-09-11 23:41:05 +08:00
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if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
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clk_set_parent(secondary_sel_clk, pll2_bus_clk);
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else
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clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
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clk_set_parent(step_clk, secondary_sel_clk);
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clk_set_parent(pll1_sw_clk, step_clk);
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} else {
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clk_set_parent(step_clk, pll2_pfd2_396m_clk);
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clk_set_parent(pll1_sw_clk, step_clk);
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if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
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clk_set_rate(pll1_sys_clk, new_freq * 1000);
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clk_set_parent(pll1_sw_clk, pll1_sys_clk);
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2017-08-28 19:05:18 +08:00
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} else {
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/* pll1_sys needs to be enabled for divider rate change to work. */
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pll1_sys_temp_enabled = true;
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clk_prepare_enable(pll1_sys_clk);
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2015-09-11 23:41:05 +08:00
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}
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2013-02-04 13:46:29 +08:00
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}
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/* Ensure the arm clock divider is what we expect */
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2013-08-14 22:08:24 +08:00
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ret = clk_set_rate(arm_clk, new_freq * 1000);
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2013-02-04 13:46:29 +08:00
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if (ret) {
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dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
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regulator_set_voltage_tol(arm_reg, volt_old, 0);
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2013-08-14 22:08:24 +08:00
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return ret;
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2013-02-04 13:46:29 +08:00
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}
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2017-08-28 19:05:18 +08:00
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/* PLL1 is only needed until after ARM-PODF is set. */
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if (pll1_sys_temp_enabled)
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clk_disable_unprepare(pll1_sys_clk);
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2013-02-04 13:46:29 +08:00
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/* scaling down? scale voltage after frequency */
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2013-08-14 22:08:24 +08:00
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if (new_freq < old_freq) {
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2013-02-04 13:46:29 +08:00
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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2013-06-19 13:48:20 +08:00
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if (ret) {
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2013-02-04 13:46:29 +08:00
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dev_warn(cpu_dev,
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"failed to scale vddarm down: %d\n", ret);
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2013-06-19 13:48:20 +08:00
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ret = 0;
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}
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cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 22:16:47 +08:00
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ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
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if (ret) {
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dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
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ret = 0;
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}
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2014-06-20 15:42:18 +08:00
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if (!IS_ERR(pu_reg)) {
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ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
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if (ret) {
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dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
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ret = 0;
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}
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2013-02-04 13:46:29 +08:00
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}
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}
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2013-08-14 22:08:24 +08:00
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return 0;
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2013-02-04 13:46:29 +08:00
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}
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static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
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{
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2017-04-05 01:04:12 +08:00
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int ret;
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2014-01-09 23:08:43 +08:00
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policy->clk = arm_clk;
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2017-04-05 01:04:12 +08:00
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ret = cpufreq_generic_init(policy, freq_table, transition_latency);
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policy->suspend_freq = policy->max;
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return ret;
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2013-02-04 13:46:29 +08:00
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}
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static struct cpufreq_driver imx6q_cpufreq_driver = {
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2013-12-03 13:50:45 +08:00
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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2013-10-03 22:58:08 +08:00
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.verify = cpufreq_generic_frequency_table_verify,
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2013-10-25 22:15:48 +08:00
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.target_index = imx6q_set_target,
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2014-01-09 23:08:43 +08:00
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.get = cpufreq_generic_get,
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2013-02-04 13:46:29 +08:00
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.init = imx6q_cpufreq_init,
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.name = "imx6q-cpufreq",
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2013-10-03 22:58:08 +08:00
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.attr = cpufreq_generic_attr,
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2017-04-05 01:04:12 +08:00
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.suspend = cpufreq_generic_suspend,
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2013-02-04 13:46:29 +08:00
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};
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static int imx6q_cpufreq_probe(struct platform_device *pdev)
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{
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struct device_node *np;
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2013-09-20 05:03:51 +08:00
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struct dev_pm_opp *opp;
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2013-02-04 13:46:29 +08:00
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unsigned long min_volt, max_volt;
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int num, ret;
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cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 22:16:47 +08:00
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const struct property *prop;
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const __be32 *val;
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u32 nr, i, j;
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2013-02-04 13:46:29 +08:00
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2013-09-11 01:59:47 +08:00
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cpu_dev = get_cpu_device(0);
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if (!cpu_dev) {
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pr_err("failed to get cpu0 device\n");
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return -ENODEV;
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}
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2013-02-04 13:46:29 +08:00
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2013-06-17 21:58:48 +08:00
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np = of_node_get(cpu_dev->of_node);
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2013-02-04 13:46:29 +08:00
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if (!np) {
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dev_err(cpu_dev, "failed to find cpu0 node\n");
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return -ENOENT;
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}
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2014-05-15 00:02:23 +08:00
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arm_clk = clk_get(cpu_dev, "arm");
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pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
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pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
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step_clk = clk_get(cpu_dev, "step");
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pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
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2013-02-04 13:46:29 +08:00
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if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
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IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
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dev_err(cpu_dev, "failed to get clocks\n");
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ret = -ENOENT;
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2014-05-15 00:02:23 +08:00
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goto put_clk;
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2013-02-04 13:46:29 +08:00
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}
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2017-05-30 23:57:18 +08:00
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if (of_machine_is_compatible("fsl,imx6ul") ||
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of_machine_is_compatible("fsl,imx6ull")) {
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2015-09-11 23:41:05 +08:00
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pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
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secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
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if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {
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dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
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ret = -ENOENT;
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goto put_clk;
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}
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}
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2014-05-15 00:02:23 +08:00
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arm_reg = regulator_get(cpu_dev, "arm");
|
2014-06-20 15:42:18 +08:00
|
|
|
pu_reg = regulator_get_optional(cpu_dev, "pu");
|
2014-05-15 00:02:23 +08:00
|
|
|
soc_reg = regulator_get(cpu_dev, "soc");
|
2017-04-05 01:04:11 +08:00
|
|
|
if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
|
|
|
|
PTR_ERR(soc_reg) == -EPROBE_DEFER ||
|
|
|
|
PTR_ERR(pu_reg) == -EPROBE_DEFER) {
|
|
|
|
ret = -EPROBE_DEFER;
|
|
|
|
dev_dbg(cpu_dev, "regulators not ready, defer\n");
|
|
|
|
goto put_reg;
|
|
|
|
}
|
2014-06-20 15:42:18 +08:00
|
|
|
if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
|
2013-02-04 13:46:29 +08:00
|
|
|
dev_err(cpu_dev, "failed to get regulators\n");
|
|
|
|
ret = -ENOENT;
|
2014-05-15 00:02:23 +08:00
|
|
|
goto put_reg;
|
2013-02-04 13:46:29 +08:00
|
|
|
}
|
|
|
|
|
2013-12-20 14:56:28 +08:00
|
|
|
/*
|
|
|
|
* We expect an OPP table supplied by platform.
|
|
|
|
* Just, incase the platform did not supply the OPP
|
|
|
|
* table, it will try to get it.
|
|
|
|
*/
|
2013-09-20 05:03:50 +08:00
|
|
|
num = dev_pm_opp_get_opp_count(cpu_dev);
|
2013-02-04 13:46:29 +08:00
|
|
|
if (num < 0) {
|
2015-09-04 16:17:24 +08:00
|
|
|
ret = dev_pm_opp_of_add_table(cpu_dev);
|
2013-12-20 14:56:28 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
|
2014-05-15 00:02:23 +08:00
|
|
|
goto put_reg;
|
2013-12-20 14:56:28 +08:00
|
|
|
}
|
|
|
|
|
2014-11-25 18:34:23 +08:00
|
|
|
/* Because we have added the OPPs here, we must free them */
|
|
|
|
free_opp = true;
|
|
|
|
|
2013-12-20 14:56:28 +08:00
|
|
|
num = dev_pm_opp_get_opp_count(cpu_dev);
|
|
|
|
if (num < 0) {
|
|
|
|
ret = num;
|
|
|
|
dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
|
2014-11-25 18:34:23 +08:00
|
|
|
goto out_free_opp;
|
2013-12-20 14:56:28 +08:00
|
|
|
}
|
2013-02-04 13:46:29 +08:00
|
|
|
}
|
|
|
|
|
2013-09-20 05:03:50 +08:00
|
|
|
ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
|
2013-02-04 13:46:29 +08:00
|
|
|
if (ret) {
|
|
|
|
dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
|
2017-04-09 15:33:52 +08:00
|
|
|
goto out_free_opp;
|
2013-02-04 13:46:29 +08:00
|
|
|
}
|
|
|
|
|
cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 22:16:47 +08:00
|
|
|
/* Make imx6_soc_volt array's size same as arm opp number */
|
|
|
|
imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
|
|
|
|
if (imx6_soc_volt == NULL) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto free_freq_table;
|
|
|
|
}
|
|
|
|
|
|
|
|
prop = of_find_property(np, "fsl,soc-operating-points", NULL);
|
|
|
|
if (!prop || !prop->value)
|
|
|
|
goto soc_opp_out;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Each OPP is a set of tuples consisting of frequency and
|
|
|
|
* voltage like <freq-kHz vol-uV>.
|
|
|
|
*/
|
|
|
|
nr = prop->length / sizeof(u32);
|
|
|
|
if (nr % 2 || (nr / 2) < num)
|
|
|
|
goto soc_opp_out;
|
|
|
|
|
|
|
|
for (j = 0; j < num; j++) {
|
|
|
|
val = prop->value;
|
|
|
|
for (i = 0; i < nr / 2; i++) {
|
|
|
|
unsigned long freq = be32_to_cpup(val++);
|
|
|
|
unsigned long volt = be32_to_cpup(val++);
|
|
|
|
if (freq_table[j].frequency == freq) {
|
|
|
|
imx6_soc_volt[soc_opp_count++] = volt;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
soc_opp_out:
|
|
|
|
/* use fixed soc opp volt if no valid soc opp info found in dtb */
|
|
|
|
if (soc_opp_count != num) {
|
|
|
|
dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
|
|
|
|
for (j = 0; j < num; j++)
|
|
|
|
imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
|
|
|
|
if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
|
|
|
|
imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
|
|
|
|
}
|
|
|
|
|
2013-02-04 13:46:29 +08:00
|
|
|
if (of_property_read_u32(np, "clock-latency", &transition_latency))
|
|
|
|
transition_latency = CPUFREQ_ETERNAL;
|
|
|
|
|
cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 22:16:47 +08:00
|
|
|
/*
|
|
|
|
* Calculate the ramp time for max voltage change in the
|
|
|
|
* VDDSOC and VDDPU regulators.
|
|
|
|
*/
|
|
|
|
ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
|
|
|
|
if (ret > 0)
|
|
|
|
transition_latency += ret * 1000;
|
2014-06-20 15:42:18 +08:00
|
|
|
if (!IS_ERR(pu_reg)) {
|
|
|
|
ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
|
|
|
|
if (ret > 0)
|
|
|
|
transition_latency += ret * 1000;
|
|
|
|
}
|
cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 22:16:47 +08:00
|
|
|
|
2013-02-04 13:46:29 +08:00
|
|
|
/*
|
|
|
|
* OPP is maintained in order of increasing frequency, and
|
|
|
|
* freq_table initialised from OPP is therefore sorted in the
|
|
|
|
* same order.
|
|
|
|
*/
|
2013-09-20 05:03:50 +08:00
|
|
|
opp = dev_pm_opp_find_freq_exact(cpu_dev,
|
2013-02-04 13:46:29 +08:00
|
|
|
freq_table[0].frequency * 1000, true);
|
2013-09-20 05:03:50 +08:00
|
|
|
min_volt = dev_pm_opp_get_voltage(opp);
|
2017-01-23 12:41:47 +08:00
|
|
|
dev_pm_opp_put(opp);
|
2013-09-20 05:03:50 +08:00
|
|
|
opp = dev_pm_opp_find_freq_exact(cpu_dev,
|
2013-02-04 13:46:29 +08:00
|
|
|
freq_table[--num].frequency * 1000, true);
|
2013-09-20 05:03:50 +08:00
|
|
|
max_volt = dev_pm_opp_get_voltage(opp);
|
2017-01-23 12:41:47 +08:00
|
|
|
dev_pm_opp_put(opp);
|
|
|
|
|
2013-02-04 13:46:29 +08:00
|
|
|
ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
|
|
|
|
if (ret > 0)
|
|
|
|
transition_latency += ret * 1000;
|
|
|
|
|
|
|
|
ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(cpu_dev, "failed register driver: %d\n", ret);
|
|
|
|
goto free_freq_table;
|
|
|
|
}
|
|
|
|
|
|
|
|
of_node_put(np);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
free_freq_table:
|
2013-09-20 05:03:50 +08:00
|
|
|
dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
|
2014-11-25 18:34:23 +08:00
|
|
|
out_free_opp:
|
|
|
|
if (free_opp)
|
2015-09-04 16:17:24 +08:00
|
|
|
dev_pm_opp_of_remove_table(cpu_dev);
|
2014-05-15 00:02:23 +08:00
|
|
|
put_reg:
|
|
|
|
if (!IS_ERR(arm_reg))
|
|
|
|
regulator_put(arm_reg);
|
|
|
|
if (!IS_ERR(pu_reg))
|
|
|
|
regulator_put(pu_reg);
|
|
|
|
if (!IS_ERR(soc_reg))
|
|
|
|
regulator_put(soc_reg);
|
|
|
|
put_clk:
|
|
|
|
if (!IS_ERR(arm_clk))
|
|
|
|
clk_put(arm_clk);
|
|
|
|
if (!IS_ERR(pll1_sys_clk))
|
|
|
|
clk_put(pll1_sys_clk);
|
|
|
|
if (!IS_ERR(pll1_sw_clk))
|
|
|
|
clk_put(pll1_sw_clk);
|
|
|
|
if (!IS_ERR(step_clk))
|
|
|
|
clk_put(step_clk);
|
|
|
|
if (!IS_ERR(pll2_pfd2_396m_clk))
|
|
|
|
clk_put(pll2_pfd2_396m_clk);
|
2015-09-11 23:41:05 +08:00
|
|
|
if (!IS_ERR(pll2_bus_clk))
|
|
|
|
clk_put(pll2_bus_clk);
|
|
|
|
if (!IS_ERR(secondary_sel_clk))
|
|
|
|
clk_put(secondary_sel_clk);
|
2013-02-04 13:46:29 +08:00
|
|
|
of_node_put(np);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx6q_cpufreq_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
cpufreq_unregister_driver(&imx6q_cpufreq_driver);
|
2013-09-20 05:03:50 +08:00
|
|
|
dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
|
2014-11-25 18:34:23 +08:00
|
|
|
if (free_opp)
|
2015-09-04 16:17:24 +08:00
|
|
|
dev_pm_opp_of_remove_table(cpu_dev);
|
2014-05-15 00:02:23 +08:00
|
|
|
regulator_put(arm_reg);
|
2014-06-20 15:42:18 +08:00
|
|
|
if (!IS_ERR(pu_reg))
|
|
|
|
regulator_put(pu_reg);
|
2014-05-15 00:02:23 +08:00
|
|
|
regulator_put(soc_reg);
|
|
|
|
clk_put(arm_clk);
|
|
|
|
clk_put(pll1_sys_clk);
|
|
|
|
clk_put(pll1_sw_clk);
|
|
|
|
clk_put(step_clk);
|
|
|
|
clk_put(pll2_pfd2_396m_clk);
|
2015-09-11 23:41:05 +08:00
|
|
|
clk_put(pll2_bus_clk);
|
|
|
|
clk_put(secondary_sel_clk);
|
2013-02-04 13:46:29 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver imx6q_cpufreq_platdrv = {
|
|
|
|
.driver = {
|
|
|
|
.name = "imx6q-cpufreq",
|
|
|
|
},
|
|
|
|
.probe = imx6q_cpufreq_probe,
|
|
|
|
.remove = imx6q_cpufreq_remove,
|
|
|
|
};
|
|
|
|
module_platform_driver(imx6q_cpufreq_platdrv);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
|
|
|
|
MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
|
|
|
|
MODULE_LICENSE("GPL");
|