mirror of https://gitee.com/openkylin/linux.git
61 lines
1.4 KiB
YAML
61 lines
1.4 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas CPG DIV6 Clock
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description:
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The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
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Generator (CPG). Their clock input is divided by a configurable factor from 1
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to 64.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r8a73a4-div6-clock # R-Mobile APE6
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- renesas,r8a7740-div6-clock # R-Mobile A1
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- renesas,sh73a0-div6-clock # SH-Mobile AG5
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- const: renesas,cpg-div6-clock
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reg:
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maxItems: 1
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clocks:
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oneOf:
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- maxItems: 1
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- maxItems: 4
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- maxItems: 8
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description:
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For clocks with multiple parents, invalid settings must be specified as
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"<0>".
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'#clock-cells':
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const: 0
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clock-output-names: true
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a73a4-clock.h>
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sdhi2_clk: sdhi2_clk@e615007c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615007c 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
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<&extal2_clk>;
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#clock-cells = <0>;
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};
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