2010-10-19 15:08:12 +08:00
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/*
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* Texas Instruments AM35x "glue layer"
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*
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* Copyright (c) 2010, by Texas Instruments
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*
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* Based on the DA8xx "glue layer" code.
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* Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*
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* The Inventra Controller Driver for Linux is free software; you
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* can redistribute it and/or modify it under the terms of the GNU
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* General Public License version 2 as published by the Free Software
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* Foundation.
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*
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* The Inventra Controller Driver for Linux is distributed in
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* the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with The Inventra Controller Driver for Linux ; if not,
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* write to the Free Software Foundation, Inc., 59 Temple Place,
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* Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <plat/control.h>
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#include <plat/usb.h>
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#include "musb_core.h"
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/*
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* AM35x specific definitions
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*/
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/* USB 2.0 OTG module registers */
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#define USB_REVISION_REG 0x00
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#define USB_CTRL_REG 0x04
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#define USB_STAT_REG 0x08
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#define USB_EMULATION_REG 0x0c
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/* 0x10 Reserved */
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#define USB_AUTOREQ_REG 0x14
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#define USB_SRP_FIX_TIME_REG 0x18
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#define USB_TEARDOWN_REG 0x1c
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#define EP_INTR_SRC_REG 0x20
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#define EP_INTR_SRC_SET_REG 0x24
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#define EP_INTR_SRC_CLEAR_REG 0x28
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#define EP_INTR_MASK_REG 0x2c
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#define EP_INTR_MASK_SET_REG 0x30
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#define EP_INTR_MASK_CLEAR_REG 0x34
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#define EP_INTR_SRC_MASKED_REG 0x38
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#define CORE_INTR_SRC_REG 0x40
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#define CORE_INTR_SRC_SET_REG 0x44
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#define CORE_INTR_SRC_CLEAR_REG 0x48
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#define CORE_INTR_MASK_REG 0x4c
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#define CORE_INTR_MASK_SET_REG 0x50
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#define CORE_INTR_MASK_CLEAR_REG 0x54
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#define CORE_INTR_SRC_MASKED_REG 0x58
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/* 0x5c Reserved */
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#define USB_END_OF_INTR_REG 0x60
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/* Control register bits */
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#define AM35X_SOFT_RESET_MASK 1
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/* USB interrupt register bits */
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#define AM35X_INTR_USB_SHIFT 16
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#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
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#define AM35X_INTR_DRVVBUS 0x100
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#define AM35X_INTR_RX_SHIFT 16
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#define AM35X_INTR_TX_SHIFT 0
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#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
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#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
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#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
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#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
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#define USB_MENTOR_CORE_OFFSET 0x400
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static inline void phy_on(void)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(100);
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u32 devconf2;
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/*
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* Start the on-chip PHY and its PLL.
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*/
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devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
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devconf2 |= CONF2_PHY_PLLON;
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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DBG(1, "Waiting for PHY clock good...\n");
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while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
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& CONF2_PHYCLKGD)) {
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cpu_relax();
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if (time_after(jiffies, timeout)) {
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DBG(1, "musb PHY clock good timed out\n");
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break;
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}
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}
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}
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static inline void phy_off(void)
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{
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u32 devconf2;
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/*
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* Power down the on-chip PHY.
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*/
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devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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devconf2 &= ~CONF2_PHY_PLLON;
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devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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}
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/*
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2010-12-01 19:22:05 +08:00
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* am35x_musb_enable - enable interrupts
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2010-10-19 15:08:12 +08:00
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*/
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2010-12-01 19:22:05 +08:00
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static void am35x_musb_enable(struct musb *musb)
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2010-10-19 15:08:12 +08:00
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{
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void __iomem *reg_base = musb->ctrl_base;
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u32 epmask;
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/* Workaround: setup IRQs through both register sets. */
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epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
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((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
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musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
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musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
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/* Force the DRVVBUS IRQ so we can start polling for ID change. */
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if (is_otg_enabled(musb))
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musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
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AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
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}
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/*
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2010-12-01 19:22:05 +08:00
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* am35x_musb_disable - disable HDRC and flush interrupts
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2010-10-19 15:08:12 +08:00
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*/
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2010-12-01 19:22:05 +08:00
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static void am35x_musb_disable(struct musb *musb)
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2010-10-19 15:08:12 +08:00
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{
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void __iomem *reg_base = musb->ctrl_base;
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musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
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musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
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AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
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musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
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musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
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}
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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#define portstate(stmt) stmt
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#else
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#define portstate(stmt)
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#endif
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2010-12-01 19:22:05 +08:00
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static void am35x_musb_set_vbus(struct musb *musb, int is_on)
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2010-10-19 15:08:12 +08:00
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{
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WARN_ON(is_on && is_peripheral_active(musb));
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}
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#define POLL_SECONDS 2
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static struct timer_list otg_workaround;
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static void otg_timer(unsigned long _musb)
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{
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struct musb *musb = (void *)_musb;
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void __iomem *mregs = musb->mregs;
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u8 devctl;
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unsigned long flags;
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/*
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* We poll because AM35x's won't expose several OTG-critical
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* status change events (from the transceiver) otherwise.
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*/
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
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spin_lock_irqsave(&musb->lock, flags);
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switch (musb->xceiv->state) {
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case OTG_STATE_A_WAIT_BCON:
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devctl &= ~MUSB_DEVCTL_SESSION;
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musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
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devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
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if (devctl & MUSB_DEVCTL_BDEVICE) {
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musb->xceiv->state = OTG_STATE_B_IDLE;
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MUSB_DEV_MODE(musb);
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} else {
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musb->xceiv->state = OTG_STATE_A_IDLE;
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MUSB_HST_MODE(musb);
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}
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break;
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case OTG_STATE_A_WAIT_VFALL:
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musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
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musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
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MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
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break;
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case OTG_STATE_B_IDLE:
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if (!is_peripheral_enabled(musb))
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break;
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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if (devctl & MUSB_DEVCTL_BDEVICE)
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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else
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musb->xceiv->state = OTG_STATE_A_IDLE;
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break;
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default:
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break;
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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2010-12-01 19:22:05 +08:00
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static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
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2010-10-19 15:08:12 +08:00
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{
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static unsigned long last_timer;
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if (!is_otg_enabled(musb))
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return;
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if (timeout == 0)
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timeout = jiffies + msecs_to_jiffies(3);
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/* Never idle if active, or when VBUS timeout is not set as host */
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if (musb->is_active || (musb->a_wait_bcon == 0 &&
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musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
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DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
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del_timer(&otg_workaround);
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last_timer = jiffies;
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return;
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}
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if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
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DBG(4, "Longer idle timer already pending, ignoring...\n");
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return;
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}
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last_timer = timeout;
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DBG(4, "%s inactive, starting idle timer for %u ms\n",
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otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
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mod_timer(&otg_workaround, timeout);
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}
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2010-12-01 19:22:05 +08:00
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static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
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2010-10-19 15:08:12 +08:00
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{
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struct musb *musb = hci;
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void __iomem *reg_base = musb->ctrl_base;
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unsigned long flags;
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irqreturn_t ret = IRQ_NONE;
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u32 epintr, usbintr, lvl_intr;
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spin_lock_irqsave(&musb->lock, flags);
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/* Get endpoint interrupts */
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epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
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if (epintr) {
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musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
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musb->int_rx =
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(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
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musb->int_tx =
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(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
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}
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/* Get usb core interrupts */
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usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
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if (!usbintr && !epintr)
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goto eoi;
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if (usbintr) {
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musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
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musb->int_usb =
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(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
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}
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/*
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* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
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* AM35x's missing ID change IRQ. We need an ID change IRQ to
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* switch appropriately between halves of the OTG state machine.
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* Managing DEVCTL.SESSION per Mentor docs requires that we know its
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* value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
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* Also, DRVVBUS pulses for SRP (but not at 5V) ...
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*/
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if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
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int drvvbus = musb_readl(reg_base, USB_STAT_REG);
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void __iomem *mregs = musb->mregs;
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u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
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int err;
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err = is_host_enabled(musb) && (musb->int_usb &
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MUSB_INTR_VBUSERROR);
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if (err) {
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/*
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* The Mentor core doesn't debounce VBUS as needed
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* to cope with device connect current spikes. This
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* means it's not uncommon for bus-powered devices
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* to get VBUS errors during enumeration.
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*
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* This is a workaround, but newer RTL from Mentor
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* seems to allow a better one: "re"-starting sessions
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* without waiting for VBUS to stop registering in
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* devctl.
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*/
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musb->int_usb &= ~MUSB_INTR_VBUSERROR;
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musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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WARNING("VBUS error workaround (delay coming)\n");
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} else if (is_host_enabled(musb) && drvvbus) {
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MUSB_HST_MODE(musb);
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musb->xceiv->default_a = 1;
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musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
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portstate(musb->port1_status |= USB_PORT_STAT_POWER);
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del_timer(&otg_workaround);
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} else {
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musb->is_active = 0;
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MUSB_DEV_MODE(musb);
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musb->xceiv->default_a = 0;
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musb->xceiv->state = OTG_STATE_B_IDLE;
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portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
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}
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/* NOTE: this must complete power-on within 100 ms. */
|
|
|
|
DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
|
|
|
|
drvvbus ? "on" : "off",
|
|
|
|
otg_state_string(musb),
|
|
|
|
err ? " ERROR" : "",
|
|
|
|
devctl);
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (musb->int_tx || musb->int_rx || musb->int_usb)
|
|
|
|
ret |= musb_interrupt(musb);
|
|
|
|
|
|
|
|
eoi:
|
|
|
|
/* EOI needs to be written for the IRQ to be re-asserted. */
|
|
|
|
if (ret == IRQ_HANDLED || epintr || usbintr) {
|
|
|
|
/* clear level interrupt */
|
|
|
|
lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
|
|
|
|
lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
|
|
|
|
omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
|
|
|
|
/* write EOI */
|
|
|
|
musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Poll for ID change */
|
|
|
|
if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
|
|
|
|
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-12-01 19:22:05 +08:00
|
|
|
static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
|
2010-10-19 15:08:12 +08:00
|
|
|
{
|
|
|
|
u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
|
|
|
|
|
|
|
|
devconf2 &= ~CONF2_OTGMODE;
|
|
|
|
switch (musb_mode) {
|
|
|
|
#ifdef CONFIG_USB_MUSB_HDRC_HCD
|
|
|
|
case MUSB_HOST: /* Force VBUS valid, ID = 0 */
|
|
|
|
devconf2 |= CONF2_FORCE_HOST;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
|
|
|
|
case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
|
|
|
|
devconf2 |= CONF2_FORCE_DEVICE;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_MUSB_OTG
|
|
|
|
case MUSB_OTG: /* Don't override the VBUS/ID comparators */
|
|
|
|
devconf2 |= CONF2_NO_OVERRIDE;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
|
|
|
|
}
|
|
|
|
|
|
|
|
omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-12-01 19:22:05 +08:00
|
|
|
static int am35x_musb_init(struct musb *musb)
|
2010-10-19 15:08:12 +08:00
|
|
|
{
|
|
|
|
void __iomem *reg_base = musb->ctrl_base;
|
|
|
|
u32 rev, lvl_intr, sw_reset;
|
|
|
|
int status;
|
|
|
|
|
|
|
|
musb->mregs += USB_MENTOR_CORE_OFFSET;
|
|
|
|
|
|
|
|
clk_enable(musb->clock);
|
|
|
|
DBG(2, "musb->clock=%lud\n", clk_get_rate(musb->clock));
|
|
|
|
|
|
|
|
musb->phy_clock = clk_get(musb->controller, "fck");
|
|
|
|
if (IS_ERR(musb->phy_clock)) {
|
|
|
|
status = PTR_ERR(musb->phy_clock);
|
|
|
|
goto exit0;
|
|
|
|
}
|
|
|
|
clk_enable(musb->phy_clock);
|
|
|
|
DBG(2, "musb->phy_clock=%lud\n", clk_get_rate(musb->phy_clock));
|
|
|
|
|
|
|
|
/* Returns zero if e.g. not clocked */
|
|
|
|
rev = musb_readl(reg_base, USB_REVISION_REG);
|
|
|
|
if (!rev) {
|
|
|
|
status = -ENODEV;
|
|
|
|
goto exit1;
|
|
|
|
}
|
|
|
|
|
|
|
|
usb_nop_xceiv_register();
|
|
|
|
musb->xceiv = otg_get_transceiver();
|
|
|
|
if (!musb->xceiv) {
|
|
|
|
status = -ENODEV;
|
|
|
|
goto exit1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_host_enabled(musb))
|
|
|
|
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
|
|
|
|
|
2010-12-01 19:22:05 +08:00
|
|
|
musb->board_set_vbus = am35x_musb_set_vbus;
|
2010-10-19 15:08:12 +08:00
|
|
|
|
|
|
|
/* Global reset */
|
|
|
|
sw_reset = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
|
|
|
|
|
|
|
|
sw_reset |= AM35XX_USBOTGSS_SW_RST;
|
|
|
|
omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
|
|
|
|
|
|
|
|
sw_reset &= ~AM35XX_USBOTGSS_SW_RST;
|
|
|
|
omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
|
|
|
|
|
|
|
|
/* Reset the controller */
|
|
|
|
musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
|
|
|
|
|
|
|
|
/* Start the on-chip PHY and its PLL. */
|
|
|
|
phy_on();
|
|
|
|
|
|
|
|
msleep(5);
|
|
|
|
|
2010-12-01 19:22:05 +08:00
|
|
|
musb->isr = am35x_musb_interrupt;
|
2010-10-19 15:08:12 +08:00
|
|
|
|
|
|
|
/* clear level interrupt */
|
|
|
|
lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
|
|
|
|
lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
|
|
|
|
omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
|
|
|
|
return 0;
|
|
|
|
exit1:
|
|
|
|
clk_disable(musb->phy_clock);
|
|
|
|
clk_put(musb->phy_clock);
|
|
|
|
exit0:
|
|
|
|
clk_disable(musb->clock);
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2010-12-01 19:22:05 +08:00
|
|
|
static int am35x_musb_exit(struct musb *musb)
|
2010-10-19 15:08:12 +08:00
|
|
|
{
|
|
|
|
if (is_host_enabled(musb))
|
|
|
|
del_timer_sync(&otg_workaround);
|
|
|
|
|
|
|
|
phy_off();
|
|
|
|
|
|
|
|
otg_put_transceiver(musb->xceiv);
|
|
|
|
usb_nop_xceiv_unregister();
|
|
|
|
|
|
|
|
clk_disable(musb->clock);
|
|
|
|
|
|
|
|
clk_disable(musb->phy_clock);
|
|
|
|
clk_put(musb->phy_clock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
void musb_platform_save_context(struct musb *musb,
|
|
|
|
struct musb_context_registers *musb_context)
|
|
|
|
{
|
|
|
|
phy_off();
|
|
|
|
}
|
|
|
|
|
|
|
|
void musb_platform_restore_context(struct musb *musb,
|
|
|
|
struct musb_context_registers *musb_context)
|
|
|
|
{
|
|
|
|
phy_on();
|
|
|
|
}
|
|
|
|
#endif
|
2010-10-19 15:08:13 +08:00
|
|
|
|
|
|
|
/* AM35x supports only 32bit read operation */
|
|
|
|
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
|
|
|
|
{
|
|
|
|
void __iomem *fifo = hw_ep->fifo;
|
|
|
|
u32 val;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Read for 32bit-aligned destination address */
|
|
|
|
if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
|
|
|
|
readsl(fifo, dst, len >> 2);
|
|
|
|
dst += len & ~0x03;
|
|
|
|
len &= 0x03;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Now read the remaining 1 to 3 byte or complete length if
|
|
|
|
* unaligned address.
|
|
|
|
*/
|
|
|
|
if (len > 4) {
|
|
|
|
for (i = 0; i < (len >> 2); i++) {
|
|
|
|
*(u32 *) dst = musb_readl(fifo, 0);
|
|
|
|
dst += 4;
|
|
|
|
}
|
|
|
|
len &= 0x03;
|
|
|
|
}
|
|
|
|
if (len > 0) {
|
|
|
|
val = musb_readl(fifo, 0);
|
|
|
|
memcpy(dst, &val, len);
|
|
|
|
}
|
|
|
|
}
|
2010-12-01 19:22:05 +08:00
|
|
|
|
|
|
|
const struct musb_platform_ops musb_ops = {
|
|
|
|
.init = am35x_musb_init,
|
|
|
|
.exit = am35x_musb_exit,
|
|
|
|
|
|
|
|
.enable = am35x_musb_enable,
|
|
|
|
.disable = am35x_musb_disable,
|
|
|
|
|
|
|
|
.set_mode = am35x_musb_set_mode,
|
|
|
|
.try_idle = am35x_musb_try_idle,
|
|
|
|
|
|
|
|
.set_vbus = am35x_musb_set_vbus,
|
|
|
|
};
|