mirror of https://gitee.com/openkylin/linux.git
156 lines
4.8 KiB
C
156 lines
4.8 KiB
C
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/*
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* TQM8xx(L) board specific definitions
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*
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* Copyright (c) 1999-2002 Wolfgang Denk (wd@denx.de)
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*/
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#ifdef __KERNEL__
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#ifndef __MACH_TQM8xx_H
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#define __MACH_TQM8xx_H
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#include <asm/ppcboot.h>
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#ifndef __ASSEMBLY__
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#define TQM_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */
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#define TQM_IMAP_SIZE (64 * 1024) /* size of mapped area */
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#define IMAP_ADDR TQM_IMMR_BASE /* physical base address of IMMR area */
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#define IMAP_SIZE TQM_IMAP_SIZE /* mapped size of IMMR area */
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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#define PCMCIA_MEM_SIZE ( 64 << 20 )
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#ifndef CONFIG_KUP4K
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# define MAX_HWIFS 1 /* overwrite default in include/asm-ppc/ide.h */
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#else /* CONFIG_KUP4K */
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# define MAX_HWIFS 2 /* overwrite default in include/asm-ppc/ide.h */
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# ifndef __ASSEMBLY__
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# include <asm/8xx_immap.h>
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static __inline__ void ide_led(int on)
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{
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volatile immap_t *immap = (immap_t *)IMAP_ADDR;
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if (on) {
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immap->im_ioport.iop_padat &= ~0x80;
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} else {
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immap->im_ioport.iop_padat |= 0x80;
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}
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}
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# endif /* __ASSEMBLY__ */
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# define IDE_LED(x) ide_led((x))
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#endif /* CONFIG_KUP4K */
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/*
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* Definitions for IDE0 Interface
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*/
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#define IDE0_BASE_OFFSET 0
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#define IDE0_DATA_REG_OFFSET (PCMCIA_MEM_SIZE + 0x320)
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#define IDE0_ERROR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 1)
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#define IDE0_NSECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 2)
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#define IDE0_SECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 3)
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#define IDE0_LCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 4)
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#define IDE0_HCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 5)
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#define IDE0_SELECT_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 6)
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#define IDE0_STATUS_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 7)
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#define IDE0_CONTROL_REG_OFFSET 0x0106
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#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */
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/* define IO_BASE for PCMCIA */
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#define _IO_BASE 0x80000000
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#define _IO_BASE_SIZE (64<<10)
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#define FEC_INTERRUPT 9 /* = SIU_LEVEL4 */
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#define PHY_INTERRUPT 12 /* = IRQ6 */
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#define IDE0_INTERRUPT 13
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#ifdef CONFIG_IDE
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#endif
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/*-----------------------------------------------------------------------
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* CPM Ethernet through SCCx.
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*-----------------------------------------------------------------------
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*
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*/
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/*** TQM823L, TQM850L ***********************************************/
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#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L)
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/* Bits in parallel I/O port registers that have to be set/cleared
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* to configure the pins for SCC1 use.
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*/
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#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
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#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
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#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
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#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
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#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
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#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
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#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
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/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
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* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x0000ff00)
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#define SICR_ENET_CLKRT ((uint)0x00002600)
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#endif /* CONFIG_TQM823L, CONFIG_TQM850L */
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/*** TQM860L ********************************************************/
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#ifdef CONFIG_TQM860L
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/* Bits in parallel I/O port registers that have to be set/cleared
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* to configure the pins for SCC1 use.
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*/
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#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
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#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
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#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
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#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
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#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
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#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
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#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
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/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
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* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x000000ff)
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#define SICR_ENET_CLKRT ((uint)0x00000026)
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#endif /* CONFIG_TQM860L */
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/*** FPS850L *********************************************************/
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#ifdef CONFIG_FPS850L
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/* Bits in parallel I/O port registers that have to be set/cleared
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* to configure the pins for SCC1 use.
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*/
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#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
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#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
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#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
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#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
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#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
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#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
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#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
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/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
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* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x0000ff00)
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#define SICR_ENET_CLKRT ((uint)0x00002600)
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#endif /* CONFIG_FPS850L */
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/* We don't use the 8259.
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*/
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#define NR_8259_INTS 0
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#endif /* !__ASSEMBLY__ */
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#endif /* __MACH_TQM8xx_H */
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#endif /* __KERNEL__ */
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