2009-03-27 21:25:20 +08:00
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/*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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2009-05-26 22:30:09 +08:00
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* MMU code derived from arch/ppc/kernel/head_4xx.S:
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* Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
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* Initial PowerPC version.
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* Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Rewritten for PReP
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* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
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* Low-level exception handers, MMU support, and rewrite.
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* Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
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* PowerPC 8xx modifications.
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* Copyright (c) 1998-1999 TiVo, Inc.
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* PowerPC 403GCX modifications.
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* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
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* PowerPC 403GCX/405GP modifications.
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* Copyright 2000 MontaVista Software Inc.
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* PPC405 modifications
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* PowerPC 403GCX/405GP modifications.
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* Author: MontaVista Software, Inc.
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* frank_rowand@mvista.com or source@mvista.com
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* debbie_chu@mvista.com
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*
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2009-03-27 21:25:20 +08:00
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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2010-04-10 11:03:37 +08:00
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#include <linux/init.h>
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2009-03-27 21:25:20 +08:00
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <asm/page.h>
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2009-10-16 00:57:53 +08:00
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#include <linux/of_fdt.h> /* for OF_DT_HEADER */
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2009-03-27 21:25:20 +08:00
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2009-05-26 22:30:09 +08:00
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#ifdef CONFIG_MMU
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#include <asm/setup.h> /* COMMAND_LINE_SIZE */
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#include <asm/mmu.h>
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#include <asm/processor.h>
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2011-01-31 21:57:26 +08:00
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.section .data
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2009-05-26 22:30:09 +08:00
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.global empty_zero_page
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.align 12
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empty_zero_page:
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2010-05-13 23:48:27 +08:00
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.space PAGE_SIZE
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2009-05-26 22:30:09 +08:00
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.global swapper_pg_dir
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swapper_pg_dir:
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2010-05-13 23:48:27 +08:00
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.space PAGE_SIZE
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2009-05-26 22:30:09 +08:00
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#endif /* CONFIG_MMU */
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2011-01-31 21:57:26 +08:00
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.section .rodata
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.align 4
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endian_check:
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.word 1
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2010-04-10 11:03:37 +08:00
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__HEAD
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2009-03-27 21:25:20 +08:00
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ENTRY(_start)
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2010-03-15 15:48:27 +08:00
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#if CONFIG_KERNEL_BASE_ADDR == 0
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brai TOPHYS(real_start)
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.org 0x100
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real_start:
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#endif
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2011-11-09 22:39:58 +08:00
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mts rmsr, r0
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2009-07-30 20:31:23 +08:00
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/*
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2011-02-04 22:24:11 +08:00
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* According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
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* if the msrclr instruction is not enabled. We use this to detect
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* if the opcode is available, by issuing msrclr and then testing the result.
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* r8 == 0 - msr instructions are implemented
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* r8 != 0 - msr instructions are not implemented
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2009-07-30 20:31:23 +08:00
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*/
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2011-11-09 22:39:58 +08:00
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mfs r1, rmsr
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2011-02-04 22:24:11 +08:00
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msrclr r8, 0 /* clear nothing - just read msr for test */
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cmpu r8, r8, r1 /* r1 must contain msr reg content */
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2009-07-30 20:31:23 +08:00
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2009-06-22 12:02:09 +08:00
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/* r7 may point to an FDT, or there may be one linked in.
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if it's in r7, we've got to save it away ASAP.
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We ensure r7 points to a valid FDT, just in case the bootloader
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is broken or non-existent */
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beqi r7, no_fdt_arg /* NULL pointer? don't copy */
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2011-01-26 20:41:05 +08:00
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/* Does r7 point to a valid FDT? Load HEADER magic number */
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/* Run time Big/Little endian platform */
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/* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
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2011-01-31 21:57:26 +08:00
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lbui r11, r0, TOPHYS(endian_check)
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2011-01-26 20:41:05 +08:00
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beqid r11, big_endian /* DO NOT break delay stop dependency */
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lw r11, r0, r7 /* Big endian load in delay slot */
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lwr r11, r0, r7 /* Little endian load */
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big_endian:
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rsubi r11, r11, OF_DT_HEADER /* Check FDT header */
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2009-06-22 18:31:55 +08:00
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beqi r11, _prepare_copy_fdt
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or r7, r0, r0 /* clear R7 when not valid DTB */
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2009-06-22 12:02:09 +08:00
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bnei r11, no_fdt_arg /* No - get out of here */
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2009-06-22 18:31:55 +08:00
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_prepare_copy_fdt:
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2009-03-27 21:25:20 +08:00
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or r11, r0, r0 /* incremment */
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2009-06-22 12:02:09 +08:00
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ori r4, r0, TOPHYS(_fdt_start)
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2011-07-13 21:26:09 +08:00
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ori r3, r0, (0x8000 - 4)
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2009-03-27 21:25:20 +08:00
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_copy_fdt:
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lw r12, r7, r11 /* r12 = r7 + r11 */
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sw r12, r4, r11 /* addr[r4 + r11] = r12 */
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addik r11, r11, 4 /* increment counting */
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bgtid r3, _copy_fdt /* loop for all entries */
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addik r3, r3, -4 /* descrement loop */
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no_fdt_arg:
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2009-05-26 22:30:09 +08:00
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#ifdef CONFIG_MMU
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#ifndef CONFIG_CMDLINE_BOOL
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/*
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* handling command line
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* copy command line to __init_end. There is space for storing command line.
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*/
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or r6, r0, r0 /* incremment */
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ori r4, r0, __init_end /* load address of command line */
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tophys(r4,r4) /* convert to phys address */
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ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
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_copy_command_line:
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2010-03-24 18:06:23 +08:00
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lbu r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
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sb r2, r4, r6 /* addr[r4+r6]= r2*/
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2009-05-26 22:30:09 +08:00
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addik r6, r6, 1 /* increment counting */
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bgtid r3, _copy_command_line /* loop for all entries */
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addik r3, r3, -1 /* descrement loop */
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addik r5, r4, 0 /* add new space for command line */
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tovirt(r5,r5)
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#endif /* CONFIG_CMDLINE_BOOL */
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#ifdef NOT_COMPILE
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/* save bram context */
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or r6, r0, r0 /* incremment */
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ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */
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ori r3, r0, (LMB_SIZE - 4)
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_copy_bram:
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lw r7, r0, r6 /* r7 = r0 + r6 */
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sw r7, r4, r6 /* addr[r4 + r6] = r7*/
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addik r6, r6, 4 /* increment counting */
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bgtid r3, _copy_bram /* loop for all entries */
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addik r3, r3, -4 /* descrement loop */
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#endif
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/* We have to turn on the MMU right away. */
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/*
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* Set up the initial MMU state so we can do the first level of
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* kernel initialization. This maps the first 16 MBytes of memory 1:1
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* virtual to physical.
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*/
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nop
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2010-03-24 17:09:17 +08:00
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addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */
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2009-05-26 22:30:09 +08:00
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_invalidate:
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mts rtlbx, r3
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mts rtlbhi, r0 /* flush: ensure V is clear */
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bgtid r3, _invalidate /* loop for all entries */
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addik r3, r3, -1
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/* sync */
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2010-02-04 18:42:24 +08:00
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/* Setup the kernel PID */
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mts rpid,r0 /* Load the kernel PID */
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nop
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bri 4
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2009-05-26 22:30:09 +08:00
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|
/*
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|
* We should still be executing code at physical address area
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* RAM_BASEADDR at this point. However, kernel code is at
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* a virtual address. So, set up a TLB mapping to cover this once
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* translation is enabled.
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*/
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addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
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tophys(r4,r3) /* Load the kernel physical address */
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|
2010-02-08 23:41:38 +08:00
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/* start to do TLB calculation */
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addik r12, r0, _end
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rsub r12, r3, r12
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addik r12, r12, CONFIG_KERNEL_PAD /* that's the pad */
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or r9, r0, r0 /* TLB0 = 0 */
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or r10, r0, r0 /* TLB1 = 0 */
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addik r11, r12, -0x1000000
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bgei r11, GT16 /* size is greater than 16MB */
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addik r11, r12, -0x0800000
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bgei r11, GT8 /* size is greater than 8MB */
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addik r11, r12, -0x0400000
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bgei r11, GT4 /* size is greater than 4MB */
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/* size is less than 4MB */
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addik r11, r12, -0x0200000
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bgei r11, GT2 /* size is greater than 2MB */
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addik r9, r0, 0x0100000 /* TLB0 must be 1MB */
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addik r11, r12, -0x0100000
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bgei r11, GT1 /* size is greater than 1MB */
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/* TLB1 is 0 which is setup above */
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bri tlb_end
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GT4: /* r11 contains the rest - will be either 1 or 4 */
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ori r9, r0, 0x400000 /* TLB0 is 4MB */
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bri TLB1
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GT16: /* TLB0 is 16MB */
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addik r9, r0, 0x1000000 /* means TLB0 is 16MB */
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TLB1:
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|
/* must be used r2 because of substract if failed */
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addik r2, r11, -0x0400000
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bgei r2, GT20 /* size is greater than 16MB */
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/* size is >16MB and <20MB */
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addik r11, r11, -0x0100000
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bgei r11, GT17 /* size is greater than 17MB */
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|
/* kernel is >16MB and < 17MB */
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GT1:
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addik r10, r0, 0x0100000 /* means TLB1 is 1MB */
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bri tlb_end
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GT2: /* TLB0 is 0 and TLB1 will be 4MB */
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GT17: /* TLB1 is 4MB - kernel size <20MB */
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|
|
addik r10, r0, 0x0400000 /* means TLB1 is 4MB */
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bri tlb_end
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GT8: /* TLB0 is still zero that's why I can use only TLB1 */
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GT20: /* TLB1 is 16MB - kernel size >20MB */
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addik r10, r0, 0x1000000 /* means TLB1 is 16MB */
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tlb_end:
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|
2009-05-26 22:30:09 +08:00
|
|
|
/*
|
|
|
|
* Configure and load two entries into TLB slots 0 and 1.
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|
|
* In case we are pinning TLBs, these are reserved in by the
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|
|
|
* other TLB functions. If not reserving, then it doesn't
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|
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* matter where they are loaded.
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|
*/
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|
|
|
andi r4,r4,0xfffffc00 /* Mask off the real page number */
|
|
|
|
ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
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|
|
|
|
2010-02-08 23:41:38 +08:00
|
|
|
/* TLB0 can be zeroes that's why we not setup it */
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|
|
beqi r9, jump_over
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|
|
/* look at the code below */
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|
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ori r30, r0, 0x200
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|
|
andi r29, r9, 0x100000
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|
|
bneid r29, 1f
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|
|
addik r30, r30, 0x80
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|
|
andi r29, r9, 0x400000
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|
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bneid r29, 1f
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|
addik r30, r30, 0x80
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|
|
andi r29, r9, 0x1000000
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|
|
|
bneid r29, 1f
|
|
|
|
addik r30, r30, 0x80
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1:
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|
|
ori r11, r30, 0
|
|
|
|
|
2009-05-26 22:30:09 +08:00
|
|
|
andi r3,r3,0xfffffc00 /* Mask off the effective page number */
|
2010-02-08 23:41:38 +08:00
|
|
|
ori r3,r3,(TLB_VALID)
|
|
|
|
or r3, r3, r11
|
2009-05-26 22:30:09 +08:00
|
|
|
|
|
|
|
mts rtlbx,r0 /* TLB slow 0 */
|
|
|
|
|
|
|
|
mts rtlblo,r4 /* Load the data portion of the entry */
|
|
|
|
mts rtlbhi,r3 /* Load the tag portion of the entry */
|
|
|
|
|
2010-02-08 23:41:38 +08:00
|
|
|
jump_over:
|
|
|
|
/* TLB1 can be zeroes that's why we not setup it */
|
|
|
|
beqi r10, jump_over2
|
|
|
|
|
|
|
|
/* look at the code below */
|
|
|
|
ori r30, r0, 0x200
|
|
|
|
andi r29, r10, 0x100000
|
|
|
|
bneid r29, 1f
|
|
|
|
addik r30, r30, 0x80
|
|
|
|
andi r29, r10, 0x400000
|
|
|
|
bneid r29, 1f
|
|
|
|
addik r30, r30, 0x80
|
|
|
|
andi r29, r10, 0x1000000
|
|
|
|
bneid r29, 1f
|
|
|
|
addik r30, r30, 0x80
|
|
|
|
1:
|
|
|
|
ori r12, r30, 0
|
|
|
|
|
|
|
|
addk r4, r4, r9 /* previous addr + TLB0 size */
|
|
|
|
addk r3, r3, r9
|
|
|
|
|
|
|
|
andi r3,r3,0xfffffc00 /* Mask off the effective page number */
|
|
|
|
ori r3,r3,(TLB_VALID)
|
|
|
|
or r3, r3, r12
|
2009-05-26 22:30:09 +08:00
|
|
|
|
|
|
|
ori r6,r0,1 /* TLB slot 1 */
|
|
|
|
mts rtlbx,r6
|
|
|
|
|
|
|
|
mts rtlblo,r4 /* Load the data portion of the entry */
|
|
|
|
mts rtlbhi,r3 /* Load the tag portion of the entry */
|
|
|
|
|
2010-02-08 23:41:38 +08:00
|
|
|
jump_over2:
|
2009-05-26 22:30:09 +08:00
|
|
|
/*
|
|
|
|
* Load a TLB entry for LMB, since we need access to
|
|
|
|
* the exception vectors, using a 4k real==virtual mapping.
|
|
|
|
*/
|
|
|
|
ori r6,r0,3 /* TLB slot 3 */
|
|
|
|
mts rtlbx,r6
|
|
|
|
|
|
|
|
ori r4,r0,(TLB_WR | TLB_EX)
|
|
|
|
ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
|
|
|
|
|
|
|
|
mts rtlblo,r4 /* Load the data portion of the entry */
|
|
|
|
mts rtlbhi,r3 /* Load the tag portion of the entry */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We now have the lower 16 Meg of RAM mapped into TLB entries, and the
|
|
|
|
* caches ready to work.
|
|
|
|
*/
|
|
|
|
turn_on_mmu:
|
|
|
|
ori r15,r0,start_here
|
|
|
|
ori r4,r0,MSR_KERNEL_VMS
|
|
|
|
mts rmsr,r4
|
|
|
|
nop
|
|
|
|
rted r15,0 /* enables MMU */
|
|
|
|
nop
|
|
|
|
|
|
|
|
start_here:
|
|
|
|
#endif /* CONFIG_MMU */
|
|
|
|
|
2009-03-27 21:25:20 +08:00
|
|
|
/* Initialize small data anchors */
|
2011-02-01 16:00:57 +08:00
|
|
|
addik r13, r0, _KERNEL_SDA_BASE_
|
|
|
|
addik r2, r0, _KERNEL_SDA2_BASE_
|
2009-03-27 21:25:20 +08:00
|
|
|
|
|
|
|
/* Initialize stack pointer */
|
2011-02-01 16:00:57 +08:00
|
|
|
addik r1, r0, init_thread_union + THREAD_SIZE - 4
|
2009-03-27 21:25:20 +08:00
|
|
|
|
|
|
|
/* Initialize r31 with current task address */
|
2011-02-01 16:00:57 +08:00
|
|
|
addik r31, r0, init_task
|
2009-03-27 21:25:20 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Call platform dependent initialize function.
|
|
|
|
* Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
|
|
|
|
* the function.
|
|
|
|
*/
|
2010-02-08 23:41:38 +08:00
|
|
|
addik r11, r0, machine_early_init
|
|
|
|
brald r15, r11
|
2009-03-27 21:25:20 +08:00
|
|
|
nop
|
|
|
|
|
2009-05-26 22:30:09 +08:00
|
|
|
#ifndef CONFIG_MMU
|
2011-02-01 16:00:57 +08:00
|
|
|
addik r15, r0, machine_halt
|
2009-03-27 21:25:20 +08:00
|
|
|
braid start_kernel
|
|
|
|
nop
|
2009-05-26 22:30:09 +08:00
|
|
|
#else
|
|
|
|
/*
|
|
|
|
* Initialize the MMU.
|
|
|
|
*/
|
|
|
|
bralid r15, mmu_init
|
|
|
|
nop
|
|
|
|
|
|
|
|
/* Go back to running unmapped so we can load up new values
|
|
|
|
* and change to using our exception vectors.
|
|
|
|
* On the MicroBlaze, all we invalidate the used TLB entries to clear
|
|
|
|
* the old 16M byte TLB mappings.
|
|
|
|
*/
|
|
|
|
ori r15,r0,TOPHYS(kernel_load_context)
|
|
|
|
ori r4,r0,MSR_KERNEL
|
|
|
|
mts rmsr,r4
|
|
|
|
nop
|
|
|
|
bri 4
|
|
|
|
rted r15,0
|
|
|
|
nop
|
|
|
|
|
|
|
|
/* Load up the kernel context */
|
|
|
|
kernel_load_context:
|
|
|
|
# Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away.
|
|
|
|
ori r5,r0,3
|
|
|
|
mts rtlbx,r5
|
|
|
|
nop
|
|
|
|
mts rtlbhi,r0
|
|
|
|
nop
|
|
|
|
addi r15, r0, machine_halt
|
|
|
|
ori r17, r0, start_kernel
|
|
|
|
ori r4, r0, MSR_KERNEL_VMS
|
|
|
|
mts rmsr, r4
|
|
|
|
nop
|
|
|
|
rted r17, 0 /* enable MMU and jump to start_kernel */
|
|
|
|
nop
|
|
|
|
#endif /* CONFIG_MMU */
|