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linux/arch/sparc/mm/init_64.h

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sparc64: Kill sparse warnings in mm/init.h 1) Several exported symbols need extern decls, they are exported not for C code but for assembler routines. 2) PAGE_EXEC isn't used, delete 3) Several larger than 32-bit constants need "UL" markers Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-12 15:19:21 +08:00
#ifndef _SPARC64_MM_INIT_H
#define _SPARC64_MM_INIT_H
sparc64: Document the shift counts used to validate linear kernel addresses. This way we can see exactly what they are derived from, and in particular how they would change if we were to use a different PAGE_OFFSET value. Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Bob Picco <bob.picco@oracle.com>
2013-09-19 06:39:06 +08:00
#include <asm/page.h>
sparc64: Kill sparse warnings in mm/init.h 1) Several exported symbols need extern decls, they are exported not for C code but for assembler routines. 2) PAGE_EXEC isn't used, delete 3) Several larger than 32-bit constants need "UL" markers Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-12 15:19:21 +08:00
/* Most of the symbols in this file are defined in init.c and
* marked non-static so that assembler code can get at them.
*/
sparc64: Document the shift counts used to validate linear kernel addresses. This way we can see exactly what they are derived from, and in particular how they would change if we were to use a different PAGE_OFFSET value. Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Bob Picco <bob.picco@oracle.com>
2013-09-19 06:39:06 +08:00
#define MAX_PHYS_ADDRESS (1UL << MAX_PHYS_ADDRESS_BITS)
sparc64: Validate linear D-TLB misses. When page alloc debugging is not enabled, we essentially accept any virtual address for linear kernel TLB misses. But with kgdb, kernel address probing, and other facilities we can try to access arbitrary crap. So, make sure the address we miss on will translate to physical memory that actually exists. In order to make this work we have to embed the valid address bitmap into the kernel image. And in order to make that less expensive we make an adjustment, in that the max physical memory address is decreased to "1 << 41", even on the chips that support a 42-bit physical address space. We can do this because bit 41 indicates "I/O space" and thus covers non-memory ranges. The result of this is that: 1) kpte_linear_bitmap shrinks from 2K to 1K in size 2) we need 64K more for the valid address bitmap We can't let the valid address bitmap be dynamically allocated once we start using it to validate TLB misses, otherwise we have crazy issues to deal with wrt. recursive TLB misses and such. If we're in a TLB miss it could be the deepest trap level that's legal inside of the cpu. So if we TLB miss referencing the bitmap, the cpu will be out of trap levels and enter RED state. To guard against out-of-range accesses to the bitmap, we have to check to make sure no bits in the physical address above bit 40 are set. We could export and use last_valid_pfn for this check, but that's just an unnecessary extra memory reference. On the plus side of all this, since we load all of these translations into the special 4MB mapping TSB, and we check the TSB first for TLB misses, there should be absolutely no real cost for these new checks in the TLB miss path. Reported-by: heyongli@gmail.com Signed-off-by: David S. Miller <davem@davemloft.net>
2009-08-26 07:47:46 +08:00
#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
sparc64: Kill sparse warnings in mm/init.h 1) Several exported symbols need extern decls, they are exported not for C code but for assembler routines. 2) PAGE_EXEC isn't used, delete 3) Several larger than 32-bit constants need "UL" markers Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-12 15:19:21 +08:00
#define KPTE_BITMAP_BYTES \
sparc64: Support 2GB and 16GB page sizes for kernel linear mappings. SPARC-T4 supports 2GB pages. So convert kpte_linear_bitmap into an array of 2-bit values which index into kern_linear_pte_xor. Now kern_linear_pte_xor is used for 4 page size aligned regions, 4MB, 256MB, 2GB, and 16GB respectively. Enabling 2GB pages is currently hardcoded using a check against sun4v_chip_type. In the future this will be done more cleanly by interrogating the machine description which is the correct way to determine this kind of thing. Signed-off-by: David S. Miller <davem@davemloft.net>
2012-09-07 09:13:58 +08:00
((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 4)
sparc64: Validate linear D-TLB misses. When page alloc debugging is not enabled, we essentially accept any virtual address for linear kernel TLB misses. But with kgdb, kernel address probing, and other facilities we can try to access arbitrary crap. So, make sure the address we miss on will translate to physical memory that actually exists. In order to make this work we have to embed the valid address bitmap into the kernel image. And in order to make that less expensive we make an adjustment, in that the max physical memory address is decreased to "1 << 41", even on the chips that support a 42-bit physical address space. We can do this because bit 41 indicates "I/O space" and thus covers non-memory ranges. The result of this is that: 1) kpte_linear_bitmap shrinks from 2K to 1K in size 2) we need 64K more for the valid address bitmap We can't let the valid address bitmap be dynamically allocated once we start using it to validate TLB misses, otherwise we have crazy issues to deal with wrt. recursive TLB misses and such. If we're in a TLB miss it could be the deepest trap level that's legal inside of the cpu. So if we TLB miss referencing the bitmap, the cpu will be out of trap levels and enter RED state. To guard against out-of-range accesses to the bitmap, we have to check to make sure no bits in the physical address above bit 40 are set. We could export and use last_valid_pfn for this check, but that's just an unnecessary extra memory reference. On the plus side of all this, since we load all of these translations into the special 4MB mapping TSB, and we check the TSB first for TLB misses, there should be absolutely no real cost for these new checks in the TLB miss path. Reported-by: heyongli@gmail.com Signed-off-by: David S. Miller <davem@davemloft.net>
2009-08-26 07:47:46 +08:00
#define VALID_ADDR_BITMAP_CHUNK_SZ (4UL * 1024UL * 1024UL)
#define VALID_ADDR_BITMAP_BYTES \
((MAX_PHYS_ADDRESS / VALID_ADDR_BITMAP_CHUNK_SZ) / 8)
sparc64: Kill sparse warnings in mm/init.h 1) Several exported symbols need extern decls, they are exported not for C code but for assembler routines. 2) PAGE_EXEC isn't used, delete 3) Several larger than 32-bit constants need "UL" markers Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-12 15:19:21 +08:00
sparc64: Support 2GB and 16GB page sizes for kernel linear mappings. SPARC-T4 supports 2GB pages. So convert kpte_linear_bitmap into an array of 2-bit values which index into kern_linear_pte_xor. Now kern_linear_pte_xor is used for 4 page size aligned regions, 4MB, 256MB, 2GB, and 16GB respectively. Enabling 2GB pages is currently hardcoded using a check against sun4v_chip_type. In the future this will be done more cleanly by interrogating the machine description which is the correct way to determine this kind of thing. Signed-off-by: David S. Miller <davem@davemloft.net>
2012-09-07 09:13:58 +08:00
extern unsigned long kern_linear_pte_xor[4];
sparc64: Kill sparse warnings in mm/init.h 1) Several exported symbols need extern decls, they are exported not for C code but for assembler routines. 2) PAGE_EXEC isn't used, delete 3) Several larger than 32-bit constants need "UL" markers Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-12 15:19:21 +08:00
extern unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
extern unsigned int sparc64_highest_unlocked_tlb_ent;
extern unsigned long sparc64_kern_pri_context;
extern unsigned long sparc64_kern_pri_nuc_bits;
extern unsigned long sparc64_kern_sec_context;
extern void mmu_info(struct seq_file *m);
struct linux_prom_translation {
unsigned long virt;
unsigned long size;
unsigned long data;
};
/* Exported for kernel TLB miss handling in ktlb.S */
extern struct linux_prom_translation prom_trans[512];
extern unsigned int prom_trans_ents;
/* Exported for SMP bootup purposes. */
extern unsigned long kern_locked_tte_data;
extern void prom_world(int enter);
#ifdef CONFIG_SPARSEMEM_VMEMMAP
#define VMEMMAP_CHUNK_SHIFT 22
#define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
#define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
#define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
#define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
sparc64: Fix definition of VMEMMAP_SIZE. This was the cause of various boot failures on V480, V880, etc. systems. Kernel image memory was being overwritten because the vmemmap[] array was being sized to small. So if you had physical memory addresses past a certain point, the early bootup would spam all over variables in the kernel data section. The vmemmap mappings map page structs, not page struct pointers. And that was the key thinko in the macro definition. This was fixable thanks to the help, reports, and tireless patience of Hermann Lauer. Reported-by: Hermann Lauer <Hermann.Lauer@iwr.uni-heidelberg.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2009-11-24 08:38:56 +08:00
sizeof(struct page)) >> VMEMMAP_CHUNK_SHIFT)
sparc64: Kill sparse warnings in mm/init.h 1) Several exported symbols need extern decls, they are exported not for C code but for assembler routines. 2) PAGE_EXEC isn't used, delete 3) Several larger than 32-bit constants need "UL" markers Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-12 15:19:21 +08:00
extern unsigned long vmemmap_table[VMEMMAP_SIZE];
#endif
#endif /* _SPARC64_MM_INIT_H */