2018-05-16 16:50:40 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2016-08-28 01:40:50 +08:00
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/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* Copyright (c) 2016 BayLibre, Inc.
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* Michael Turquette <mturquette@baylibre.com>
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*/
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#ifndef __MESON8B_H
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#define __MESON8B_H
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/*
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* Clock controller register offsets
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*
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* Register offsets from the HardKernel[0] data sheet are listed in comment
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* blocks below. Those offsets must be multiplied by 4 before adding them to
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* the base address to get the right value
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*
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* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
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*/
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2019-03-24 23:11:03 +08:00
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#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
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clk: meson: meson8b: add the read-only video clock trees
Add all clocks to give us the final video clocks within the Meson8,
Meson8b and Meson8m2 SoCs. The final video clocks are:
- cts_enct
- cts_encl
- cts_encp
- cts_enci
- cts_vdac0
- hdmi_tx_pixel
- hdmi_sys
Add multiple clocks in between which are needed to implement these
clocks:
- Opposed to GXBB there is no pre-multiplier for the PLL input. The
assumption here is that the multiplier is required to achieve the HDMI
2.0 clock rates (which are up to twice the rate of the HDMI 1.4
rates).
- The main PLL is called "HDMI PLL" or "HPLL" in the datasheet. Rename
our existing "vid_pll_dco" to "hdmi_pll_dco". The actual VID_PLL clock
also exists further down the tree.
- Rename the existing "vid_pll" clock (which is the OD divider at
HHI_VID_PLL_CNTL[17:16]) to "hdmi_pll_lvds_out" to match the naming
from the datasheet.
- Add the second OD divider called "hdmi_pll_hdmi_out" at
HHI_VID_PLL_CNTL[19:18].
- Add the "vid_pll_in_sel" which can choose between "hdmi_pll_dco" and
another parent. However, the second parent is not use on Amlogic's
3.10 kernel for HDMI or CVBS output so just leave a TODO in the code.
- Add the "vid_pll_in_en" which is located after "vid_pll_in_sel"
according to the datasheet.
- Add "vid_pll_pre_div" which is used for divide-by-5 and divide-by-6 in
Amlogic's 3.10 kernel sources.
- Add "vid_pll_post_div" which divides the output of "vid_pll_pre_div"
further down. The Amlogic 3.10 kernel configures this as divide-by-2
with "vid_pll_pre_div" being configured as divide-by-5 to achieve a
total divider of 10.
- Add the real "vid_pll" clock which selects between "vid_pll_pre_div",
"vid_pll_post_div" and a third "vid_pll_pre_div_mult7_div2" (which is
"vid_pll_pre_div" divided by 3.5). The latter is not supported yet
because it's not used in Amlogic's 3.10 kernel. The "vid_pll" clock
rate can also be measured by clkmsr to check whether this
implementation is correct.
- Add "vid_pll_final_div" which is a post-divider for "vid_pll" and it's
used as input for "vclk" and "vclk2"
- Add the two symmetric "vclk" and "vclk" clock trees, each with a
divide-by-1, divide-by-2, divide-by-4, divide-by-6 and divide-by-12
clock and a divider for each clock.
- Add the "cts_enct", "cts_encp" and "hdmi_tx_pixel" clocks which each
have their own gate and can select between any of the five "vclk"
dividers.
- Add the "cts_encl" and "cts_vdac0" clocks which each have their own
gate and can select between any of the five "vclk2" dividers.
The "hdmi_sys" clock is a different than these video clocks. It takes
"xtal" as input (there are three more but unknown parents). Add this
clock as well as it's used by the HDMI controller. Amlogic's 3.10 kernel
always configures this as "xtal divided by 1", so we can ignore the
other parents for now.
This was tested on Meson8b and Meson8m2 boards by comparing the common
clock framework output with the clock measurer output. The following
video modes were first set in u-boot (by running "video dev open $mode")
before booting Linux:
4K2K30HZ (only supported by Meson8m2, not tested on Meson8b):
- vid_pll: 297000000Hz
- cts_encp: 297000000Hz
- hdmi_tx_pixel: 297000000Hz
1080P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 148500000Hz
720P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 74250000Hz
480P:
- vid_pll: 216000000Hz
- cts_encp: 54000000Hz
- hdmi_tx_pixel: 27000000Hz
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-4-martin.blumenstingl@googlemail.com
2018-12-03 05:42:20 +08:00
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#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
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#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
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2016-08-28 01:40:54 +08:00
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#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
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#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
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#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
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#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
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#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
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2016-08-28 01:40:51 +08:00
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#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
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clk: meson: meson8b: add the read-only video clock trees
Add all clocks to give us the final video clocks within the Meson8,
Meson8b and Meson8m2 SoCs. The final video clocks are:
- cts_enct
- cts_encl
- cts_encp
- cts_enci
- cts_vdac0
- hdmi_tx_pixel
- hdmi_sys
Add multiple clocks in between which are needed to implement these
clocks:
- Opposed to GXBB there is no pre-multiplier for the PLL input. The
assumption here is that the multiplier is required to achieve the HDMI
2.0 clock rates (which are up to twice the rate of the HDMI 1.4
rates).
- The main PLL is called "HDMI PLL" or "HPLL" in the datasheet. Rename
our existing "vid_pll_dco" to "hdmi_pll_dco". The actual VID_PLL clock
also exists further down the tree.
- Rename the existing "vid_pll" clock (which is the OD divider at
HHI_VID_PLL_CNTL[17:16]) to "hdmi_pll_lvds_out" to match the naming
from the datasheet.
- Add the second OD divider called "hdmi_pll_hdmi_out" at
HHI_VID_PLL_CNTL[19:18].
- Add the "vid_pll_in_sel" which can choose between "hdmi_pll_dco" and
another parent. However, the second parent is not use on Amlogic's
3.10 kernel for HDMI or CVBS output so just leave a TODO in the code.
- Add the "vid_pll_in_en" which is located after "vid_pll_in_sel"
according to the datasheet.
- Add "vid_pll_pre_div" which is used for divide-by-5 and divide-by-6 in
Amlogic's 3.10 kernel sources.
- Add "vid_pll_post_div" which divides the output of "vid_pll_pre_div"
further down. The Amlogic 3.10 kernel configures this as divide-by-2
with "vid_pll_pre_div" being configured as divide-by-5 to achieve a
total divider of 10.
- Add the real "vid_pll" clock which selects between "vid_pll_pre_div",
"vid_pll_post_div" and a third "vid_pll_pre_div_mult7_div2" (which is
"vid_pll_pre_div" divided by 3.5). The latter is not supported yet
because it's not used in Amlogic's 3.10 kernel. The "vid_pll" clock
rate can also be measured by clkmsr to check whether this
implementation is correct.
- Add "vid_pll_final_div" which is a post-divider for "vid_pll" and it's
used as input for "vclk" and "vclk2"
- Add the two symmetric "vclk" and "vclk" clock trees, each with a
divide-by-1, divide-by-2, divide-by-4, divide-by-6 and divide-by-12
clock and a divider for each clock.
- Add the "cts_enct", "cts_encp" and "hdmi_tx_pixel" clocks which each
have their own gate and can select between any of the five "vclk"
dividers.
- Add the "cts_encl" and "cts_vdac0" clocks which each have their own
gate and can select between any of the five "vclk2" dividers.
The "hdmi_sys" clock is a different than these video clocks. It takes
"xtal" as input (there are three more but unknown parents). Add this
clock as well as it's used by the HDMI controller. Amlogic's 3.10 kernel
always configures this as "xtal divided by 1", so we can ignore the
other parents for now.
This was tested on Meson8b and Meson8m2 boards by comparing the common
clock framework output with the clock measurer output. The following
video modes were first set in u-boot (by running "video dev open $mode")
before booting Linux:
4K2K30HZ (only supported by Meson8m2, not tested on Meson8b):
- vid_pll: 297000000Hz
- cts_encp: 297000000Hz
- hdmi_tx_pixel: 297000000Hz
1080P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 148500000Hz
720P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 74250000Hz
480P:
- vid_pll: 216000000Hz
- cts_encp: 54000000Hz
- hdmi_tx_pixel: 27000000Hz
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-4-martin.blumenstingl@googlemail.com
2018-12-03 05:42:20 +08:00
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#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
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2016-08-28 01:40:51 +08:00
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#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
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2019-05-21 04:03:17 +08:00
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#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
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2017-07-29 05:13:12 +08:00
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#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
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2019-05-21 04:03:18 +08:00
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#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
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clk: meson: meson8b: add the read-only video clock trees
Add all clocks to give us the final video clocks within the Meson8,
Meson8b and Meson8m2 SoCs. The final video clocks are:
- cts_enct
- cts_encl
- cts_encp
- cts_enci
- cts_vdac0
- hdmi_tx_pixel
- hdmi_sys
Add multiple clocks in between which are needed to implement these
clocks:
- Opposed to GXBB there is no pre-multiplier for the PLL input. The
assumption here is that the multiplier is required to achieve the HDMI
2.0 clock rates (which are up to twice the rate of the HDMI 1.4
rates).
- The main PLL is called "HDMI PLL" or "HPLL" in the datasheet. Rename
our existing "vid_pll_dco" to "hdmi_pll_dco". The actual VID_PLL clock
also exists further down the tree.
- Rename the existing "vid_pll" clock (which is the OD divider at
HHI_VID_PLL_CNTL[17:16]) to "hdmi_pll_lvds_out" to match the naming
from the datasheet.
- Add the second OD divider called "hdmi_pll_hdmi_out" at
HHI_VID_PLL_CNTL[19:18].
- Add the "vid_pll_in_sel" which can choose between "hdmi_pll_dco" and
another parent. However, the second parent is not use on Amlogic's
3.10 kernel for HDMI or CVBS output so just leave a TODO in the code.
- Add the "vid_pll_in_en" which is located after "vid_pll_in_sel"
according to the datasheet.
- Add "vid_pll_pre_div" which is used for divide-by-5 and divide-by-6 in
Amlogic's 3.10 kernel sources.
- Add "vid_pll_post_div" which divides the output of "vid_pll_pre_div"
further down. The Amlogic 3.10 kernel configures this as divide-by-2
with "vid_pll_pre_div" being configured as divide-by-5 to achieve a
total divider of 10.
- Add the real "vid_pll" clock which selects between "vid_pll_pre_div",
"vid_pll_post_div" and a third "vid_pll_pre_div_mult7_div2" (which is
"vid_pll_pre_div" divided by 3.5). The latter is not supported yet
because it's not used in Amlogic's 3.10 kernel. The "vid_pll" clock
rate can also be measured by clkmsr to check whether this
implementation is correct.
- Add "vid_pll_final_div" which is a post-divider for "vid_pll" and it's
used as input for "vclk" and "vclk2"
- Add the two symmetric "vclk" and "vclk" clock trees, each with a
divide-by-1, divide-by-2, divide-by-4, divide-by-6 and divide-by-12
clock and a divider for each clock.
- Add the "cts_enct", "cts_encp" and "hdmi_tx_pixel" clocks which each
have their own gate and can select between any of the five "vclk"
dividers.
- Add the "cts_encl" and "cts_vdac0" clocks which each have their own
gate and can select between any of the five "vclk2" dividers.
The "hdmi_sys" clock is a different than these video clocks. It takes
"xtal" as input (there are three more but unknown parents). Add this
clock as well as it's used by the HDMI controller. Amlogic's 3.10 kernel
always configures this as "xtal divided by 1", so we can ignore the
other parents for now.
This was tested on Meson8b and Meson8m2 boards by comparing the common
clock framework output with the clock measurer output. The following
video modes were first set in u-boot (by running "video dev open $mode")
before booting Linux:
4K2K30HZ (only supported by Meson8m2, not tested on Meson8b):
- vid_pll: 297000000Hz
- cts_encp: 297000000Hz
- hdmi_tx_pixel: 297000000Hz
1080P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 148500000Hz
720P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 74250000Hz
480P:
- vid_pll: 216000000Hz
- cts_encp: 54000000Hz
- hdmi_tx_pixel: 27000000Hz
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-4-martin.blumenstingl@googlemail.com
2018-12-03 05:42:20 +08:00
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#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
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2017-07-29 05:13:12 +08:00
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#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
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#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
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2018-12-09 01:12:45 +08:00
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#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
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2019-03-24 23:11:04 +08:00
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#define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */
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clk: meson: meson8b: add the read-only video clock trees
Add all clocks to give us the final video clocks within the Meson8,
Meson8b and Meson8m2 SoCs. The final video clocks are:
- cts_enct
- cts_encl
- cts_encp
- cts_enci
- cts_vdac0
- hdmi_tx_pixel
- hdmi_sys
Add multiple clocks in between which are needed to implement these
clocks:
- Opposed to GXBB there is no pre-multiplier for the PLL input. The
assumption here is that the multiplier is required to achieve the HDMI
2.0 clock rates (which are up to twice the rate of the HDMI 1.4
rates).
- The main PLL is called "HDMI PLL" or "HPLL" in the datasheet. Rename
our existing "vid_pll_dco" to "hdmi_pll_dco". The actual VID_PLL clock
also exists further down the tree.
- Rename the existing "vid_pll" clock (which is the OD divider at
HHI_VID_PLL_CNTL[17:16]) to "hdmi_pll_lvds_out" to match the naming
from the datasheet.
- Add the second OD divider called "hdmi_pll_hdmi_out" at
HHI_VID_PLL_CNTL[19:18].
- Add the "vid_pll_in_sel" which can choose between "hdmi_pll_dco" and
another parent. However, the second parent is not use on Amlogic's
3.10 kernel for HDMI or CVBS output so just leave a TODO in the code.
- Add the "vid_pll_in_en" which is located after "vid_pll_in_sel"
according to the datasheet.
- Add "vid_pll_pre_div" which is used for divide-by-5 and divide-by-6 in
Amlogic's 3.10 kernel sources.
- Add "vid_pll_post_div" which divides the output of "vid_pll_pre_div"
further down. The Amlogic 3.10 kernel configures this as divide-by-2
with "vid_pll_pre_div" being configured as divide-by-5 to achieve a
total divider of 10.
- Add the real "vid_pll" clock which selects between "vid_pll_pre_div",
"vid_pll_post_div" and a third "vid_pll_pre_div_mult7_div2" (which is
"vid_pll_pre_div" divided by 3.5). The latter is not supported yet
because it's not used in Amlogic's 3.10 kernel. The "vid_pll" clock
rate can also be measured by clkmsr to check whether this
implementation is correct.
- Add "vid_pll_final_div" which is a post-divider for "vid_pll" and it's
used as input for "vclk" and "vclk2"
- Add the two symmetric "vclk" and "vclk" clock trees, each with a
divide-by-1, divide-by-2, divide-by-4, divide-by-6 and divide-by-12
clock and a divider for each clock.
- Add the "cts_enct", "cts_encp" and "hdmi_tx_pixel" clocks which each
have their own gate and can select between any of the five "vclk"
dividers.
- Add the "cts_encl" and "cts_vdac0" clocks which each have their own
gate and can select between any of the five "vclk2" dividers.
The "hdmi_sys" clock is a different than these video clocks. It takes
"xtal" as input (there are three more but unknown parents). Add this
clock as well as it's used by the HDMI controller. Amlogic's 3.10 kernel
always configures this as "xtal divided by 1", so we can ignore the
other parents for now.
This was tested on Meson8b and Meson8m2 boards by comparing the common
clock framework output with the clock measurer output. The following
video modes were first set in u-boot (by running "video dev open $mode")
before booting Linux:
4K2K30HZ (only supported by Meson8m2, not tested on Meson8b):
- vid_pll: 297000000Hz
- cts_encp: 297000000Hz
- hdmi_tx_pixel: 297000000Hz
1080P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 148500000Hz
720P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 74250000Hz
480P:
- vid_pll: 216000000Hz
- cts_encp: 54000000Hz
- hdmi_tx_pixel: 27000000Hz
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-4-martin.blumenstingl@googlemail.com
2018-12-03 05:42:20 +08:00
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#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
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2019-03-24 23:14:23 +08:00
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#define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */
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#define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */
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#define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */
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2018-04-24 03:35:09 +08:00
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#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
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2016-08-28 01:40:51 +08:00
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
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#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
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2018-12-03 05:42:19 +08:00
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#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
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2016-08-28 01:40:50 +08:00
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2017-03-09 18:41:52 +08:00
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/*
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* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
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* confirm these are the same for the S805.
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*/
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
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#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
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#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
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#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
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#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
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#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */
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#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */
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#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
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#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
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2016-08-28 01:40:52 +08:00
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/*
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* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
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2017-07-31 19:38:31 +08:00
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
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* to expose, such as the internal muxes and dividers of composite clocks,
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|
|
|
|
* will remain defined here.
|
2016-08-28 01:40:52 +08:00
|
|
|
*/
|
|
|
|
|
|
2018-02-12 22:58:43 +08:00
|
|
|
#define CLKID_MPLL0_DIV 96
|
|
|
|
|
#define CLKID_MPLL1_DIV 97
|
|
|
|
|
#define CLKID_MPLL2_DIV 98
|
2018-02-12 22:58:44 +08:00
|
|
|
#define CLKID_CPU_IN_SEL 99
|
2018-11-23 05:40:16 +08:00
|
|
|
#define CLKID_CPU_IN_DIV2 100
|
|
|
|
|
#define CLKID_CPU_IN_DIV3 101
|
2018-02-12 22:58:44 +08:00
|
|
|
#define CLKID_CPU_SCALE_DIV 102
|
|
|
|
|
#define CLKID_CPU_SCALE_OUT_SEL 103
|
2018-02-19 19:21:44 +08:00
|
|
|
#define CLKID_MPLL_PREDIV 104
|
2018-02-19 19:21:45 +08:00
|
|
|
#define CLKID_FCLK_DIV2_DIV 105
|
|
|
|
|
#define CLKID_FCLK_DIV3_DIV 106
|
|
|
|
|
#define CLKID_FCLK_DIV4_DIV 107
|
|
|
|
|
#define CLKID_FCLK_DIV5_DIV 108
|
|
|
|
|
#define CLKID_FCLK_DIV7_DIV 109
|
2018-04-24 03:35:09 +08:00
|
|
|
#define CLKID_NAND_SEL 110
|
|
|
|
|
#define CLKID_NAND_DIV 111
|
2018-08-01 22:00:52 +08:00
|
|
|
#define CLKID_PLL_FIXED_DCO 113
|
clk: meson: meson8b: add the read-only video clock trees
Add all clocks to give us the final video clocks within the Meson8,
Meson8b and Meson8m2 SoCs. The final video clocks are:
- cts_enct
- cts_encl
- cts_encp
- cts_enci
- cts_vdac0
- hdmi_tx_pixel
- hdmi_sys
Add multiple clocks in between which are needed to implement these
clocks:
- Opposed to GXBB there is no pre-multiplier for the PLL input. The
assumption here is that the multiplier is required to achieve the HDMI
2.0 clock rates (which are up to twice the rate of the HDMI 1.4
rates).
- The main PLL is called "HDMI PLL" or "HPLL" in the datasheet. Rename
our existing "vid_pll_dco" to "hdmi_pll_dco". The actual VID_PLL clock
also exists further down the tree.
- Rename the existing "vid_pll" clock (which is the OD divider at
HHI_VID_PLL_CNTL[17:16]) to "hdmi_pll_lvds_out" to match the naming
from the datasheet.
- Add the second OD divider called "hdmi_pll_hdmi_out" at
HHI_VID_PLL_CNTL[19:18].
- Add the "vid_pll_in_sel" which can choose between "hdmi_pll_dco" and
another parent. However, the second parent is not use on Amlogic's
3.10 kernel for HDMI or CVBS output so just leave a TODO in the code.
- Add the "vid_pll_in_en" which is located after "vid_pll_in_sel"
according to the datasheet.
- Add "vid_pll_pre_div" which is used for divide-by-5 and divide-by-6 in
Amlogic's 3.10 kernel sources.
- Add "vid_pll_post_div" which divides the output of "vid_pll_pre_div"
further down. The Amlogic 3.10 kernel configures this as divide-by-2
with "vid_pll_pre_div" being configured as divide-by-5 to achieve a
total divider of 10.
- Add the real "vid_pll" clock which selects between "vid_pll_pre_div",
"vid_pll_post_div" and a third "vid_pll_pre_div_mult7_div2" (which is
"vid_pll_pre_div" divided by 3.5). The latter is not supported yet
because it's not used in Amlogic's 3.10 kernel. The "vid_pll" clock
rate can also be measured by clkmsr to check whether this
implementation is correct.
- Add "vid_pll_final_div" which is a post-divider for "vid_pll" and it's
used as input for "vclk" and "vclk2"
- Add the two symmetric "vclk" and "vclk" clock trees, each with a
divide-by-1, divide-by-2, divide-by-4, divide-by-6 and divide-by-12
clock and a divider for each clock.
- Add the "cts_enct", "cts_encp" and "hdmi_tx_pixel" clocks which each
have their own gate and can select between any of the five "vclk"
dividers.
- Add the "cts_encl" and "cts_vdac0" clocks which each have their own
gate and can select between any of the five "vclk2" dividers.
The "hdmi_sys" clock is a different than these video clocks. It takes
"xtal" as input (there are three more but unknown parents). Add this
clock as well as it's used by the HDMI controller. Amlogic's 3.10 kernel
always configures this as "xtal divided by 1", so we can ignore the
other parents for now.
This was tested on Meson8b and Meson8m2 boards by comparing the common
clock framework output with the clock measurer output. The following
video modes were first set in u-boot (by running "video dev open $mode")
before booting Linux:
4K2K30HZ (only supported by Meson8m2, not tested on Meson8b):
- vid_pll: 297000000Hz
- cts_encp: 297000000Hz
- hdmi_tx_pixel: 297000000Hz
1080P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 148500000Hz
720P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 74250000Hz
480P:
- vid_pll: 216000000Hz
- cts_encp: 54000000Hz
- hdmi_tx_pixel: 27000000Hz
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-4-martin.blumenstingl@googlemail.com
2018-12-03 05:42:20 +08:00
|
|
|
#define CLKID_HDMI_PLL_DCO 114
|
2018-08-01 22:00:52 +08:00
|
|
|
#define CLKID_PLL_SYS_DCO 115
|
2018-11-23 05:40:17 +08:00
|
|
|
#define CLKID_CPU_CLK_DIV2 116
|
|
|
|
|
#define CLKID_CPU_CLK_DIV3 117
|
|
|
|
|
#define CLKID_CPU_CLK_DIV4 118
|
|
|
|
|
#define CLKID_CPU_CLK_DIV5 119
|
|
|
|
|
#define CLKID_CPU_CLK_DIV6 120
|
|
|
|
|
#define CLKID_CPU_CLK_DIV7 121
|
|
|
|
|
#define CLKID_CPU_CLK_DIV8 122
|
2019-02-11 06:26:03 +08:00
|
|
|
#define CLKID_APB_SEL 123
|
2018-11-23 05:40:17 +08:00
|
|
|
#define CLKID_PERIPH_SEL 125
|
|
|
|
|
#define CLKID_AXI_SEL 127
|
|
|
|
|
#define CLKID_L2_DRAM_SEL 129
|
clk: meson: meson8b: add the read-only video clock trees
Add all clocks to give us the final video clocks within the Meson8,
Meson8b and Meson8m2 SoCs. The final video clocks are:
- cts_enct
- cts_encl
- cts_encp
- cts_enci
- cts_vdac0
- hdmi_tx_pixel
- hdmi_sys
Add multiple clocks in between which are needed to implement these
clocks:
- Opposed to GXBB there is no pre-multiplier for the PLL input. The
assumption here is that the multiplier is required to achieve the HDMI
2.0 clock rates (which are up to twice the rate of the HDMI 1.4
rates).
- The main PLL is called "HDMI PLL" or "HPLL" in the datasheet. Rename
our existing "vid_pll_dco" to "hdmi_pll_dco". The actual VID_PLL clock
also exists further down the tree.
- Rename the existing "vid_pll" clock (which is the OD divider at
HHI_VID_PLL_CNTL[17:16]) to "hdmi_pll_lvds_out" to match the naming
from the datasheet.
- Add the second OD divider called "hdmi_pll_hdmi_out" at
HHI_VID_PLL_CNTL[19:18].
- Add the "vid_pll_in_sel" which can choose between "hdmi_pll_dco" and
another parent. However, the second parent is not use on Amlogic's
3.10 kernel for HDMI or CVBS output so just leave a TODO in the code.
- Add the "vid_pll_in_en" which is located after "vid_pll_in_sel"
according to the datasheet.
- Add "vid_pll_pre_div" which is used for divide-by-5 and divide-by-6 in
Amlogic's 3.10 kernel sources.
- Add "vid_pll_post_div" which divides the output of "vid_pll_pre_div"
further down. The Amlogic 3.10 kernel configures this as divide-by-2
with "vid_pll_pre_div" being configured as divide-by-5 to achieve a
total divider of 10.
- Add the real "vid_pll" clock which selects between "vid_pll_pre_div",
"vid_pll_post_div" and a third "vid_pll_pre_div_mult7_div2" (which is
"vid_pll_pre_div" divided by 3.5). The latter is not supported yet
because it's not used in Amlogic's 3.10 kernel. The "vid_pll" clock
rate can also be measured by clkmsr to check whether this
implementation is correct.
- Add "vid_pll_final_div" which is a post-divider for "vid_pll" and it's
used as input for "vclk" and "vclk2"
- Add the two symmetric "vclk" and "vclk" clock trees, each with a
divide-by-1, divide-by-2, divide-by-4, divide-by-6 and divide-by-12
clock and a divider for each clock.
- Add the "cts_enct", "cts_encp" and "hdmi_tx_pixel" clocks which each
have their own gate and can select between any of the five "vclk"
dividers.
- Add the "cts_encl" and "cts_vdac0" clocks which each have their own
gate and can select between any of the five "vclk2" dividers.
The "hdmi_sys" clock is a different than these video clocks. It takes
"xtal" as input (there are three more but unknown parents). Add this
clock as well as it's used by the HDMI controller. Amlogic's 3.10 kernel
always configures this as "xtal divided by 1", so we can ignore the
other parents for now.
This was tested on Meson8b and Meson8m2 boards by comparing the common
clock framework output with the clock measurer output. The following
video modes were first set in u-boot (by running "video dev open $mode")
before booting Linux:
4K2K30HZ (only supported by Meson8m2, not tested on Meson8b):
- vid_pll: 297000000Hz
- cts_encp: 297000000Hz
- hdmi_tx_pixel: 297000000Hz
1080P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 148500000Hz
720P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 74250000Hz
480P:
- vid_pll: 216000000Hz
- cts_encp: 54000000Hz
- hdmi_tx_pixel: 27000000Hz
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-4-martin.blumenstingl@googlemail.com
2018-12-03 05:42:20 +08:00
|
|
|
#define CLKID_HDMI_PLL_LVDS_OUT 131
|
|
|
|
|
#define CLKID_HDMI_PLL_HDMI_OUT 132
|
|
|
|
|
#define CLKID_VID_PLL_IN_SEL 133
|
|
|
|
|
#define CLKID_VID_PLL_IN_EN 134
|
|
|
|
|
#define CLKID_VID_PLL_PRE_DIV 135
|
|
|
|
|
#define CLKID_VID_PLL_POST_DIV 136
|
|
|
|
|
#define CLKID_VID_PLL_FINAL_DIV 137
|
|
|
|
|
#define CLKID_VCLK_IN_SEL 138
|
|
|
|
|
#define CLKID_VCLK_IN_EN 139
|
|
|
|
|
#define CLKID_VCLK_DIV1 140
|
|
|
|
|
#define CLKID_VCLK_DIV2_DIV 141
|
|
|
|
|
#define CLKID_VCLK_DIV2 142
|
|
|
|
|
#define CLKID_VCLK_DIV4_DIV 143
|
|
|
|
|
#define CLKID_VCLK_DIV4 144
|
|
|
|
|
#define CLKID_VCLK_DIV6_DIV 145
|
|
|
|
|
#define CLKID_VCLK_DIV6 146
|
|
|
|
|
#define CLKID_VCLK_DIV12_DIV 147
|
|
|
|
|
#define CLKID_VCLK_DIV12 148
|
|
|
|
|
#define CLKID_VCLK2_IN_SEL 149
|
|
|
|
|
#define CLKID_VCLK2_IN_EN 150
|
|
|
|
|
#define CLKID_VCLK2_DIV1 151
|
|
|
|
|
#define CLKID_VCLK2_DIV2_DIV 152
|
|
|
|
|
#define CLKID_VCLK2_DIV2 153
|
|
|
|
|
#define CLKID_VCLK2_DIV4_DIV 154
|
|
|
|
|
#define CLKID_VCLK2_DIV4 155
|
|
|
|
|
#define CLKID_VCLK2_DIV6_DIV 156
|
|
|
|
|
#define CLKID_VCLK2_DIV6 157
|
|
|
|
|
#define CLKID_VCLK2_DIV12_DIV 158
|
|
|
|
|
#define CLKID_VCLK2_DIV12 159
|
|
|
|
|
#define CLKID_CTS_ENCT_SEL 160
|
|
|
|
|
#define CLKID_CTS_ENCT 161
|
|
|
|
|
#define CLKID_CTS_ENCP_SEL 162
|
|
|
|
|
#define CLKID_CTS_ENCP 163
|
|
|
|
|
#define CLKID_CTS_ENCI_SEL 164
|
|
|
|
|
#define CLKID_CTS_ENCI 165
|
|
|
|
|
#define CLKID_HDMI_TX_PIXEL_SEL 166
|
|
|
|
|
#define CLKID_HDMI_TX_PIXEL 167
|
|
|
|
|
#define CLKID_CTS_ENCL_SEL 168
|
|
|
|
|
#define CLKID_CTS_ENCL 169
|
|
|
|
|
#define CLKID_CTS_VDAC0_SEL 170
|
|
|
|
|
#define CLKID_CTS_VDAC0 171
|
|
|
|
|
#define CLKID_HDMI_SYS_SEL 172
|
|
|
|
|
#define CLKID_HDMI_SYS_DIV 173
|
2018-12-09 01:12:45 +08:00
|
|
|
#define CLKID_MALI_0_SEL 175
|
|
|
|
|
#define CLKID_MALI_0_DIV 176
|
|
|
|
|
#define CLKID_MALI_0 177
|
|
|
|
|
#define CLKID_MALI_1_SEL 178
|
|
|
|
|
#define CLKID_MALI_1_DIV 179
|
|
|
|
|
#define CLKID_MALI_1 180
|
2019-03-24 23:11:03 +08:00
|
|
|
#define CLKID_GP_PLL_DCO 181
|
|
|
|
|
#define CLKID_GP_PLL 182
|
2019-03-24 23:11:04 +08:00
|
|
|
#define CLKID_VPU_0_SEL 183
|
|
|
|
|
#define CLKID_VPU_0_DIV 184
|
|
|
|
|
#define CLKID_VPU_0 185
|
|
|
|
|
#define CLKID_VPU_1_SEL 186
|
|
|
|
|
#define CLKID_VPU_1_DIV 187
|
|
|
|
|
#define CLKID_VPU_1 189
|
2019-03-24 23:14:23 +08:00
|
|
|
#define CLKID_VDEC_1_SEL 191
|
|
|
|
|
#define CLKID_VDEC_1_1_DIV 192
|
|
|
|
|
#define CLKID_VDEC_1_1 193
|
|
|
|
|
#define CLKID_VDEC_1_2_DIV 194
|
|
|
|
|
#define CLKID_VDEC_1_2 195
|
|
|
|
|
#define CLKID_VDEC_HCODEC_SEL 197
|
|
|
|
|
#define CLKID_VDEC_HCODEC_DIV 198
|
|
|
|
|
#define CLKID_VDEC_2_SEL 200
|
|
|
|
|
#define CLKID_VDEC_2_DIV 201
|
|
|
|
|
#define CLKID_VDEC_HEVC_SEL 203
|
|
|
|
|
#define CLKID_VDEC_HEVC_DIV 204
|
|
|
|
|
#define CLKID_VDEC_HEVC_EN 205
|
2019-05-21 04:03:17 +08:00
|
|
|
#define CLKID_CTS_AMCLK_SEL 207
|
|
|
|
|
#define CLKID_CTS_AMCLK_DIV 208
|
2019-05-21 04:03:18 +08:00
|
|
|
#define CLKID_CTS_MCLK_I958_SEL 210
|
|
|
|
|
#define CLKID_CTS_MCLK_I958_DIV 211
|
2018-02-12 22:58:43 +08:00
|
|
|
|
2019-05-21 04:03:19 +08:00
|
|
|
#define CLK_NR_CLKS 214
|
2016-08-28 01:40:52 +08:00
|
|
|
|
2017-07-29 05:13:12 +08:00
|
|
|
/*
|
|
|
|
|
* include the CLKID and RESETID that have
|
|
|
|
|
* been made part of the stable DT binding
|
|
|
|
|
*/
|
2016-08-28 01:40:52 +08:00
|
|
|
#include <dt-bindings/clock/meson8b-clkc.h>
|
2017-07-29 05:13:12 +08:00
|
|
|
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
|
2016-08-28 01:40:52 +08:00
|
|
|
|
2016-08-28 01:40:50 +08:00
|
|
|
#endif /* __MESON8B_H */
|