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linux/drivers/phy/amlogic/Makefile

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phy: Group vendor specific phy drivers Adding vendor specific directories in phy to group phy drivers under their respective vendor umbrella. Also updated the MAINTAINERS file to reflect the correct directory structure for phy drivers. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: David S. Miller <davem@davemloft.net> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-05-11 14:47:42 +08:00
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
phy: meson: add USB2 PHY support for Meson GXL and GXM This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout). The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY). Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-05-20 21:50:41 +08:00
obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
phy: amlogic: add Amlogic G12A USB2 PHY Driver This adds support for the USB2 PHY found in the Amlogic G12A SoC Family. It supports Host and/or Peripheral mode, depending on it's position. The first PHY is only used as Host, but the second supports Dual modes defined by the USB Control Glue HW in front of the USB Controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-03-25 17:39:40 +08:00
obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o
phy: amlogic: add USB3 PHY support for Meson GXL and GXM This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout). Unfortunately there is no documentation for this PHY in the public S905X datasheet (published for example by Khadas). What we know so far about this PHY: - even though the Meson GXL and GXM SoCs do not expose an USB3 port (the dwc3 controller only has USB2 ports enabled) we need to initialize the USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this initialization high-speed USB devices (especially USB hard disks and thumb drives, slower devices like mice do not seem to be affected) - on some boards the USB3 PHY starts in "device mode" - we want to bring it into a known state (by switching it to host mode for now). - it is responsible for the OTG detection and for switching the first USB2 PHY between host and peripheral (aka device) mode. an interrupt can be used to detect changes between host and device mode. There are five inputs to this register area: - the clock and reset line for the USB3 PHY itself - the clock and reset line for the peripheral mode and OTG detection logic (on the GXL and GXM SoCs these are the same clock and reset line as for the USB3 PHY itself, but Amlogic sees this as two different components - even though they share the same register space - so they have to be passed individually to allow specifying different inputs on other SoCs if needed) - the interrupt for the OTG detection logic The whole OTG detection logic is not implemented yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Yixun Lan <yixun.lan@amlogic.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-04 02:47:00 +08:00
obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o