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linux/arch/powerpc/include/asm/cputable.h

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[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#ifndef __ASM_POWERPC_CPUTABLE_H
#define __ASM_POWERPC_CPUTABLE_H
#define PPC_FEATURE_32 0x80000000
#define PPC_FEATURE_64 0x40000000
#define PPC_FEATURE_601_INSTR 0x20000000
#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
#define PPC_FEATURE_HAS_FPU 0x08000000
#define PPC_FEATURE_HAS_MMU 0x04000000
#define PPC_FEATURE_HAS_4xxMAC 0x02000000
#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
#define PPC_FEATURE_HAS_SPE 0x00800000
#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Merge changes from linux-2.6 by hand
2005-10-22 14:51:34 +08:00
#define PPC_FEATURE_NO_TB 0x00100000
powerpc: Add user CPU features for POWER4, POWER5, POWER5+ and Cell. This is at the request of the glibc folks, who want to use these bits to select libraries optimized for the microarchitecture and new instructions in these processors. Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-10 11:29:18 +08:00
#define PPC_FEATURE_POWER4 0x00080000
#define PPC_FEATURE_POWER5 0x00040000
#define PPC_FEATURE_POWER5_PLUS 0x00020000
#define PPC_FEATURE_CELL 0x00010000
powerpc: Provide a suitable AT_PLATFORM value The glibc folks want to use AT_PLATFORM to select between possible alternative versions of shared libraries. This commit makes the kernel supply an AT_PLATFORM string that indicates what class of processor we are running on. Processors with the same set of user-level instructions and roughly the same instruction scheduling characteristics are given the same AT_PLATFORM value; for example, 821, 823 and 860 are all reported as "ppc823", and 7447, 7447A, 7448, 7450, 7451, 7455 are all called "ppc7450". The intention is that the AT_PLATFORM values match the values that gcc accepts for the -mcpu= option. For values which are numeric (e.g. -mcpu=750), "ppc" has been prepended. This also adds a PPC_FEATURE_BOOKE bit to the AT_HWCAP value and sets it for the 440 family and the Freescale 85xx family. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-14 07:11:39 +08:00
#define PPC_FEATURE_BOOKE 0x00008000
[PATCH] powerpc: Expose SMT and L1 icache snoop userland features This patch makes userland aware of the icache snoop capability of the POWER5 (and possibly others in the future) and of SMT capabilities. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-01 12:07:07 +08:00
#define PPC_FEATURE_SMT 0x00004000
#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
[PATCH] powerpc: Add cputable entry for POWER6 Add a cputable entry for the POWER6 processor. The SIHV and SIPR bits in the mmcra have moved in POWER6, so disable support for that until oprofile is fixed. Also tell firmware that we know about POWER6. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-04-29 07:51:06 +08:00
#define PPC_FEATURE_ARCH_2_05 0x00001000
[POWERPC] powerpc: PA6T cputable entry, PVR value Introduce PWRficient PA6T cputable entries and feature bits. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-09-07 03:35:57 +08:00
#define PPC_FEATURE_PA6T 0x00000800
[POWERPC] Distinguish POWER6 partition modes and tell userspace This adds code to look at the properties firmware puts in the device tree to determine what compatibility mode the partition is in on POWER6 machines, and set the ELF aux vector AT_HWCAP and AT_PLATFORM entries appropriately. Specifically, we look at the cpu-version property in the cpu node(s). If that contains a "logical" PVR value (of the form 0x0f00000x), we call identify_cpu again with this PVR value. A value of 0x0f000001 indicates the partition is in POWER5+ compatibility mode, and a value of 0x0f000002 indicates "POWER6 architected" mode, with various extensions disabled. We also look for various other properties: ibm,dfp, ibm,purr and ibm,spurr. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-10 17:38:53 +08:00
#define PPC_FEATURE_HAS_DFP 0x00000400
#define PPC_FEATURE_POWER6_EXT 0x00000200
powerpc: Add cputable entry for POWER7 Add a cputable entry for the POWER7 processor. Also tell firmware that we know about POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-18 08:47:26 +08:00
#define PPC_FEATURE_ARCH_2_06 0x00000100
powerpc: Add VSX CPU feature Add a VSX CPU feature. Also add code to detect if VSX is available from the device tree. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-25 12:07:18 +08:00
#define PPC_FEATURE_HAS_VSX 0x00000080
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPAT Background from Maynard Johnson: As of POWER6, a set of 32 common events is defined that must be supported on all future POWER processors. The main impetus for this compat set is the need to support partition migration, especially from processor P(n) to processor P(n+1), where performance software that's running in the new partition may not be knowledgeable about processor P(n+1). If a performance tool determines it does not support the physical processor, but is told (via the PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports the notion of the PMU compat set, then the performance tool can surface just those events to the user of the tool. PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at least this basic subset of events which is compatible across POWER processor lines. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2008-07-09 23:06:57 +08:00
#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
0x00000040
[PATCH] powerpc: Implement support for setting little-endian mode via prctl This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-07 14:14:40 +08:00
#define PPC_FEATURE_TRUE_LE 0x00000002
#define PPC_FEATURE_PPC_LE 0x00000001
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#ifdef __KERNEL__
powerpc: Don't export asm/asm-compat.h to userspace asm/asm-compat.h doesn't seem to be intended for userspace usage. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-24 01:48:21 +08:00
#include <asm/asm-compat.h>
powerpc: Consolidate CPU and firmware feature fixup macros The CPU and firmware feature fixup macros are currently spread across three files, firmware.h, cputable.h and asm-compat.h. Consolidate them into their own file, feature-fixups.h Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-24 09:32:39 +08:00
#include <asm/feature-fixups.h>
powerpc: Don't export asm/asm-compat.h to userspace asm/asm-compat.h doesn't seem to be intended for userspace usage. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-24 01:48:21 +08:00
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#ifndef __ASSEMBLY__
/* This structure can grow, it's real size is used by head.S code
* via the mkdefs mechanism.
*/
struct cpu_spec;
typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
[POWERPC] Cleanup CPU inits Cleanup CPU inits a bit more, Geoff Levand already did some earlier. * Move CPU state save to cpu_setup, since cpu_setup is only ever done on cpu 0 on 64-bit and save is never done more than once. * Rename __restore_cpu_setup to __restore_cpu_ppc970 and add function pointers to the cputable to use instead. Powermac always has 970 so no need to check there. * Rename __970_cpu_preinit to __cpu_preinit_ppc970 and check PVR before calling it instead of in it, it's too early to use cputable. * Rename pSeries_secondary_smp_init to generic_secondary_smp_init since everyone but powermac and iSeries use it. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-08-11 13:07:08 +08:00
typedef void (*cpu_restore_t)(void);
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
[PATCH] ppc64: Fix oprofile when compiled as a module My recent changes to oprofile broke it when built as a module. Fix it by using an enum instead of a function pointer. This way we still retain the oprofile configuration in the cputable. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-09 12:41:31 +08:00
enum powerpc_oprofile_type {
[PATCH] powerpc: oprofile cpu type names clash with other code In 2.6.15-git6 a change was commited in the oprofile support in the powerpc architecture. It introduced the powerpc_oprofile_type which contains the define G4. This causes a name clash with the existing wacom usb tablet driver. CC [M] drivers/usb/input/wacom.o drivers/usb/input/wacom.c:98: error: conflicting types for `G4' include/asm/cputable.h:37: error: previous declaration of `G4' CC [M] drivers/usb/mon/mon_text.o make[3]: *** [drivers/usb/input/wacom.o] Error 1 make[2]: *** [drivers/usb/input] Error 2 The elements of an enum declared in global scope are effectivly global identifiers themselves. As such we need to ensure the names are unique. This patch updates the later oprofile support to use unique names. Signed-off-by: Andy Whitcroft <apw@shadowen.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-13 20:35:49 +08:00
PPC_OPROFILE_INVALID = 0,
PPC_OPROFILE_RS64 = 1,
PPC_OPROFILE_POWER4 = 2,
PPC_OPROFILE_G4 = 3,
[POWERPC] Made FSL Book-E PMC support more generic Some of the more recent e300 cores have the same performance monitor implementation as the e500. e300 isn't book-e, so the name isn't really appropriate. In preparation for e300 support, rename a bunch of fsl_booke things to say fsl_emb (Freescale Embedded Performance Monitors). Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-02-05 08:27:55 +08:00
PPC_OPROFILE_FSL_EMB = 4,
[POWERPC] cell: Add oprofile support Add PPU event-based and cycle-based profiling support to Oprofile for Cell. Oprofile is expected to collect data on all CPUs simultaneously. However, there is one set of performance counters per node. There are two hardware threads or virtual CPUs on each node. Hence, OProfile must multiplex in time the performance counter collection on the two virtual CPUs. The multiplexing of the performance counters is done by a virtual counter routine. Initially, the counters are configured to collect data on the even CPUs in the system, one CPU per node. In order to capture the PC for the virtual CPU when the performance counter interrupt occurs (the specified number of events between samples has occurred), the even processors are configured to handle the performance counter interrupts for their node. The virtual counter routine is called via a kernel timer after the virtual sample time. The routine stops the counters, saves the current counts, loads the last counts for the other virtual CPU on the node, sets interrupts to be handled by the other virtual CPU and restarts the counters, the virtual timer routine is scheduled to run again. The virtual sample time is kept relatively small to make sure sampling occurs on both CPUs on the node with a relatively small granularity. Whenever the counters overflow, the performance counter interrupt is called to collect the PC for the CPU where data is being collected. The oprofile driver relies on a firmware RTAS call to setup the debug bus to route the desired signals to the performance counter hardware to be counted. The RTAS call must set the routing registers appropriately in each of the islands to pass the signals down the debug bus as well as routing the signals from a particular island onto the bus. There is a second firmware RTAS call to reset the debug bus to the non pass thru state when the counters are not in use. Signed-off-by: Carl Love <carll@us.ibm.com> Signed-off-by: Maynard Johnson <mpjohn@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-21 01:45:16 +08:00
PPC_OPROFILE_CELL = 5,
[POWERPC] pasemi: PA6T oprofile support Oprofile support for PA6T, kernel side. Also rename the PA6T_SPRN.* defines to SPRN_PA6T.*. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-04-18 14:38:21 +08:00
PPC_OPROFILE_PA6T = 6,
[PATCH] ppc64: Fix oprofile when compiled as a module My recent changes to oprofile broke it when built as a module. Fix it by using an enum instead of a function pointer. This way we still retain the oprofile configuration in the cputable. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-09 12:41:31 +08:00
};
[POWERPC] Add PMC type to cputable Add cputable entries for which type of PMC implementation the processor has. I've only filled in the current 64-bit processors, the unfilled default value will have same behaviour as before so it can be done over time as needed. Also tidy up the dummy_perf implementation a bit, aggregating it into one function with ifdefs instead of several. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-01-29 11:23:54 +08:00
enum powerpc_pmc_type {
PPC_PMC_DEFAULT = 0,
PPC_PMC_IBM = 1,
PPC_PMC_PA6T = 2,
powerpc: Expose PMCs & cache topology in sysfs on 32-bit The file arch/powerpc/kernel/sysfs.c is currently only compiled for 64-bit kernels. It contain code to register CPU sysdevs in sysfs and add various properties such as cache topology and raw access by root to performance monitor counters (PMCs). A lot of that can be re-used as is on 32-bits. This makes the file be built for both, with appropriate ifdef'ing for the few bits that are really 64-bit specific, and adds some support for the raw PMCs for 75x and 74xx processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-18 12:23:51 +08:00
PPC_PMC_G4 = 3,
[POWERPC] Add PMC type to cputable Add cputable entries for which type of PMC implementation the processor has. I've only filled in the current 64-bit processors, the unfilled default value will have same behaviour as before so it can be done over time as needed. Also tidy up the dummy_perf implementation a bit, aggregating it into one function with ifdefs instead of several. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-01-29 11:23:54 +08:00
};
[POWERPC] Reworking machine check handling and Fix 440/440A This adds a cputable function pointer for the CPU-side machine check handling. The semantic is still the same as the old one, the one in ppc_md. overrides the one in cputable, though ultimately we'll want to change that so the CPU gets first. This removes CONFIG_440A which was a problem for multiplatform kernels and instead fixes up the IVOR at runtime from a setup_cpu function. The "A" version of the machine check also tweaks the regs->trap value to differenciate the 2 versions at the C level. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-12-21 12:39:21 +08:00
struct pt_regs;
extern int machine_check_generic(struct pt_regs *regs);
extern int machine_check_4xx(struct pt_regs *regs);
extern int machine_check_440A(struct pt_regs *regs);
powerpc/e500mc: Implement machine check handler. Most of the MSCR bit assigments are different in e500mc versus e500, and they are now write-one-to-clear. Some e500mc machine check conditions are made recoverable (as long as they aren't stuck on), most notably L1 instruction cache parity errors. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-08 13:38:22 +08:00
extern int machine_check_e500mc(struct pt_regs *regs);
[POWERPC] Reworking machine check handling and Fix 440/440A This adds a cputable function pointer for the CPU-side machine check handling. The semantic is still the same as the old one, the one in ppc_md. overrides the one in cputable, though ultimately we'll want to change that so the CPU gets first. This removes CONFIG_440A which was a problem for multiplatform kernels and instead fixes up the IVOR at runtime from a setup_cpu function. The "A" version of the machine check also tweaks the regs->trap value to differenciate the 2 versions at the C level. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-12-21 12:39:21 +08:00
extern int machine_check_e500(struct pt_regs *regs);
extern int machine_check_e200(struct pt_regs *regs);
powerpc/476: add machine check handler for 47x core The 47x core's MCSR varies from 44x, so it needs it's own machine check handler. Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2010-03-05 11:43:18 +08:00
extern int machine_check_47x(struct pt_regs *regs);
[POWERPC] Reworking machine check handling and Fix 440/440A This adds a cputable function pointer for the CPU-side machine check handling. The semantic is still the same as the old one, the one in ppc_md. overrides the one in cputable, though ultimately we'll want to change that so the CPU gets first. This removes CONFIG_440A which was a problem for multiplatform kernels and instead fixes up the IVOR at runtime from a setup_cpu function. The "A" version of the machine check also tweaks the regs->trap value to differenciate the 2 versions at the C level. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-12-21 12:39:21 +08:00
[POWERPC] Fix performance monitor on machines with logical PVR Some IBM machines supply a "logical" PVR (processor version register) value in the device tree in the cpu nodes rather than the real PVR. This is used for instance to indicate that the processors in a POWER6 partition have been configured by the hypervisor to run in POWER5+ mode rather than POWER6 mode. To cope with this, we call identify_cpu a second time with the logical PVR value (the first call is with the real PVR value in the very early setup code). However, POWER5+ machines can also supply a logical PVR value, and use the same value (the value that indicates a v2.04 architecture compliant processor). This causes problems for code that uses the performance monitor (such as oprofile), because the PMU registers are different in POWER6 (even in POWER5+ mode) from the real POWER5+. This change works around this problem by taking out the PMU information from the cputable entries for the logical PVR values, and changing identify_cpu so that the second call to it won't overwrite the PMU information that was established by the first call (the one with the real PVR), but does update the other fields. Specifically, if the cputable entry for the logical PVR value has num_pmcs == 0, none of the PMU-related fields get used. So that we can create a mixed cputable entry, we now make cur_cpu_spec point to a single static struct cpu_spec, and copy stuff from cpu_specs[i] into it. This has the side-effect that we can now make cpu_specs[] be initdata. Ultimately it would be good to move the PMU-related fields out to a separate structure, pointed to by the cputable entries, and change identify_cpu so that it saves the PMU info pointer, copies the whole structure, and restores the PMU info pointer, rather than identify_cpu having to list all the fields that are *not* PMU-related. Signed-off-by: Paul Mackerras <paulus@samba.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2007-10-04 12:18:01 +08:00
/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
struct cpu_spec {
/* CPU is matched via (PVR & pvr_mask) == pvr_value */
unsigned int pvr_mask;
unsigned int pvr_value;
char *cpu_name;
unsigned long cpu_features; /* Kernel features */
unsigned int cpu_user_features; /* Userland features */
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
unsigned int mmu_features; /* MMU features */
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
/* cache line sizes */
unsigned int icache_bsize;
unsigned int dcache_bsize;
/* number of performance monitor counters */
unsigned int num_pmcs;
[POWERPC] Add PMC type to cputable Add cputable entries for which type of PMC implementation the processor has. I've only filled in the current 64-bit processors, the unfilled default value will have same behaviour as before so it can be done over time as needed. Also tidy up the dummy_perf implementation a bit, aggregating it into one function with ifdefs instead of several. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-01-29 11:23:54 +08:00
enum powerpc_pmc_type pmc_type;
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
/* this is called to initialize various CPU bits like L1 cache,
* BHT, SPD, etc... from head.S before branching to identify_machine
*/
cpu_setup_t cpu_setup;
[POWERPC] Cleanup CPU inits Cleanup CPU inits a bit more, Geoff Levand already did some earlier. * Move CPU state save to cpu_setup, since cpu_setup is only ever done on cpu 0 on 64-bit and save is never done more than once. * Rename __restore_cpu_setup to __restore_cpu_ppc970 and add function pointers to the cputable to use instead. Powermac always has 970 so no need to check there. * Rename __970_cpu_preinit to __cpu_preinit_ppc970 and check PVR before calling it instead of in it, it's too early to use cputable. * Rename pSeries_secondary_smp_init to generic_secondary_smp_init since everyone but powermac and iSeries use it. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-08-11 13:07:08 +08:00
/* Used to restore cpu setup on secondary processors and at resume */
cpu_restore_t cpu_restore;
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
/* Used by oprofile userspace to select the right counters */
char *oprofile_cpu_type;
/* Processor specific oprofile operations */
[PATCH] ppc64: Fix oprofile when compiled as a module My recent changes to oprofile broke it when built as a module. Fix it by using an enum instead of a function pointer. This way we still retain the oprofile configuration in the cputable. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-09 12:41:31 +08:00
enum powerpc_oprofile_type oprofile_type;
powerpc: Provide a suitable AT_PLATFORM value The glibc folks want to use AT_PLATFORM to select between possible alternative versions of shared libraries. This commit makes the kernel supply an AT_PLATFORM string that indicates what class of processor we are running on. Processors with the same set of user-level instructions and roughly the same instruction scheduling characteristics are given the same AT_PLATFORM value; for example, 821, 823 and 860 are all reported as "ppc823", and 7447, 7447A, 7448, 7450, 7451, 7455 are all called "ppc7450". The intention is that the AT_PLATFORM values match the values that gcc accepts for the -mcpu= option. For values which are numeric (e.g. -mcpu=750), "ppc" has been prepended. This also adds a PPC_FEATURE_BOOKE bit to the AT_HWCAP value and sets it for the 440 family and the Freescale 85xx family. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-14 07:11:39 +08:00
[PATCH] powerpc: oprofile support for POWER6 POWER6 moves some of the MMCRA bits and also requires some bits to be cleared each PMU interrupt. Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-08 12:42:34 +08:00
/* Bit locations inside the mmcra change */
unsigned long oprofile_mmcra_sihv;
unsigned long oprofile_mmcra_sipr;
/* Bits to clear during an oprofile exception */
unsigned long oprofile_mmcra_clear;
powerpc: Provide a suitable AT_PLATFORM value The glibc folks want to use AT_PLATFORM to select between possible alternative versions of shared libraries. This commit makes the kernel supply an AT_PLATFORM string that indicates what class of processor we are running on. Processors with the same set of user-level instructions and roughly the same instruction scheduling characteristics are given the same AT_PLATFORM value; for example, 821, 823 and 860 are all reported as "ppc823", and 7447, 7447A, 7448, 7450, 7451, 7455 are all called "ppc7450". The intention is that the AT_PLATFORM values match the values that gcc accepts for the -mcpu= option. For values which are numeric (e.g. -mcpu=750), "ppc" has been prepended. This also adds a PPC_FEATURE_BOOKE bit to the AT_HWCAP value and sets it for the 440 family and the Freescale 85xx family. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-14 07:11:39 +08:00
/* Name of processor class, for the ELF AT_PLATFORM entry */
char *platform;
[POWERPC] Reworking machine check handling and Fix 440/440A This adds a cputable function pointer for the CPU-side machine check handling. The semantic is still the same as the old one, the one in ppc_md. overrides the one in cputable, though ultimately we'll want to change that so the CPU gets first. This removes CONFIG_440A which was a problem for multiplatform kernels and instead fixes up the IVOR at runtime from a setup_cpu function. The "A" version of the machine check also tweaks the regs->trap value to differenciate the 2 versions at the C level. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-12-21 12:39:21 +08:00
/* Processor specific machine check handling. Return negative
* if the error is fatal, 1 if it was fully recovered and 0 to
* pass up (not CPU originated) */
int (*machine_check)(struct pt_regs *regs);
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
};
extern struct cpu_spec *cur_cpu_spec;
[POWERPC] Consolidate feature fixup code There are currently two versions of the functions for applying the feature fixups, one for CPU features and one for firmware features. In addition, they are both in assembly and with separate implementations for 32 and 64 bits. identify_cpu() is also implemented in assembly and separately for 32 and 64 bits. This patch replaces them with a pair of C functions. The call sites are slightly moved on ppc64 as well to be called from C instead of from assembly, though it's a very small change, and thus shouldn't cause any problem. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-24 14:42:40 +08:00
extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
[POWERPC] Distinguish POWER6 partition modes and tell userspace This adds code to look at the properties firmware puts in the device tree to determine what compatibility mode the partition is in on POWER6 machines, and set the ELF aux vector AT_HWCAP and AT_PLATFORM entries appropriately. Specifically, we look at the cpu-version property in the cpu node(s). If that contains a "logical" PVR value (of the form 0x0f00000x), we call identify_cpu again with this PVR value. A value of 0x0f000001 indicates the partition is in POWER5+ compatibility mode, and a value of 0x0f000002 indicates "POWER6 architected" mode, with various extensions disabled. We also look for various other properties: ibm,dfp, ibm,purr and ibm,spurr. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-10 17:38:53 +08:00
extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
[POWERPC] Support feature fixups in vdso's This patch reworks the feature fixup mecanism so vdso's can be fixed up. The main issue was that the construct: .long label (or .llong on 64 bits) will not work in the case of a shared library like the vdso. It will generate an empty placeholder in the fixup table along with a reloc, which is not something we can deal with in the vdso. The idea here (thanks Alan Modra !) is to instead use something like: 1: .long label - 1b That is, the feature fixup tables no longer contain addresses of bits of code to patch, but offsets of such code from the fixup table entry itself. That is properly resolved by ld when building the .so's. I've modified the fixup mecanism generically to use that method for the rest of the kernel as well. Another trick is that the 32 bits vDSO included in the 64 bits kernel need to have a table in the 64 bits format. However, gas does not support 32 bits code with a statement of the form: .llong label - 1b (Or even just .llong label) That is, it cannot emit the right fixup/relocation for the linker to use to assign a 32 bits address to an .llong field. Thus, in the specific case of the 32 bits vdso built as part of the 64 bits kernel, we are using a modified macro that generates: .long 0xffffffff .llong label - 1b Note that is assumes that the value is negative which is enforced by the .lds (those offsets are always negative as the .text is always before the fixup table and gas doesn't support emiting the reloc the other way around). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-20 09:47:18 +08:00
extern void do_feature_fixups(unsigned long value, void *fixup_start,
void *fixup_end);
powerpc: Merge in the ppc64 version of the prom code. This brings in the ppc64 version of prom_init.c, prom.c and btext.c and makes them work for ppc32. This also brings in the new calling convention, where the first entry to the kernel (with r5 != 0) goes to the prom_init code, which then restarts from the beginning (with r5 == 0) after it has done its stuff. For now this also brings in the ppc32 version of setup.c. It also merges lmb.h. Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-06 10:06:20 +08:00
powerpc: Enable AT_BASE_PLATFORM aux vector Stash the first platform string matched by identify_cpu() in powerpc_base_platform, and supply that to the ELF loader for the value of AT_BASE_PLATFORM. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2008-07-16 07:58:51 +08:00
extern const char *powerpc_base_platform;
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#endif /* __ASSEMBLY__ */
/* CPU kernel features */
/* Retain the 32b definitions all use bottom half of word */
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
powerpc/e500mc: flush L2 on NAP for e500mc If we have an L2CSR register (e500mc) we need to flush the L2 before going to nap. We use the HW flush mechanism provided in that register. The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by any code in the kernel. Additionally we didn't reuse the exist L2CR feature bit as this is intended for the 7xxx L2CR register and L2CSR is part of the new Freescale "Book-E" registers. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-19 22:40:31 +08:00
#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
powerpc: Add support for using doorbells for SMP IPI The e500mc supports the new msgsnd/doorbell mechanisms that were added in the Power ISA 2.05 architecture. We use the normal level doorbell for doing SMP IPIs at this point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-12 21:54:53 +08:00
#define CPU_FTR_DBELL ASM_CONST(0x0000000000000200)
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
powerpc/476: define specific cpu table entry DD2 core The DD2 core still has some unstability. Define CPU_FTR_476_DD2 to enable workarounds in later patches. This is based on an earlier, unreleased patch for DD1 by Ben Herrenschmidt. Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2011-01-26 14:17:58 +08:00
#define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000)
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
powerpc/fsl-booke64: Add support for Debug Level exception handler Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-06 13:18:48 +08:00
#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x0000000000080000)
[PATCH] powerpc: trivial: Cleanup whitespace in cputable.h Remove redundant whitespace in include/asm-powerpc/cputable.h Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-21 17:45:58 +08:00
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
[PATCH] powerpc: Implement support for setting little-endian mode via prctl This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-07 14:14:40 +08:00
#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
[POWERPC] Add support for FP emulation for the e300c2 core The e300c2 has no FPU. Its MSR[FP] is grounded to zero. If an attempt is made to execute a floating point instruction (including floating-point load, store, or move instructions), the e300c2 takes a floating-point unavailable interrupt. This patch adds support for FP emulation on the e300c2 by declaring a new CPU_FTR_FP_TAKES_FPUNAVAIL, where FP unavail interrupts are intercepted and redirected to the ProgramCheck exception path for correct emulation handling. (If we run out of CPU_FTR bits we could look to reclaim this bit by adding support to test the cpu_user_features for PPC_FEATURE_HAS_FPU instead) It adds a nop to the exception path for 32-bit processors with a FPU. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2006-12-08 16:43:30 +08:00
#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
[POWERPC] Add cpu feature for SPE handling Make it so that SPE support can be determined at runtime. This is similiar to how we handle AltiVec. This allows us to have SPE support built in and work on processors with and without SPE. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-13 14:44:20 +08:00
#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
powerpc: Fixup lwsync at runtime To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up the code. We default to 'sync' since that is always safe and if the cpu is capable we will replace 'sync' with 'lwsync'. We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is needed. This flag could be moved elsewhere since we dont really use it for the normal CPU_FTR purpose. Finally we only store the relative offset in the fixup section to keep it as small as possible rather than using a full fixup_entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-07-01 23:16:40 +08:00
#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
powerpc: Fix bogus cache flushing on all 40x and BookE processors v2 We were missing the CPU_FTR_NOEXECUTE bit in our cputable for all these processors. The result is that update_mmu_cache() would flush the cache for all pages mapped to userspace which is totally unnecessary on those processors since we already handle flushing on execute in the page fault path. This should provide a nice speed up ;-) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-12 14:33:25 +08:00
#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000)
powerpc/4xx: Extended DCR support v2 This adds supports to the "extended" DCR addressing via the indirect mfdcrx/mtdcrx instructions supported by some 4xx cores (440H6 and later). I enabled the feature for now only on AMCC 460 chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:22 +08:00
#define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000)
KVM: PPC: e500mc support Add processor support for e500mc, using hardware virtualization support (GS-mode). Current issues include: - No support for external proxy (coreint) interrupt mode in the guest. Includes work by Ashish Kalra <Ashish.Kalra@freescale.com>, Varun Sethi <Varun.Sethi@freescale.com>, and Liu Yu <yu.liu@freescale.com>. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-20 23:34:47 +08:00
#define CPU_FTR_EMB_HV ASM_CONST(0x0000000040000000)
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
[POWERPC] Simplify the code defining the 64-bit CPU features Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-28 11:50:39 +08:00
/*
* Add the 64-bit processor unique features in the top half of the word;
* on 32-bit, make the names available but defined to be 0.
*/
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#ifdef __powerpc64__
[POWERPC] Simplify the code defining the 64-bit CPU features Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-28 11:50:39 +08:00
#define LONG_ASM_CONST(x) ASM_CONST(x)
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#else
[POWERPC] Simplify the code defining the 64-bit CPU features Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-28 11:50:39 +08:00
#define LONG_ASM_CONST(x) 0
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#endif
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to indicate that we have a usable hypervisor mode, and another to indicate that the processor conforms to PowerISA version 2.06. We also add another bit to indicate that the processor conforms to ISA version 2.01 and set that for PPC970 and derivatives. Some PPC970 chips (specifically those in Apple machines) have a hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode is not useful in the sense that there is no way to run any code in supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1 bits in HID4 are always 0, and we use that as a way of detecting that hypervisor mode is not useful. Where we have a feature section in assembly code around code that only applies on POWER7 in hypervisor mode, we use a construct like END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) The definition of END_FTR_SECTION_IFSET is such that the code will be enabled (not overwritten with nops) only if all bits in the provided mask are set. Note that the CPU feature check in __tlbie() only needs to check the ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called if we are running bare-metal, i.e. in hypervisor mode. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 08:26:11 +08:00
#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000200000000)
#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000400000000)
#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000800000000)
powerpc: Save Come-From Address Register (CFAR) in exception frame Recent 64-bit server processors (POWER6 and POWER7) have a "Come-From Address Register" (CFAR), that records the address of the most recent branch or rfid (return from interrupt) instruction for debugging purposes. This saves the value of the CFAR in the exception entry code and stores it in the exception frame. We also make xmon print the CFAR value in its register dump code. Rather than extend the pt_regs struct at this time, we steal the orig_gpr3 field, which is only used for system calls, and use it for the CFAR value for all exceptions/interrupts other than system calls. This means we don't save the CFAR on system calls, which is not a great problem since system calls tend not to happen unexpectedly, and also avoids adding the overhead of reading the CFAR to the system call entry path. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-05-02 03:48:20 +08:00
#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000001000000000)
[POWERPC] Simplify the code defining the 64-bit CPU features Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-28 11:50:39 +08:00
#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
[POWERPC] Cell timebase bug workaround The Cell CPU timebase has an erratum. When reading the entire 64 bits of the timebase with one mftb instruction, there is a handful of cycles window during which one might read a value with the low order 32 bits already reset to 0x00000000 but the high order bits not yet incremeted by one. This fixes it by reading the timebase again until the low order 32 bits is no longer 0. That might introduce occasional latencies if hitting mftb just at the wrong time, but no more than 70ns on a cell blade, and that was considered acceptable. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-20 12:37:05 +08:00
#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
[POWERPC] Distinguish POWER6 partition modes and tell userspace This adds code to look at the properties firmware puts in the device tree to determine what compatibility mode the partition is in on POWER6 machines, and set the ELF aux vector AT_HWCAP and AT_PLATFORM entries appropriately. Specifically, we look at the cpu-version property in the cpu node(s). If that contains a "logical" PVR value (of the form 0x0f00000x), we call identify_cpu again with this PVR value. A value of 0x0f000001 indicates the partition is in POWER5+ compatibility mode, and a value of 0x0f000002 indicates "POWER6 architected" mode, with various extensions disabled. We also look for various other properties: ibm,dfp, ibm,purr and ibm,spurr. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-10 17:38:53 +08:00
#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
[POWERPC] Add DSCR SPR to sysfs POWER6 adds a new SPR, the data stream control register (DSCR). It can be used to adjust how agressive the prefetch mechanisms are. Its possible we may want to context switch this, but for now just export it to userspace via sysfs so we can adjust it. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-12-08 14:46:58 +08:00
#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
powerpc: Add VSX CPU feature Add a VSX CPU feature. Also add code to detect if VSX is available from the device tree. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-25 12:07:18 +08:00
#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
powerpc/mm: Add SAO Feature bit to the cputable Add the CPU feature bit for the new Strong Access Ordering facility of Power7 Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2008-07-07 22:28:53 +08:00
#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
powerpc: Add new CPU feature: CPU_FTR_CP_USE_DCBTZ Add a new CPU feature bit, CPU_FTR_CP_USE_DCBTZ, to be added to the 64bit powerpc chips that benefit from having dcbt and dcbz instructions used in their memory copy routines. This will be used in a subsequent patch that updates copy_4K_page(). The new bit is added to Cell, PPC970 and Power4 because they show better performance with the new copy_4K_page() when dcbt and dcbz instructions are used. Signed-off-by: Mark Nelson <markn@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-22 12:36:19 +08:00
#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
powerpc: Add new CPU feature: CPU_FTR_UNALIGNED_LD_STD Add a new CPU feature bit, CPU_FTR_UNALIGNED_LD_STD, to be added to the 64bit powerpc chips that can do unaligned load double and store double without any performance hit. This is added to Power6 and Cell and will be used in the next commit to disable the code that gets the destination address aligned on those CPUs where doing that doesn't improve performance. Signed-off-by: Mark Nelson <markn@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-10-27 08:43:02 +08:00
#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
powerpc: Enable asymmetric SMT scheduling on POWER7 The POWER7 core has dynamic SMT mode switching which is controlled by the hypervisor. There are 3 SMT modes: SMT1 uses thread 0 SMT2 uses threads 0 & 1 SMT4 uses threads 0, 1, 2 & 3 When in any particular SMT mode, all threads have the same performance as each other (ie. at any moment in time, all threads perform the same). The SMT mode switching works such that when linux has threads 2 & 3 idle and 0 & 1 active, it will cede (H_CEDE hypercall) threads 2 and 3 in the idle loop and the hypervisor will automatically switch to SMT2 for that core (independent of other cores). The opposite is not true, so if threads 0 & 1 are idle and 2 & 3 are active, we will stay in SMT4 mode. Similarly if thread 0 is active and threads 1, 2 & 3 are idle, we'll go into SMT1 mode. If we can get the core into a lower SMT mode (SMT1 is best), the threads will perform better (since they share less core resources). Hence when we have idle threads, we want them to be the higher ones. This adds a feature bit for asymmetric packing to powerpc and then enables it on POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: linuxppc-dev@ozlabs.org LKML-Reference: <20100608045702.31FB5CC8C7@localhost.localdomain> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-08 12:57:02 +08:00
#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000)
powerpc: Feature nop out reservation clear when stcx checks address The POWER architecture does not require stcx to check that it is operating on the same address as the larx. This means it is possible for an an exception handler to execute a larx, get a reservation, decide not to do the stcx and then return back with an active reservation. If the interrupted code was in the middle of a larx/stcx sequence the stcx could incorrectly succeed. All recent POWER CPUs check the address before letting the stcx succeed so we can create a CPU feature and nop it out. As Ben suggested, we can only do this in our syscall path because there is a remote possibility some kernel code gets interrupted by an exception that ends up operating on the same cacheline. Thanks to Paul Mackerras and Derek Williams for the idea. To test this I used a very simple null syscall (actually getppid) testcase at http://ozlabs.org/~anton/junkcode/null_syscall.c I tested against 2.6.35-git10 with the following changes against the pseries_defconfig: CONFIG_VIRT_CPU_ACCOUNTING=n CONFIG_AUDIT=n CONFIG_PPC_4K_PAGES=n CONFIG_PPC_64K_PAGES=y CONFIG_FORCE_MAX_ZONEORDER=9 CONFIG_PPC_SUBPAGE_PROT=n CONFIG_FUNCTION_TRACER=n CONFIG_FUNCTION_GRAPH_TRACER=n CONFIG_IRQSOFF_TRACER=n CONFIG_STACK_TRACER=n to remove the overhead of virtual CPU accounting, syscall auditing and the ftrace mcount tracers. 64kB pages were enabled to minimise TLB misses. POWER6: +8.2% POWER7: +7.0% Another suggestion was to use a larx to something in the L1 instead of a stcx. This was almost as fast as removing the larx on POWER6, but only 3.5% faster on POWER7. We can use this to speed up the reservation clear in our exception exit code. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-11 09:40:27 +08:00
#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000)
powerpc: Add support for popcnt instructions POWER5 added popcntb, and POWER7 added popcntw and popcntd. As a first step this patch does all the work out of line, but it would be nice to implement them as inlines with an out of line fallback. The performance issue with hweight was noticed when disabling SMT on a large (192 thread) POWER7 box. The patch improves that testcase by about 8%. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-13 00:28:09 +08:00
#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000)
#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000)
powerpc: Add Initiate Coprocessor Store Word (icswx) support Icswx is a PowerPC instruction to send data to a co-processor. On Book-S processors the LPAR_ID and process ID (PID) of the owning process are registered in the window context of the co-processor at initialization time. When the icswx instruction is executed the L2 generates a cop-reg transaction on PowerBus. The transaction has no address and the processor does not perform an MMU access to authenticate the transaction. The co-processor compares the LPAR_ID and the PID included in the transaction and the LPAR_ID and PID held in the window context to determine if the process is authorized to generate the transaction. The OS needs to assign a 16-bit PID for the process. This cop-PID needs to be updated during context switch. The cop-PID needs to be destroyed when the context is destroyed. Signed-off-by: Sonny Rao <sonnyrao@linux.vnet.ibm.com> Signed-off-by: Tseng-Hui (Frank) Lin <thlin@linux.vnet.ibm.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-05-03 04:43:04 +08:00
#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000)
powerpc: POWER7 optimised copy_to_user/copy_from_user using VMX Implement a POWER7 optimised copy_to_user/copy_from_user using VMX. For large aligned copies this new loop is over 10% faster, and for large unaligned copies it is over 200% faster. If we take a fault we fall back to the old version, this keeps things relatively simple and easy to verify. On POWER7 unaligned stores rarely slow down - they only flush when a store crosses a 4KB page boundary. Furthermore this flush is handled completely in hardware and should be 20-30 cycles. Unaligned loads on the other hand flush much more often - whenever crossing a 128 byte cache line, or a 32 byte sector if either sector is an L1 miss. Considering this information we really want to get the loads aligned and not worry about the alignment of the stores. Microbenchmarks confirm that this approach is much faster than the current unaligned copy loop that uses shifts and rotates to ensure both loads and stores are aligned. We also want to try and do the stores in cacheline aligned, cacheline sized chunks. If the store queue is unable to merge an entire cacheline of stores then the L2 cache will have to do a read/modify/write. Even worse, we will serialise this with the stores in the next iteration of the copy loop since both iterations hit the same cacheline. Based on this, the new loop does the following things: 1 - 127 bytes Get the source 8 byte aligned and use 8 byte loads and stores. Pretty boring and similar to how the current loop works. 128 - 4095 bytes Get the source 8 byte aligned and use 8 byte loads and stores, 1 cacheline at a time. We aren't doing the stores in cacheline aligned chunks so we will potentially serialise once per cacheline. Even so it is much better than the loop we have today. 4096 - bytes If both source and destination have the same alignment get them both 16 byte aligned, then get the destination cacheline aligned. Do cacheline sized loads and stores using VMX. If source and destination do not have the same alignment, we get the destination cacheline aligned, and use permute to do aligned loads. In both cases the VMX loop should be optimal - we always do aligned loads and stores and are always doing stores in cacheline aligned, cacheline sized chunks. To be able to use VMX we must be careful about interrupts and sleeping. We don't use the VMX loop when in an interrupt (which should be rare anyway) and we wrap the VMX loop in disable/enable_pagefault and fall back to the existing copy_tofrom_user loop if we do need to sleep. The VMX breakpoint of 4096 bytes was chosen using this microbenchmark: http://ozlabs.org/~anton/junkcode/copy_to_user.c Since we are using VMX and there is a cost to saving and restoring the user VMX state there are two broad cases we need to benchmark: - Best case - userspace never uses VMX - Worst case - userspace always uses VMX In reality a userspace process will sit somewhere between these two extremes. Since we need to test both aligned and unaligned copies we end up with 4 combinations. The point at which the VMX loop begins to win is: 0% VMX aligned 2048 bytes unaligned 2048 bytes 100% VMX aligned 16384 bytes unaligned 8192 bytes Considering this is a microbenchmark, the data is hot in cache and the VMX loop has better store queue merging properties we set the breakpoint to 4096 bytes, a little below the unaligned breakpoints. Some future optimisations we can look at: - Looking at the perf data, a significant part of the cost when a task is always using VMX is the extra exception we take to restore the VMX state. As such we should do something similar to the x86 optimisation that restores FPU state for heavy users. ie: /* * If the task has used fpu the last 5 timeslices, just do a full * restore of the math state immediately to avoid the trap; the * chances of needing FPU soon are obviously high now */ preload_fpu = tsk_used_math(next_p) && next_p->fpu_counter > 5; and /* * fpu_counter contains the number of consecutive context switches * that the FPU is used. If this is over a threshold, the lazy fpu * saving becomes unlazy to save the trap. This is an unsigned char * so that after 256 times the counter wraps and the behavior turns * lazy again; this to deal with bursty apps that only use FPU for * a short time */ - We could create a paca bit to mirror the VMX enabled MSR bit and check that first, avoiding multiple calls to calling enable_kernel_altivec. That should help with iovec based system calls like readv. - We could have two VMX breakpoints, one for when we know the user VMX state is loaded into the registers and one when it isn't. This could be a second bit in the paca so we can calculate the break points quickly. - One suggestion from Ben was to save and restore the VSX registers we use inline instead of using enable_kernel_altivec. [BenH: Fixed a problem with preempt and fixed build without CONFIG_ALTIVEC] Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08 04:11:45 +08:00
#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x2000000000000000)
[POWERPC] Simplify the code defining the 64-bit CPU features Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-28 11:50:39 +08:00
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#ifndef __ASSEMBLY__
powerpc: Free up some CPU feature bits by moving out MMU-related features Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-04-07 03:48:50 +08:00
#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
MMU_FTR_16M_PAGE)
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
/* We only set the altivec features if the kernel was compiled with altivec
* support
*/
#ifdef CONFIG_ALTIVEC
#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
#else
#define CPU_FTR_ALTIVEC_COMP 0
#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
#endif
powerpc: Add VSX CPU feature Add a VSX CPU feature. Also add code to detect if VSX is available from the device tree. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-25 12:07:18 +08:00
/* We only set the VSX features if the kernel was compiled with VSX
* support
*/
#ifdef CONFIG_VSX
#define CPU_FTR_VSX_COMP CPU_FTR_VSX
#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
#else
#define CPU_FTR_VSX_COMP 0
#define PPC_FEATURE_HAS_VSX_COMP 0
#endif
[POWERPC] Add cpu feature for SPE handling Make it so that SPE support can be determined at runtime. This is similiar to how we handle AltiVec. This allows us to have SPE support built in and work on processors with and without SPE. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-13 14:44:20 +08:00
/* We only set the spe features if the kernel was compiled with spe
* support
*/
#ifdef CONFIG_SPE
#define CPU_FTR_SPE_COMP CPU_FTR_SPE
#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
#else
#define CPU_FTR_SPE_COMP 0
#define PPC_FEATURE_HAS_SPE_COMP 0
#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
#endif
[POWERPC] mpc82xx: Define CPU_FTR_NEED_COHERENT The 8272 (and presumably other PCI PQ2 chips) appear to have the same issue as the 83xx regarding PCI streaming DMA. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-15 04:32:14 +08:00
/* We need to mark all pages as being coherent if we're SMP or we have a
* 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
* require it for PCI "streaming/prefetch" to work properly.
powerpc/5200: Enable CPU_FTR_NEED_COHERENT for MPC52xx BestComm, a DMA engine in MPC52xx SoC, requires snooping when CPU caches are enabled to work properly. Adding CPU_FTR_NEED_COHERENT fixes NFS problems on MPC52xx machines introduced by 'powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup code' (sha1: 4c456a67f501b8b15542c7c21c28812bf88f484b). Signed-off-by: Piotr Ziecik <kosmo@semihalf.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2009-03-17 23:17:50 +08:00
* This is also required by 52xx family.
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
*/
[PATCH] powerpc: Enable coherency for all pages on 83xx to fix PCI data corruption On the 83xx platform to ensure the PCI inbound memory is handled properly we have to turn on coherency for all pages in the MMU. Otherwise we see corruption if inbound "prefetching/streaming" is enabled on the PCI controller. Signed-off-by: Randy Vinson <rvinson@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-22 23:46:02 +08:00
#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
powerpc/5200: Enable CPU_FTR_NEED_COHERENT for MPC52xx BestComm, a DMA engine in MPC52xx SoC, requires snooping when CPU caches are enabled to work properly. Adding CPU_FTR_NEED_COHERENT fixes NFS problems on MPC52xx machines introduced by 'powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup code' (sha1: 4c456a67f501b8b15542c7c21c28812bf88f484b). Signed-off-by: Piotr Ziecik <kosmo@semihalf.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2009-03-17 23:17:50 +08:00
|| defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
|| defined(CONFIG_PPC_MPC52xx)
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
#else
#define CPU_FTR_COMMON 0
#endif
/* The powersave features NAP & DOZE seems to confuse BDI when
debugging. So if a BDI is used, disable theses
*/
#ifndef CONFIG_BDI_SWITCH
#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
#else
#define CPU_FTR_MAYBE_CAN_DOZE 0
#define CPU_FTR_MAYBE_CAN_NAP 0
#endif
#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
!defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
!defined(CONFIG_BOOKE))
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
#define CPU_FTRS_603 (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
[PATCH] powerpc: Implement support for setting little-endian mode via prctl This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-07 14:14:40 +08:00
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_604 (CPU_FTR_COMMON | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_740 (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
[PATCH] powerpc: Implement support for setting little-endian mode via prctl This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-07 14:14:40 +08:00
CPU_FTR_PPC_LE)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_750 (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
[PATCH] powerpc: Implement support for setting little-endian mode via prctl This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-07 14:14:40 +08:00
CPU_FTR_PPC_LE)
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
#define CPU_FTRS_750CL (CPU_FTRS_750)
[POWERPC] Consolidate PowerPC 750 cputable features The 750 CPU_FTR macros have quite a bit of duplication in them. Consolidate them to use CPU_FTRS_750 and only list the unique features for derivatives. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-07-03 00:06:53 +08:00
#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
[POWERPC] Consolidate PowerPC 750 cputable features The 750 CPU_FTR macros have quite a bit of duplication in them. Consolidate them to use CPU_FTRS_750 and only list the unique features for derivatives. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-07-03 00:06:53 +08:00
#define CPU_FTRS_750GX (CPU_FTRS_750FX)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_ALTIVEC_COMP | \
[PATCH] powerpc: Implement support for setting little-endian mode via prctl This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-07 14:14:40 +08:00
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
[PATCH] powerpc: Implement support for setting little-endian mode via prctl This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-07 14:14:40 +08:00
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
[PATCH] powerpc: Implement support for setting little-endian mode via prctl This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-07 14:14:40 +08:00
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
CPU_FTR_NEED_PAIRED_STWCX)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
[POWERPC] Remove CPU_FTR_NEED_COHERENT for 7448. Remove CPU_FTR_NEED_COHERENT for MPC7448 (and single-core MPC86xx). This prevents needlessly setting M=1 when not SMP. Signed-off-by: James.Yang <James.Yang@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-05-03 05:34:43 +08:00
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
[POWERPC] Avoid unpaired stwcx. on some processors The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-10 06:17:49 +08:00
CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
[POWERPC] mpc82xx: Define CPU_FTR_NEED_COHERENT The 8272 (and presumably other PCI PQ2 chips) appear to have the same issue as the 83xx regarding PCI streaming DMA. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-15 04:32:14 +08:00
#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_COMMON)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
[POWERPC] Add support for FP emulation for the e300c2 core The e300c2 has no FPU. Its MSR[FP] is grounded to zero. If an attempt is made to execute a floating point instruction (including floating-point load, store, or move instructions), the e300c2 takes a floating-point unavailable interrupt. This patch adds support for FP emulation on the e300c2 by declaring a new CPU_FTR_FP_TAKES_FPUNAVAIL, where FP unavail interrupts are intercepted and redirected to the ProgramCheck exception path for correct emulation handling. (If we run out of CPU_FTR bits we could look to reclaim this bit by adding support to test the cpu_user_features for PPC_FEATURE_HAS_FPU instead) It adds a nop to the exception path for 32-bit processors with a FPU. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2006-12-08 16:43:30 +08:00
CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
[POWERPC] Merge CPU features pertaining to icache coherency Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-13 12:52:57 +08:00
#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
powerpc: Fix bogus cache flushing on all 40x and BookE processors v2 We were missing the CPU_FTR_NOEXECUTE bit in our cputable for all these processors. The result is that update_mmu_cache() would flush the cache for all pages mapped to userspace which is totally unnecessary on those processors since we already handle flushing on execute in the page fault path. This should provide a nice speed up ;-) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-12 14:33:25 +08:00
#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
powerpc/4xx: Extended DCR support v2 This adds supports to the "extended" DCR addressing via the indirect mfdcrx/mtdcrx instructions supported by some 4xx cores (440H6 and later). I enabled the feature for now only on AMCC 460 chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:22 +08:00
#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
CPU_FTR_INDEXED_DCR)
powerpc/47x: Base ppc476 support This patch adds the base support for the 476 processor. The code was primarily written by Ben Herrenschmidt and Torez Smith, but I've been maintaining it for a while. The goal is to have a single binary that will run on 44x and 47x, but we still have some details to work out. The biggest is that the L1 cache line size differs on the two platforms, but it's currently a compile-time option. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2010-03-05 18:43:12 +08:00
#define CPU_FTRS_47X (CPU_FTRS_440x6)
[POWERPC] Add cpu feature for SPE handling Make it so that SPE support can be determined at runtime. This is similiar to how we handle AltiVec. This allows us to have SPE support built in and work on processors with and without SPE. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-13 14:44:20 +08:00
#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
powerpc/booke: Set CPU_FTR_DEBUG_LVL_EXC on 32-bit Currently 32-bit only cares about this for choice of exception vector, which is done in core-specific code. However, KVM will want to distinguish as well. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-20 23:34:12 +08:00
CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
CPU_FTR_DEBUG_LVL_EXC)
powerpc/85xx: add DOZE/NAP support for e500 core The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-19 05:26:52 +08:00
#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
powerpc: Fix bogus cache flushing on all 40x and BookE processors v2 We were missing the CPU_FTR_NOEXECUTE bit in our cputable for all these processors. The result is that update_mmu_cache() would flush the cache for all pages mapped to userspace which is totally unnecessary on those processors since we already handle flushing on execute in the page fault path. This should provide a nice speed up ;-) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-12 14:33:25 +08:00
CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
CPU_FTR_NOEXECUTE)
powerpc/85xx: add DOZE/NAP support for e500 core The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-19 05:26:52 +08:00
#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
powerpc: Fix bogus cache flushing on all 40x and BookE processors v2 We were missing the CPU_FTR_NOEXECUTE bit in our cputable for all these processors. The result is that update_mmu_cache() would flush the cache for all pages mapped to userspace which is totally unnecessary on those processors since we already handle flushing on execute in the page fault path. This should provide a nice speed up ;-) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-12 14:33:25 +08:00
CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
powerpc/e500mc: Remove CPU_FTR_MAYBE_CAN_NAP/CPU_FTR_MAYBE_CAN_DOZE e500mc does not support the HID0/MSR mechanism that is used by e500_idle (and there are also issues with waking on certain types of interrupts). Further, even if napping is never actually enabled, just having CPU_FTR_CAN_NAP will cause machine_init() to overwrite the board's supplied ppc_md.power_save(). We drop CPU_FTR_MAYBE_CAN_DOZE becuase we should use 'wait' instead on e500mc. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-28 06:35:12 +08:00
#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
powerpc: Add support for using doorbells for SMP IPI The e500mc supports the new msgsnd/doorbell mechanisms that were added in the Power ISA 2.05 architecture. We use the normal level doorbell for doing SMP IPIs at this point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-12 21:54:53 +08:00
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
KVM: PPC: e500mc support Add processor support for e500mc, using hardware virtualization support (GS-mode). Current issues include: - No support for external proxy (coreint) interrupt mode in the guest. Includes work by Ashish Kalra <Ashish.Kalra@freescale.com>, Varun Sethi <Varun.Sethi@freescale.com>, and Liu Yu <yu.liu@freescale.com>. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-20 23:34:47 +08:00
CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
powerpc/book3e: Fix CPU feature handling on 64-bit e5500 The CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS defines did not encompass e5500 CPU features when built for 64-bit. This causes issues with cpu_has_feature() as it utilizes the POSSIBLE & ALWAYS defines as part of its check. Create a unique CPU_FTRS_E5500 (as its different from CPU_FTRS_E500MC), created a new group for 64-bit Book3e based CPUs and add CPU_FTRS_E5500 to that group. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-06 13:11:06 +08:00
#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
powerpc/fsl-booke64: Add support for Debug Level exception handler Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-06 13:18:48 +08:00
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
KVM: PPC: e500mc support Add processor support for e500mc, using hardware virtualization support (GS-mode). Current issues include: - No support for external proxy (coreint) interrupt mode in the guest. Includes work by Ashish Kalra <Ashish.Kalra@freescale.com>, Varun Sethi <Varun.Sethi@freescale.com>, and Liu Yu <yu.liu@freescale.com>. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-20 23:34:47 +08:00
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
powerpc: Add initial e6500 cpu support Add basic support for e6500 core in its single threaded mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-07 01:51:07 +08:00
#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
KVM: PPC: add CPU_FTR_EMB_HV to CPU table e6500 support (commit 10241842fbe900276634fee8d37ec48a7d8a762f, "powerpc: Add initial e6500 cpu support" and the introduction of CPU_FTR_EMB_HV (commit 73196cd364a2d972d73fa08da9d81ca3215bed68, "KVM: PPC: e500mc support") collided during merge, leaving e6500's CPU table entry missing CPU_FTR_EMB_HV. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2012-04-12 04:27:52 +08:00
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
[POWERPC] Make 64-bit cpu features defined on 32-bit It saves #ifdef'ing in callers if we at least define the 64-bit cpu features for 32-bit also. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2006-11-23 07:46:46 +08:00
/* 64-bit CPUs */
powerpc: Use lwsync for acquire barrier if CPU supports it Nick Piggin discovered that lwsync barriers around locks were faster than isync on 970. That was a long time ago and I completely dropped the ball in testing his patches across other ppc64 processors. Turns out the idea helps on other chips. Using a microbenchmark that uses a lot of threads to contend on a global pthread mutex (and therefore a global futex), POWER6 improves 8% and POWER7 improves 2%. I checked POWER5 and while I couldn't measure an improvement, there was no regression. This patch uses the lwsync patching code to replace the isyncs with lwsyncs on CPUs that support the instruction. We were marking POWER3 and RS64 as lwsync capable but in reality they treat it as a full sync (ie slow). Remove the CPU_FTR_LWSYNC bit from these CPUs so they continue to use the faster isync method. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-02-10 09:10:25 +08:00
#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_IABR | CPU_FTR_PPC_LE)
powerpc: Use lwsync for acquire barrier if CPU supports it Nick Piggin discovered that lwsync barriers around locks were faster than isync on 970. That was a long time ago and I completely dropped the ball in testing his patches across other ppc64 processors. Turns out the idea helps on other chips. Using a microbenchmark that uses a lot of threads to contend on a global pthread mutex (and therefore a global futex), POWER6 improves 8% and POWER7 improves 2%. I checked POWER5 and while I couldn't measure an improvement, there was no regression. This patch uses the lwsync patching code to replace the isyncs with lwsyncs on CPUs that support the instruction. We were marking POWER3 and RS64 as lwsync capable but in reality they treat it as a full sync (ie slow). Remove the CPU_FTR_LWSYNC bit from these CPUs so they continue to use the faster isync method. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-02-10 09:10:25 +08:00
#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_IABR | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MMCRA | CPU_FTR_CTRL)
powerpc: Fixup lwsync at runtime To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up the code. We default to 'sync' since that is always safe and if the cpu is capable we will replace 'sync' with 'lwsync'. We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is needed. This flag could be moved elsewhere since we dont really use it for the normal CPU_FTR purpose. Finally we only store the relative offset in the fixup section to keep it as small as possible rather than using a full fixup_entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-07-01 23:16:40 +08:00
#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
powerpc: Feature nop out reservation clear when stcx checks address The POWER architecture does not require stcx to check that it is operating on the same address as the larx. This means it is possible for an an exception handler to execute a larx, get a reservation, decide not to do the stcx and then return back with an active reservation. If the interrupted code was in the middle of a larx/stcx sequence the stcx could incorrectly succeed. All recent POWER CPUs check the address before letting the stcx succeed so we can create a CPU feature and nop it out. As Ben suggested, we can only do this in our syscall path because there is a remote possibility some kernel code gets interrupted by an exception that ends up operating on the same cacheline. Thanks to Paul Mackerras and Derek Williams for the idea. To test this I used a very simple null syscall (actually getppid) testcase at http://ozlabs.org/~anton/junkcode/null_syscall.c I tested against 2.6.35-git10 with the following changes against the pseries_defconfig: CONFIG_VIRT_CPU_ACCOUNTING=n CONFIG_AUDIT=n CONFIG_PPC_4K_PAGES=n CONFIG_PPC_64K_PAGES=y CONFIG_FORCE_MAX_ZONEORDER=9 CONFIG_PPC_SUBPAGE_PROT=n CONFIG_FUNCTION_TRACER=n CONFIG_FUNCTION_GRAPH_TRACER=n CONFIG_IRQSOFF_TRACER=n CONFIG_STACK_TRACER=n to remove the overhead of virtual CPU accounting, syscall auditing and the ftrace mcount tracers. 64kB pages were enabled to minimise TLB misses. POWER6: +8.2% POWER7: +7.0% Another suggestion was to use a larx to something in the L1 instead of a stcx. This was almost as fast as removing the larx on POWER6, but only 3.5% faster on POWER7. We can use this to speed up the reservation clear in our exception exit code. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-11 09:40:27 +08:00
CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
CPU_FTR_STCX_CHECKS_ADDRESS)
powerpc: Fixup lwsync at runtime To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up the code. We default to 'sync' since that is always safe and if the cpu is capable we will replace 'sync' with 'lwsync'. We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is needed. This flag could be moved elsewhere since we dont really use it for the normal CPU_FTR purpose. Finally we only store the relative offset in the fixup section to keep it as small as possible rather than using a full fixup_entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-07-01 23:16:40 +08:00
#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to indicate that we have a usable hypervisor mode, and another to indicate that the processor conforms to PowerISA version 2.06. We also add another bit to indicate that the processor conforms to ISA version 2.01 and set that for PPC970 and derivatives. Some PPC970 chips (specifically those in Apple machines) have a hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode is not useful in the sense that there is no way to run any code in supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1 bits in HID4 are always 0, and we use that as a way of detecting that hypervisor mode is not useful. Where we have a feature section in assembly code around code that only applies on POWER7 in hypervisor mode, we use a construct like END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) The definition of END_FTR_SECTION_IFSET is such that the code will be enabled (not overwritten with nops) only if all bits in the provided mask are set. Note that the CPU feature check in __tlbie() only needs to check the ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called if we are running bare-metal, i.e. in hypervisor mode. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 08:26:11 +08:00
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
powerpc: Add new CPU feature: CPU_FTR_CP_USE_DCBTZ Add a new CPU feature bit, CPU_FTR_CP_USE_DCBTZ, to be added to the 64bit powerpc chips that benefit from having dcbt and dcbz instructions used in their memory copy routines. This will be used in a subsequent patch that updates copy_4K_page(). The new bit is added to Cell, PPC970 and Power4 because they show better performance with the new copy_4K_page() when dcbt and dcbz instructions are used. Signed-off-by: Mark Nelson <markn@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-22 12:36:19 +08:00
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to indicate that we have a usable hypervisor mode, and another to indicate that the processor conforms to PowerISA version 2.06. We also add another bit to indicate that the processor conforms to ISA version 2.01 and set that for PPC970 and derivatives. Some PPC970 chips (specifically those in Apple machines) have a hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode is not useful in the sense that there is no way to run any code in supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1 bits in HID4 are always 0, and we use that as a way of detecting that hypervisor mode is not useful. Where we have a feature section in assembly code around code that only applies on POWER7 in hypervisor mode, we use a construct like END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) The definition of END_FTR_SECTION_IFSET is such that the code will be enabled (not overwritten with nops) only if all bits in the provided mask are set. Note that the CPU feature check in __tlbie() only needs to check the ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called if we are running bare-metal, i.e. in hypervisor mode. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 08:26:11 +08:00
CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
CPU_FTR_HVMODE)
powerpc: Fixup lwsync at runtime To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up the code. We default to 'sync' since that is always safe and if the cpu is capable we will replace 'sync' with 'lwsync'. We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is needed. This flag could be moved elsewhere since we dont really use it for the normal CPU_FTR purpose. Finally we only store the relative offset in the fixup section to keep it as small as possible rather than using a full fixup_entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-07-01 23:16:40 +08:00
#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_MMCRA | CPU_FTR_SMT | \
powerpc: Free up some CPU feature bits by moving out MMU-related features Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-04-07 03:48:50 +08:00
CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
powerpc: Fixup lwsync at runtime To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up the code. We default to 'sync' since that is always safe and if the cpu is capable we will replace 'sync' with 'lwsync'. We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is needed. This flag could be moved elsewhere since we dont really use it for the normal CPU_FTR purpose. Finally we only store the relative offset in the fixup section to keep it as small as possible rather than using a full fixup_entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-07-01 23:16:40 +08:00
#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
[PATCH] powerpc: Add cputable entry for POWER6 Add a cputable entry for the POWER6 processor. The SIHV and SIPR bits in the mmcra have moved in POWER6, so disable support for that until oprofile is fixed. Also tell firmware that we know about POWER6. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-04-29 07:51:06 +08:00
CPU_FTR_MMCRA | CPU_FTR_SMT | \
powerpc: Free up some CPU feature bits by moving out MMU-related features Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-04-07 03:48:50 +08:00
CPU_FTR_COHERENT_ICACHE | \
[POWERPC] Add DSCR SPR to sysfs POWER6 adds a new SPR, the data stream control register (DSCR). It can be used to adjust how agressive the prefetch mechanisms are. Its possible we may want to context switch this, but for now just export it to userspace via sysfs so we can adjust it. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-12-08 14:46:58 +08:00
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
powerpc: Feature nop out reservation clear when stcx checks address The POWER architecture does not require stcx to check that it is operating on the same address as the larx. This means it is possible for an an exception handler to execute a larx, get a reservation, decide not to do the stcx and then return back with an active reservation. If the interrupted code was in the middle of a larx/stcx sequence the stcx could incorrectly succeed. All recent POWER CPUs check the address before letting the stcx succeed so we can create a CPU feature and nop it out. As Ben suggested, we can only do this in our syscall path because there is a remote possibility some kernel code gets interrupted by an exception that ends up operating on the same cacheline. Thanks to Paul Mackerras and Derek Williams for the idea. To test this I used a very simple null syscall (actually getppid) testcase at http://ozlabs.org/~anton/junkcode/null_syscall.c I tested against 2.6.35-git10 with the following changes against the pseries_defconfig: CONFIG_VIRT_CPU_ACCOUNTING=n CONFIG_AUDIT=n CONFIG_PPC_4K_PAGES=n CONFIG_PPC_64K_PAGES=y CONFIG_FORCE_MAX_ZONEORDER=9 CONFIG_PPC_SUBPAGE_PROT=n CONFIG_FUNCTION_TRACER=n CONFIG_FUNCTION_GRAPH_TRACER=n CONFIG_IRQSOFF_TRACER=n CONFIG_STACK_TRACER=n to remove the overhead of virtual CPU accounting, syscall auditing and the ftrace mcount tracers. 64kB pages were enabled to minimise TLB misses. POWER6: +8.2% POWER7: +7.0% Another suggestion was to use a larx to something in the L1 instead of a stcx. This was almost as fast as removing the larx on POWER6, but only 3.5% faster on POWER7. We can use this to speed up the reservation clear in our exception exit code. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-11 09:40:27 +08:00
CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
powerpc: Save Come-From Address Register (CFAR) in exception frame Recent 64-bit server processors (POWER6 and POWER7) have a "Come-From Address Register" (CFAR), that records the address of the most recent branch or rfid (return from interrupt) instruction for debugging purposes. This saves the value of the CFAR in the exception entry code and stores it in the exception frame. We also make xmon print the CFAR value in its register dump code. Rather than extend the pt_regs struct at this time, we steal the orig_gpr3 field, which is only used for system calls, and use it for the CFAR value for all exceptions/interrupts other than system calls. This means we don't save the CFAR on system calls, which is not a great problem since system calls tend not to happen unexpectedly, and also avoids adding the overhead of reading the CFAR to the system call entry path. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-05-02 03:48:20 +08:00
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
powerpc: Fixup lwsync at runtime To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up the code. We default to 'sync' since that is always safe and if the cpu is capable we will replace 'sync' with 'lwsync'. We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is needed. This flag could be moved elsewhere since we dont really use it for the normal CPU_FTR purpose. Finally we only store the relative offset in the fixup section to keep it as small as possible rather than using a full fixup_entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-07-01 23:16:40 +08:00
#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to indicate that we have a usable hypervisor mode, and another to indicate that the processor conforms to PowerISA version 2.06. We also add another bit to indicate that the processor conforms to ISA version 2.01 and set that for PPC970 and derivatives. Some PPC970 chips (specifically those in Apple machines) have a hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode is not useful in the sense that there is no way to run any code in supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1 bits in HID4 are always 0, and we use that as a way of detecting that hypervisor mode is not useful. Where we have a feature section in assembly code around code that only applies on POWER7 in hypervisor mode, we use a construct like END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) The definition of END_FTR_SECTION_IFSET is such that the code will be enabled (not overwritten with nops) only if all bits in the provided mask are set. Note that the CPU feature check in __tlbie() only needs to check the ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called if we are running bare-metal, i.e. in hypervisor mode. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 08:26:11 +08:00
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
powerpc: Add cputable entry for POWER7 Add a cputable entry for the POWER7 processor. Also tell firmware that we know about POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-18 08:47:26 +08:00
CPU_FTR_MMCRA | CPU_FTR_SMT | \
powerpc: Free up some CPU feature bits by moving out MMU-related features Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-04-07 03:48:50 +08:00
CPU_FTR_COHERENT_ICACHE | \
powerpc: Add cputable entry for POWER7 Add a cputable entry for the POWER7 processor. Also tell firmware that we know about POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-18 08:47:26 +08:00
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
powerpc: Feature nop out reservation clear when stcx checks address The POWER architecture does not require stcx to check that it is operating on the same address as the larx. This means it is possible for an an exception handler to execute a larx, get a reservation, decide not to do the stcx and then return back with an active reservation. If the interrupted code was in the middle of a larx/stcx sequence the stcx could incorrectly succeed. All recent POWER CPUs check the address before letting the stcx succeed so we can create a CPU feature and nop it out. As Ben suggested, we can only do this in our syscall path because there is a remote possibility some kernel code gets interrupted by an exception that ends up operating on the same cacheline. Thanks to Paul Mackerras and Derek Williams for the idea. To test this I used a very simple null syscall (actually getppid) testcase at http://ozlabs.org/~anton/junkcode/null_syscall.c I tested against 2.6.35-git10 with the following changes against the pseries_defconfig: CONFIG_VIRT_CPU_ACCOUNTING=n CONFIG_AUDIT=n CONFIG_PPC_4K_PAGES=n CONFIG_PPC_64K_PAGES=y CONFIG_FORCE_MAX_ZONEORDER=9 CONFIG_PPC_SUBPAGE_PROT=n CONFIG_FUNCTION_TRACER=n CONFIG_FUNCTION_GRAPH_TRACER=n CONFIG_IRQSOFF_TRACER=n CONFIG_STACK_TRACER=n to remove the overhead of virtual CPU accounting, syscall auditing and the ftrace mcount tracers. 64kB pages were enabled to minimise TLB misses. POWER6: +8.2% POWER7: +7.0% Another suggestion was to use a larx to something in the L1 instead of a stcx. This was almost as fast as removing the larx on POWER6, but only 3.5% faster on POWER7. We can use this to speed up the reservation clear in our exception exit code. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-11 09:40:27 +08:00
CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
powerpc: Add Initiate Coprocessor Store Word (icswx) support Icswx is a PowerPC instruction to send data to a co-processor. On Book-S processors the LPAR_ID and process ID (PID) of the owning process are registered in the window context of the co-processor at initialization time. When the icswx instruction is executed the L2 generates a cop-reg transaction on PowerBus. The transaction has no address and the processor does not perform an MMU access to authenticate the transaction. The co-processor compares the LPAR_ID and the PID included in the transaction and the LPAR_ID and PID held in the window context to determine if the process is authorized to generate the transaction. The OS needs to assign a 16-bit PID for the process. This cop-PID needs to be updated during context switch. The cop-PID needs to be destroyed when the context is destroyed. Signed-off-by: Sonny Rao <sonnyrao@linux.vnet.ibm.com> Signed-off-by: Tseng-Hui (Frank) Lin <thlin@linux.vnet.ibm.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-05-03 04:43:04 +08:00
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
powerpc: POWER7 optimised copy_to_user/copy_from_user using VMX Implement a POWER7 optimised copy_to_user/copy_from_user using VMX. For large aligned copies this new loop is over 10% faster, and for large unaligned copies it is over 200% faster. If we take a fault we fall back to the old version, this keeps things relatively simple and easy to verify. On POWER7 unaligned stores rarely slow down - they only flush when a store crosses a 4KB page boundary. Furthermore this flush is handled completely in hardware and should be 20-30 cycles. Unaligned loads on the other hand flush much more often - whenever crossing a 128 byte cache line, or a 32 byte sector if either sector is an L1 miss. Considering this information we really want to get the loads aligned and not worry about the alignment of the stores. Microbenchmarks confirm that this approach is much faster than the current unaligned copy loop that uses shifts and rotates to ensure both loads and stores are aligned. We also want to try and do the stores in cacheline aligned, cacheline sized chunks. If the store queue is unable to merge an entire cacheline of stores then the L2 cache will have to do a read/modify/write. Even worse, we will serialise this with the stores in the next iteration of the copy loop since both iterations hit the same cacheline. Based on this, the new loop does the following things: 1 - 127 bytes Get the source 8 byte aligned and use 8 byte loads and stores. Pretty boring and similar to how the current loop works. 128 - 4095 bytes Get the source 8 byte aligned and use 8 byte loads and stores, 1 cacheline at a time. We aren't doing the stores in cacheline aligned chunks so we will potentially serialise once per cacheline. Even so it is much better than the loop we have today. 4096 - bytes If both source and destination have the same alignment get them both 16 byte aligned, then get the destination cacheline aligned. Do cacheline sized loads and stores using VMX. If source and destination do not have the same alignment, we get the destination cacheline aligned, and use permute to do aligned loads. In both cases the VMX loop should be optimal - we always do aligned loads and stores and are always doing stores in cacheline aligned, cacheline sized chunks. To be able to use VMX we must be careful about interrupts and sleeping. We don't use the VMX loop when in an interrupt (which should be rare anyway) and we wrap the VMX loop in disable/enable_pagefault and fall back to the existing copy_tofrom_user loop if we do need to sleep. The VMX breakpoint of 4096 bytes was chosen using this microbenchmark: http://ozlabs.org/~anton/junkcode/copy_to_user.c Since we are using VMX and there is a cost to saving and restoring the user VMX state there are two broad cases we need to benchmark: - Best case - userspace never uses VMX - Worst case - userspace always uses VMX In reality a userspace process will sit somewhere between these two extremes. Since we need to test both aligned and unaligned copies we end up with 4 combinations. The point at which the VMX loop begins to win is: 0% VMX aligned 2048 bytes unaligned 2048 bytes 100% VMX aligned 16384 bytes unaligned 8192 bytes Considering this is a microbenchmark, the data is hot in cache and the VMX loop has better store queue merging properties we set the breakpoint to 4096 bytes, a little below the unaligned breakpoints. Some future optimisations we can look at: - Looking at the perf data, a significant part of the cost when a task is always using VMX is the extra exception we take to restore the VMX state. As such we should do something similar to the x86 optimisation that restores FPU state for heavy users. ie: /* * If the task has used fpu the last 5 timeslices, just do a full * restore of the math state immediately to avoid the trap; the * chances of needing FPU soon are obviously high now */ preload_fpu = tsk_used_math(next_p) && next_p->fpu_counter > 5; and /* * fpu_counter contains the number of consecutive context switches * that the FPU is used. If this is over a threshold, the lazy fpu * saving becomes unlazy to save the trap. This is an unsigned char * so that after 256 times the counter wraps and the behavior turns * lazy again; this to deal with bursty apps that only use FPU for * a short time */ - We could create a paca bit to mirror the VMX enabled MSR bit and check that first, avoiding multiple calls to calling enable_kernel_altivec. That should help with iovec based system calls like readv. - We could have two VMX breakpoints, one for when we know the user VMX state is loaded into the registers and one when it isn't. This could be a second bit in the paca so we can calculate the break points quickly. - One suggestion from Ben was to save and restore the VSX registers we use inline instead of using enable_kernel_altivec. [BenH: Fixed a problem with preempt and fixed build without CONFIG_ALTIVEC] Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08 04:11:45 +08:00
CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)
powerpc: Fixup lwsync at runtime To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up the code. We default to 'sync' since that is always safe and if the cpu is capable we will replace 'sync' with 'lwsync'. We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is needed. This flag could be moved elsewhere since we dont really use it for the normal CPU_FTR purpose. Finally we only store the relative offset in the fixup section to keep it as small as possible rather than using a full fixup_entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-07-01 23:16:40 +08:00
#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
powerpc: Free up some CPU feature bits by moving out MMU-related features Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-04-07 03:48:50 +08:00
CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
powerpc: Add new CPU feature: CPU_FTR_UNALIGNED_LD_STD Add a new CPU feature bit, CPU_FTR_UNALIGNED_LD_STD, to be added to the 64bit powerpc chips that can do unaligned load double and store double without any performance hit. This is added to Power6 and Cell and will be used in the next commit to disable the code that gets the destination address aligned on those CPUs where doing that doesn't improve performance. Signed-off-by: Mark Nelson <markn@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-10-27 08:43:02 +08:00
CPU_FTR_UNALIGNED_LD_STD)
powerpc: Fixup lwsync at runtime To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up the code. We default to 'sync' since that is always safe and if the cpu is capable we will replace 'sync' with 'lwsync'. We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is needed. This flag could be moved elsewhere since we dont really use it for the normal CPU_FTR purpose. Finally we only store the relative offset in the fixup section to keep it as small as possible rather than using a full fixup_entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-07-01 23:16:40 +08:00
#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
powerpc: Free up some CPU feature bits by moving out MMU-related features Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-04-07 03:48:50 +08:00
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_PURR | CPU_FTR_REAL_LE)
powerpc/mm: Introduce MMU features We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:32 +08:00
#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
powerpc: Add A2 cpu support Add the cputable entry, regs and setup & restore entries for the PowerPC A2 core. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-04-15 06:32:01 +08:00
#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
powerpc/book3e: Add ICSWX/ACOP support to Book3e cores like A2 ICSWX is also used by the A2 processor to access coprocessors, although not all "chips" that contain A2s have coprocessors. Signed-off-by: Jimi Xenidis <jimix@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-09-29 18:55:13 +08:00
CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
powerpc: Add A2 cpu support Add the cputable entry, regs and setup & restore entries for the PowerPC A2 core. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-04-15 06:32:01 +08:00
[PATCH] powerpc: Dont set 32bit cputable bits on 64bit Milton and I were looking at the cputable code and it looks like we can set spurious bits on 64bit. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-12-13 04:45:33 +08:00
#ifdef __powerpc64__
powerpc/book3e: Fix CPU feature handling on 64-bit e5500 The CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS defines did not encompass e5500 CPU features when built for 64-bit. This causes issues with cpu_has_feature() as it utilizes the POSSIBLE & ALWAYS defines as part of its check. Create a unique CPU_FTRS_E5500 (as its different from CPU_FTRS_E500MC), created a new group for 64-bit Book3e based CPUs and add CPU_FTRS_E5500 to that group. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-06 13:11:06 +08:00
#ifdef CONFIG_PPC_BOOK3E
powerpc: Add initial e6500 cpu support Add basic support for e6500 core in its single threaded mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-07 01:51:07 +08:00
#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
powerpc/book3e: Fix CPU feature handling on 64-bit e5500 The CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS defines did not encompass e5500 CPU features when built for 64-bit. This causes issues with cpu_has_feature() as it utilizes the POSSIBLE & ALWAYS defines as part of its check. Create a unique CPU_FTRS_E5500 (as its different from CPU_FTRS_E500MC), created a new group for 64-bit Book3e based CPUs and add CPU_FTRS_E5500 to that group. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-06 13:11:06 +08:00
#else
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
#define CPU_FTRS_POSSIBLE \
(CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
[PATCH] powerpc: Add cputable entry for POWER6 Add a cputable entry for the POWER6 processor. The SIHV and SIPR bits in the mmcra have moved in POWER6, so disable support for that until oprofile is fixed. Also tell firmware that we know about POWER6. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-04-29 07:51:06 +08:00
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
powerpc: Add cputable entry for POWER7 Add a cputable entry for the POWER7 processor. Also tell firmware that we know about POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-18 08:47:26 +08:00
CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
powerpc: Free up some CPU feature bits by moving out MMU-related features Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-04-07 03:48:50 +08:00
CPU_FTR_VSX)
powerpc/book3e: Fix CPU feature handling on 64-bit e5500 The CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS defines did not encompass e5500 CPU features when built for 64-bit. This causes issues with cpu_has_feature() as it utilizes the POSSIBLE & ALWAYS defines as part of its check. Create a unique CPU_FTRS_E5500 (as its different from CPU_FTRS_E500MC), created a new group for 64-bit Book3e based CPUs and add CPU_FTRS_E5500 to that group. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-06 13:11:06 +08:00
#endif
[PATCH] powerpc: Dont set 32bit cputable bits on 64bit Milton and I were looking at the cputable code and it looks like we can set spurious bits on 64bit. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-12-13 04:45:33 +08:00
#else
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
enum {
CPU_FTRS_POSSIBLE =
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#if CLASSIC_PPC
CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
[POWERPC] Add support for FP emulation for the e300c2 core The e300c2 has no FPU. Its MSR[FP] is grounded to zero. If an attempt is made to execute a floating point instruction (including floating-point load, store, or move instructions), the e300c2 takes a floating-point unavailable interrupt. This patch adds support for FP emulation on the e300c2 by declaring a new CPU_FTR_FP_TAKES_FPUNAVAIL, where FP unavail interrupts are intercepted and redirected to the ProgramCheck exception path for correct emulation handling. (If we run out of CPU_FTR bits we could look to reclaim this bit by adding support to test the cpu_user_features for PPC_FEATURE_HAS_FPU instead) It adds a nop to the exception path for 32-bit processors with a FPU. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2006-12-08 16:43:30 +08:00
CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
CPU_FTRS_CLASSIC32 |
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#else
CPU_FTRS_GENERIC_32 |
#endif
#ifdef CONFIG_8xx
CPU_FTRS_8XX |
#endif
#ifdef CONFIG_40x
CPU_FTRS_40X |
#endif
#ifdef CONFIG_44x
powerpc/4xx: Extended DCR support v2 This adds supports to the "extended" DCR addressing via the indirect mfdcrx/mtdcrx instructions supported by some 4xx cores (440H6 and later). I enabled the feature for now only on AMCC 460 chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:22 +08:00
CPU_FTRS_44X | CPU_FTRS_440x6 |
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#endif
powerpc/47x: Base ppc476 support This patch adds the base support for the 476 processor. The code was primarily written by Ben Herrenschmidt and Torez Smith, but I've been maintaining it for a while. The goal is to have a single binary that will run on 44x and 47x, but we still have some details to work out. The biggest is that the L1 cache line size differs on the two platforms, but it's currently a compile-time option. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2010-03-05 18:43:12 +08:00
#ifdef CONFIG_PPC_47x
powerpc/476: define specific cpu table entry DD2 core The DD2 core still has some unstability. Define CPU_FTR_476_DD2 to enable workarounds in later patches. This is based on an earlier, unreleased patch for DD1 by Ben Herrenschmidt. Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2011-01-26 14:17:58 +08:00
CPU_FTRS_47X | CPU_FTR_476_DD2 |
powerpc/47x: Base ppc476 support This patch adds the base support for the 476 processor. The code was primarily written by Ben Herrenschmidt and Torez Smith, but I've been maintaining it for a while. The goal is to have a single binary that will run on 44x and 47x, but we still have some details to work out. The biggest is that the L1 cache line size differs on the two platforms, but it's currently a compile-time option. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2010-03-05 18:43:12 +08:00
#endif
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#ifdef CONFIG_E200
CPU_FTRS_E200 |
#endif
#ifdef CONFIG_E500
powerpc/e500: split CPU_FTRS_ALWAYS/CPU_FTRS_POSSIBLE Split e500 (v1/v2) and e500mc/e5500 to allow optimization of feature checks that differ between the two. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-20 23:34:14 +08:00
CPU_FTRS_E500 | CPU_FTRS_E500_2 |
#endif
#ifdef CONFIG_PPC_E500MC
CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#endif
0,
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
};
#endif /* __powerpc64__ */
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
[PATCH] powerpc: Dont set 32bit cputable bits on 64bit Milton and I were looking at the cputable code and it looks like we can set spurious bits on 64bit. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-12-13 04:45:33 +08:00
#ifdef __powerpc64__
powerpc/book3e: Fix CPU feature handling on 64-bit e5500 The CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS defines did not encompass e5500 CPU features when built for 64-bit. This causes issues with cpu_has_feature() as it utilizes the POSSIBLE & ALWAYS defines as part of its check. Create a unique CPU_FTRS_E5500 (as its different from CPU_FTRS_E500MC), created a new group for 64-bit Book3e based CPUs and add CPU_FTRS_E5500 to that group. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-06 13:11:06 +08:00
#ifdef CONFIG_PPC_BOOK3E
powerpc: Add initial e6500 cpu support Add basic support for e6500 core in its single threaded mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-07 01:51:07 +08:00
#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
powerpc/book3e: Fix CPU feature handling on 64-bit e5500 The CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS defines did not encompass e5500 CPU features when built for 64-bit. This causes issues with cpu_has_feature() as it utilizes the POSSIBLE & ALWAYS defines as part of its check. Create a unique CPU_FTRS_E5500 (as its different from CPU_FTRS_E500MC), created a new group for 64-bit Book3e based CPUs and add CPU_FTRS_E5500 to that group. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-06 13:11:06 +08:00
#else
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
#define CPU_FTRS_ALWAYS \
(CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
[PATCH] powerpc: Add cputable entry for POWER6 Add a cputable entry for the POWER6 processor. The SIHV and SIPR bits in the mmcra have moved in POWER6, so disable support for that until oprofile is fixed. Also tell firmware that we know about POWER6. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-04-29 07:51:06 +08:00
CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
powerpc: Add cputable entry for POWER7 Add a cputable entry for the POWER7 processor. Also tell firmware that we know about POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-18 08:47:26 +08:00
CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
powerpc/book3e: Fix CPU feature handling on 64-bit e5500 The CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS defines did not encompass e5500 CPU features when built for 64-bit. This causes issues with cpu_has_feature() as it utilizes the POSSIBLE & ALWAYS defines as part of its check. Create a unique CPU_FTRS_E5500 (as its different from CPU_FTRS_E500MC), created a new group for 64-bit Book3e based CPUs and add CPU_FTRS_E5500 to that group. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-06 13:11:06 +08:00
#endif
[PATCH] powerpc: Dont set 32bit cputable bits on 64bit Milton and I were looking at the cputable code and it looks like we can set spurious bits on 64bit. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-12-13 04:45:33 +08:00
#else
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
enum {
CPU_FTRS_ALWAYS =
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#if CLASSIC_PPC
CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
[POWERPC] Add support for FP emulation for the e300c2 core The e300c2 has no FPU. Its MSR[FP] is grounded to zero. If an attempt is made to execute a floating point instruction (including floating-point load, store, or move instructions), the e300c2 takes a floating-point unavailable interrupt. This patch adds support for FP emulation on the e300c2 by declaring a new CPU_FTR_FP_TAKES_FPUNAVAIL, where FP unavail interrupts are intercepted and redirected to the ProgramCheck exception path for correct emulation handling. (If we run out of CPU_FTR bits we could look to reclaim this bit by adding support to test the cpu_user_features for PPC_FEATURE_HAS_FPU instead) It adds a nop to the exception path for 32-bit processors with a FPU. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2006-12-08 16:43:30 +08:00
CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
CPU_FTRS_CLASSIC32 &
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#else
CPU_FTRS_GENERIC_32 &
#endif
#ifdef CONFIG_8xx
CPU_FTRS_8XX &
#endif
#ifdef CONFIG_40x
CPU_FTRS_40X &
#endif
#ifdef CONFIG_44x
powerpc/4xx: Extended DCR support v2 This adds supports to the "extended" DCR addressing via the indirect mfdcrx/mtdcrx instructions supported by some 4xx cores (440H6 and later). I enabled the feature for now only on AMCC 460 chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-19 03:13:22 +08:00
CPU_FTRS_44X & CPU_FTRS_440x6 &
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#endif
#ifdef CONFIG_E200
CPU_FTRS_E200 &
#endif
#ifdef CONFIG_E500
powerpc/e500: split CPU_FTRS_ALWAYS/CPU_FTRS_POSSIBLE Split e500 (v1/v2) and e500mc/e5500 to allow optimization of feature checks that differ between the two. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-20 23:34:14 +08:00
CPU_FTRS_E500 & CPU_FTRS_E500_2 &
#endif
#ifdef CONFIG_PPC_E500MC
CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#endif
KVM: PPC: e500mc support Add processor support for e500mc, using hardware virtualization support (GS-mode). Current issues include: - No support for external proxy (coreint) interrupt mode in the guest. Includes work by Ashish Kalra <Ashish.Kalra@freescale.com>, Varun Sethi <Varun.Sethi@freescale.com>, and Liu Yu <yu.liu@freescale.com>. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-20 23:34:47 +08:00
~CPU_FTR_EMB_HV & /* can be removed at runtime */
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
CPU_FTRS_POSSIBLE,
};
[PATCH] powerpc: work around sparse warnings in cputable.h Christoph noticed that sparse warned about all the enum tags in cuptable.h that had values that required them to be type log. (enum tags are ints according to the standard.) This patch attempts to fix them in the least intrusive way possible by turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS which are hard to construct that way. This works because these last two contain no bits above 2^31. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 14:36:59 +08:00
#endif /* __powerpc64__ */
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
static inline int cpu_has_feature(unsigned long feature)
{
return (CPU_FTRS_ALWAYS & feature) ||
(CPU_FTRS_POSSIBLE
& cur_cpu_spec->cpu_features
& feature);
}
powerpc, hw_breakpoints: Implement hw_breakpoints for 64-bit server processors Implement perf-events based hw-breakpoint interfaces for PowerPC 64-bit server (Book III S) processors. This allows access to a given location to be used as an event that can be counted or profiled by the perf_events subsystem. This is done using the DABR (data breakpoint register), which can also be used for process debugging via ptrace. When perf_event hw_breakpoint support is configured in, the perf_event subsystem manages the DABR and arbitrates access to it, and ptrace then creates a perf_event when it is requested to set a data breakpoint. [Adopted suggestions from Paul Mackerras <paulus@samba.org> to - emulate_step() all system-wide breakpoints and single-step only the per-task breakpoints - perform arch-specific cleanup before unregistration through arch_unregister_hw_breakpoint() ] Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2010-06-15 14:05:19 +08:00
#ifdef CONFIG_HAVE_HW_BREAKPOINT
#define HBP_NUM 1
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
[PATCH] powerpc: merged asm/cputable.h Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-09-24 03:08:58 +08:00
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* __ASM_POWERPC_CPUTABLE_H */