2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
|
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* for more details.
|
|
|
|
*
|
|
|
|
* Copyright (C) 1994 - 2000 Ralf Baechle
|
|
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|
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
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|
|
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
|
|
|
|
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
|
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|
|
*/
|
2007-09-12 01:05:33 +08:00
|
|
|
#include <linux/bug.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <linux/init.h>
|
2016-08-22 03:58:14 +08:00
|
|
|
#include <linux/export.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <linux/signal.h>
|
|
|
|
#include <linux/sched.h>
|
2009-06-19 21:05:26 +08:00
|
|
|
#include <linux/smp.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/errno.h>
|
|
|
|
#include <linux/string.h>
|
|
|
|
#include <linux/types.h>
|
|
|
|
#include <linux/pagemap.h>
|
|
|
|
#include <linux/ptrace.h>
|
|
|
|
#include <linux/mman.h>
|
|
|
|
#include <linux/mm.h>
|
2018-10-31 06:09:49 +08:00
|
|
|
#include <linux/memblock.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <linux/highmem.h>
|
|
|
|
#include <linux/swap.h>
|
2005-01-21 08:59:54 +08:00
|
|
|
#include <linux/proc_fs.h>
|
2006-03-27 17:16:04 +08:00
|
|
|
#include <linux/pfn.h>
|
2009-09-08 02:11:31 +08:00
|
|
|
#include <linux/hardirq.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
|
|
|
#include <linux/gfp.h>
|
2013-04-12 07:10:25 +08:00
|
|
|
#include <linux/kcore.h>
|
2017-08-24 02:17:50 +08:00
|
|
|
#include <linux/initrd.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#include <asm/bootinfo.h>
|
|
|
|
#include <asm/cachectl.h>
|
|
|
|
#include <asm/cpu.h>
|
|
|
|
#include <asm/dma.h>
|
2006-10-22 06:17:35 +08:00
|
|
|
#include <asm/kmap_types.h>
|
2015-07-10 23:52:38 +08:00
|
|
|
#include <asm/maar.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <asm/mmu_context.h>
|
|
|
|
#include <asm/sections.h>
|
|
|
|
#include <asm/pgtable.h>
|
|
|
|
#include <asm/pgalloc.h>
|
|
|
|
#include <asm/tlb.h>
|
2006-10-22 06:17:35 +08:00
|
|
|
#include <asm/fixmap.h>
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
* We have up to 8 empty zeroed pages so we can map one of the right colour
|
2013-01-22 19:59:30 +08:00
|
|
|
* when needed. This is necessary only on R4000 / R4400 SC and MC versions
|
2005-04-17 06:20:36 +08:00
|
|
|
* where we have to avoid VCED / VECI exceptions for good performance at
|
|
|
|
* any price. Since page is never written to after the initialization we
|
|
|
|
* don't have to care about aliases on other CPUs.
|
|
|
|
*/
|
|
|
|
unsigned long empty_zero_page, zero_page_mask;
|
2008-06-06 21:23:06 +08:00
|
|
|
EXPORT_SYMBOL_GPL(empty_zero_page);
|
2014-09-13 04:17:23 +08:00
|
|
|
EXPORT_SYMBOL(zero_page_mask);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Not static inline because used by IP27 special magic initialization code
|
|
|
|
*/
|
2013-04-30 06:06:43 +08:00
|
|
|
void setup_zero_pages(void)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2013-04-30 06:06:43 +08:00
|
|
|
unsigned int order, i;
|
2005-04-17 06:20:36 +08:00
|
|
|
struct page *page;
|
|
|
|
|
|
|
|
if (cpu_has_vce)
|
|
|
|
order = 3;
|
|
|
|
else
|
|
|
|
order = 0;
|
|
|
|
|
|
|
|
empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
|
|
|
|
if (!empty_zero_page)
|
|
|
|
panic("Oh boy, that early out of memory?");
|
|
|
|
|
2006-10-19 19:19:59 +08:00
|
|
|
page = virt_to_page((void *)empty_zero_page);
|
2006-03-22 16:08:05 +08:00
|
|
|
split_page(page, order);
|
2013-04-30 06:06:43 +08:00
|
|
|
for (i = 0; i < (1 << order); i++, page++)
|
|
|
|
mark_page_reserved(page);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2013-04-30 06:06:43 +08:00
|
|
|
zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2014-03-03 20:08:40 +08:00
|
|
|
static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
|
2006-10-22 06:17:35 +08:00
|
|
|
{
|
|
|
|
enum fixed_addresses idx;
|
MIPS: MemoryMapID (MMID) Support
Introduce support for using MemoryMapIDs (MMIDs) as an alternative to
Address Space IDs (ASIDs). The major difference between the two is that
MMIDs are global - ie. an MMID uniquely identifies an address space
across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs,
wherein each address space is allocated a separate ASID for each CPU
upon which it is used. This global namespace allows a new GINVT
instruction be used to globally invalidate TLB entries associated with a
particular MMID across all coherent CPUs in the system, removing the
need for IPIs to invalidate entries with separate ASIDs on each CPU.
The allocation scheme used here is largely borrowed from arm64 (see
arch/arm64/mm/context.c). In essence we maintain a bitmap to track
available MMIDs, and MMIDs in active use at the time of a rollover to a
new MMID version are preserved in the new version. The allocation scheme
requires efficient 64 bit atomics in order to perform reasonably, so
this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it
will only be included in MIPS64 kernels).
The first, and currently only, available CPU with support for MMIDs is
the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap
our MMIDs to 16 bits wide in order to prevent the bitmap growing to
absurd sizes if any future CPU does implement 32 bit MMIDs as the
architecture manuals suggest is recommended.
When MMIDs are in use we also make use of GINVT instruction which is
available due to the global nature of MMIDs. By executing a sequence of
GINVT & SYNC 0x14 instructions we can avoid the overhead of an IPI to
each remote CPU in many cases. One complication is that GINVT will
invalidate wired entries (in all cases apart from type 0, which targets
the entire TLB). In order to avoid GINVT invalidating any wired TLB
entries we set up, we make sure to create those entries using a reserved
MMID (0) that we never associate with any address space.
Also of note is that KVM will require further work in order to support
MMIDs & GINVT, since KVM is involved in allocating IDs for guests & in
configuring the MMU. That work is not part of this patch, so for now
when MMIDs are in use KVM is disabled.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-02 09:43:28 +08:00
|
|
|
unsigned int uninitialized_var(old_mmid);
|
2006-10-22 06:17:35 +08:00
|
|
|
unsigned long vaddr, flags, entrylo;
|
|
|
|
unsigned long old_ctx;
|
|
|
|
pte_t pte;
|
|
|
|
int tlbidx;
|
|
|
|
|
2007-09-12 01:05:33 +08:00
|
|
|
BUG_ON(Page_dcache_dirty(page));
|
|
|
|
|
2015-05-11 23:52:10 +08:00
|
|
|
preempt_disable();
|
2013-09-10 18:15:23 +08:00
|
|
|
pagefault_disable();
|
2006-10-22 06:17:35 +08:00
|
|
|
idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
|
2009-09-08 02:11:31 +08:00
|
|
|
idx += in_interrupt() ? FIX_N_COLOURS : 0;
|
2006-10-22 06:17:35 +08:00
|
|
|
vaddr = __fix_to_virt(FIX_CMAP_END - idx);
|
2014-03-03 20:08:40 +08:00
|
|
|
pte = mk_pte(page, prot);
|
2016-04-19 16:25:05 +08:00
|
|
|
#if defined(CONFIG_XPA)
|
2015-02-27 08:16:38 +08:00
|
|
|
entrylo = pte_to_entrylo(pte.pte_high);
|
2016-04-19 16:25:05 +08:00
|
|
|
#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
|
|
|
|
entrylo = pte.pte_high;
|
2006-10-22 06:17:35 +08:00
|
|
|
#else
|
2010-02-11 07:12:47 +08:00
|
|
|
entrylo = pte_to_entrylo(pte_val(pte));
|
2006-10-22 06:17:35 +08:00
|
|
|
#endif
|
|
|
|
|
2014-05-23 22:29:44 +08:00
|
|
|
local_irq_save(flags);
|
2006-10-22 06:17:35 +08:00
|
|
|
old_ctx = read_c0_entryhi();
|
|
|
|
write_c0_entryhi(vaddr & (PAGE_MASK << 1));
|
|
|
|
write_c0_entrylo0(entrylo);
|
|
|
|
write_c0_entrylo1(entrylo);
|
MIPS: MemoryMapID (MMID) Support
Introduce support for using MemoryMapIDs (MMIDs) as an alternative to
Address Space IDs (ASIDs). The major difference between the two is that
MMIDs are global - ie. an MMID uniquely identifies an address space
across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs,
wherein each address space is allocated a separate ASID for each CPU
upon which it is used. This global namespace allows a new GINVT
instruction be used to globally invalidate TLB entries associated with a
particular MMID across all coherent CPUs in the system, removing the
need for IPIs to invalidate entries with separate ASIDs on each CPU.
The allocation scheme used here is largely borrowed from arm64 (see
arch/arm64/mm/context.c). In essence we maintain a bitmap to track
available MMIDs, and MMIDs in active use at the time of a rollover to a
new MMID version are preserved in the new version. The allocation scheme
requires efficient 64 bit atomics in order to perform reasonably, so
this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it
will only be included in MIPS64 kernels).
The first, and currently only, available CPU with support for MMIDs is
the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap
our MMIDs to 16 bits wide in order to prevent the bitmap growing to
absurd sizes if any future CPU does implement 32 bit MMIDs as the
architecture manuals suggest is recommended.
When MMIDs are in use we also make use of GINVT instruction which is
available due to the global nature of MMIDs. By executing a sequence of
GINVT & SYNC 0x14 instructions we can avoid the overhead of an IPI to
each remote CPU in many cases. One complication is that GINVT will
invalidate wired entries (in all cases apart from type 0, which targets
the entire TLB). In order to avoid GINVT invalidating any wired TLB
entries we set up, we make sure to create those entries using a reserved
MMID (0) that we never associate with any address space.
Also of note is that KVM will require further work in order to support
MMIDs & GINVT, since KVM is involved in allocating IDs for guests & in
configuring the MMU. That work is not part of this patch, so for now
when MMIDs are in use KVM is disabled.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-02 09:43:28 +08:00
|
|
|
if (cpu_has_mmid) {
|
|
|
|
old_mmid = read_c0_memorymapid();
|
|
|
|
write_c0_memorymapid(MMID_KERNEL_WIRED);
|
|
|
|
}
|
2015-02-27 08:16:38 +08:00
|
|
|
#ifdef CONFIG_XPA
|
2016-04-19 16:25:10 +08:00
|
|
|
if (cpu_has_xpa) {
|
|
|
|
entrylo = (pte.pte_low & _PFNX_MASK);
|
|
|
|
writex_c0_entrylo0(entrylo);
|
|
|
|
writex_c0_entrylo1(entrylo);
|
|
|
|
}
|
2015-02-27 08:16:38 +08:00
|
|
|
#endif
|
2016-11-12 09:26:07 +08:00
|
|
|
tlbidx = num_wired_entries();
|
2006-10-22 06:17:35 +08:00
|
|
|
write_c0_wired(tlbidx + 1);
|
|
|
|
write_c0_index(tlbidx);
|
|
|
|
mtc0_tlbw_hazard();
|
|
|
|
tlb_write_indexed();
|
|
|
|
tlbw_use_hazard();
|
|
|
|
write_c0_entryhi(old_ctx);
|
MIPS: MemoryMapID (MMID) Support
Introduce support for using MemoryMapIDs (MMIDs) as an alternative to
Address Space IDs (ASIDs). The major difference between the two is that
MMIDs are global - ie. an MMID uniquely identifies an address space
across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs,
wherein each address space is allocated a separate ASID for each CPU
upon which it is used. This global namespace allows a new GINVT
instruction be used to globally invalidate TLB entries associated with a
particular MMID across all coherent CPUs in the system, removing the
need for IPIs to invalidate entries with separate ASIDs on each CPU.
The allocation scheme used here is largely borrowed from arm64 (see
arch/arm64/mm/context.c). In essence we maintain a bitmap to track
available MMIDs, and MMIDs in active use at the time of a rollover to a
new MMID version are preserved in the new version. The allocation scheme
requires efficient 64 bit atomics in order to perform reasonably, so
this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it
will only be included in MIPS64 kernels).
The first, and currently only, available CPU with support for MMIDs is
the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap
our MMIDs to 16 bits wide in order to prevent the bitmap growing to
absurd sizes if any future CPU does implement 32 bit MMIDs as the
architecture manuals suggest is recommended.
When MMIDs are in use we also make use of GINVT instruction which is
available due to the global nature of MMIDs. By executing a sequence of
GINVT & SYNC 0x14 instructions we can avoid the overhead of an IPI to
each remote CPU in many cases. One complication is that GINVT will
invalidate wired entries (in all cases apart from type 0, which targets
the entire TLB). In order to avoid GINVT invalidating any wired TLB
entries we set up, we make sure to create those entries using a reserved
MMID (0) that we never associate with any address space.
Also of note is that KVM will require further work in order to support
MMIDs & GINVT, since KVM is involved in allocating IDs for guests & in
configuring the MMU. That work is not part of this patch, so for now
when MMIDs are in use KVM is disabled.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-02 09:43:28 +08:00
|
|
|
if (cpu_has_mmid)
|
|
|
|
write_c0_memorymapid(old_mmid);
|
2014-05-23 22:29:44 +08:00
|
|
|
local_irq_restore(flags);
|
2006-10-22 06:17:35 +08:00
|
|
|
|
|
|
|
return (void*) vaddr;
|
|
|
|
}
|
|
|
|
|
2014-03-03 20:08:40 +08:00
|
|
|
void *kmap_coherent(struct page *page, unsigned long addr)
|
|
|
|
{
|
|
|
|
return __kmap_pgprot(page, addr, PAGE_KERNEL);
|
|
|
|
}
|
|
|
|
|
|
|
|
void *kmap_noncoherent(struct page *page, unsigned long addr)
|
|
|
|
{
|
|
|
|
return __kmap_pgprot(page, addr, PAGE_KERNEL_NC);
|
|
|
|
}
|
|
|
|
|
2007-04-26 22:46:25 +08:00
|
|
|
void kunmap_coherent(void)
|
2006-10-22 06:17:35 +08:00
|
|
|
{
|
|
|
|
unsigned int wired;
|
|
|
|
unsigned long flags, old_ctx;
|
|
|
|
|
2014-05-23 22:29:44 +08:00
|
|
|
local_irq_save(flags);
|
2006-10-22 06:17:35 +08:00
|
|
|
old_ctx = read_c0_entryhi();
|
2016-11-12 09:26:07 +08:00
|
|
|
wired = num_wired_entries() - 1;
|
2006-10-22 06:17:35 +08:00
|
|
|
write_c0_wired(wired);
|
|
|
|
write_c0_index(wired);
|
|
|
|
write_c0_entryhi(UNIQUE_ENTRYHI(wired));
|
|
|
|
write_c0_entrylo0(0);
|
|
|
|
write_c0_entrylo1(0);
|
|
|
|
mtc0_tlbw_hazard();
|
|
|
|
tlb_write_indexed();
|
|
|
|
tlbw_use_hazard();
|
|
|
|
write_c0_entryhi(old_ctx);
|
2014-05-23 22:29:44 +08:00
|
|
|
local_irq_restore(flags);
|
2013-09-10 18:15:23 +08:00
|
|
|
pagefault_enable();
|
2015-05-11 23:52:10 +08:00
|
|
|
preempt_enable();
|
2006-10-22 06:17:35 +08:00
|
|
|
}
|
|
|
|
|
2006-12-13 01:14:56 +08:00
|
|
|
void copy_user_highpage(struct page *to, struct page *from,
|
|
|
|
unsigned long vaddr, struct vm_area_struct *vma)
|
|
|
|
{
|
|
|
|
void *vfrom, *vto;
|
|
|
|
|
2011-11-25 23:14:15 +08:00
|
|
|
vto = kmap_atomic(to);
|
2008-02-17 06:34:25 +08:00
|
|
|
if (cpu_has_dc_aliases &&
|
2016-01-16 08:53:46 +08:00
|
|
|
page_mapcount(from) && !Page_dcache_dirty(from)) {
|
2006-12-13 01:14:56 +08:00
|
|
|
vfrom = kmap_coherent(from, vaddr);
|
|
|
|
copy_page(vto, vfrom);
|
2007-04-26 22:46:25 +08:00
|
|
|
kunmap_coherent();
|
2006-12-13 01:14:56 +08:00
|
|
|
} else {
|
2011-11-25 23:14:15 +08:00
|
|
|
vfrom = kmap_atomic(from);
|
2006-12-13 01:14:56 +08:00
|
|
|
copy_page(vto, vfrom);
|
2011-11-25 23:14:15 +08:00
|
|
|
kunmap_atomic(vfrom);
|
2006-12-13 01:14:56 +08:00
|
|
|
}
|
2008-04-29 00:14:26 +08:00
|
|
|
if ((!cpu_has_ic_fills_f_dc) ||
|
2006-12-13 01:14:56 +08:00
|
|
|
pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
|
|
|
|
flush_data_cache_page((unsigned long)vto);
|
2011-11-25 23:14:15 +08:00
|
|
|
kunmap_atomic(vto);
|
2006-12-13 01:14:56 +08:00
|
|
|
/* Make sure this page is cleared on other CPU's too before using it */
|
|
|
|
smp_wmb();
|
|
|
|
}
|
|
|
|
|
2006-10-22 06:17:35 +08:00
|
|
|
void copy_to_user_page(struct vm_area_struct *vma,
|
|
|
|
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
|
|
|
unsigned long len)
|
|
|
|
{
|
2008-02-17 06:34:25 +08:00
|
|
|
if (cpu_has_dc_aliases &&
|
2016-01-16 08:53:46 +08:00
|
|
|
page_mapcount(page) && !Page_dcache_dirty(page)) {
|
2006-10-22 06:17:35 +08:00
|
|
|
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
|
|
|
memcpy(vto, src, len);
|
2007-04-26 22:46:25 +08:00
|
|
|
kunmap_coherent();
|
2007-10-15 23:30:24 +08:00
|
|
|
} else {
|
2006-10-22 06:17:35 +08:00
|
|
|
memcpy(dst, src, len);
|
2007-10-15 23:30:24 +08:00
|
|
|
if (cpu_has_dc_aliases)
|
|
|
|
SetPageDcacheDirty(page);
|
|
|
|
}
|
2016-01-22 18:58:25 +08:00
|
|
|
if (vma->vm_flags & VM_EXEC)
|
2006-10-22 06:17:35 +08:00
|
|
|
flush_cache_page(vma, vaddr, page_to_pfn(page));
|
|
|
|
}
|
|
|
|
|
|
|
|
void copy_from_user_page(struct vm_area_struct *vma,
|
|
|
|
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
|
|
|
unsigned long len)
|
|
|
|
{
|
2008-02-17 06:34:25 +08:00
|
|
|
if (cpu_has_dc_aliases &&
|
2016-01-16 08:53:46 +08:00
|
|
|
page_mapcount(page) && !Page_dcache_dirty(page)) {
|
2007-10-15 23:30:24 +08:00
|
|
|
void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
2006-10-22 06:17:35 +08:00
|
|
|
memcpy(dst, vfrom, len);
|
2007-04-26 22:46:25 +08:00
|
|
|
kunmap_coherent();
|
2007-10-15 23:30:24 +08:00
|
|
|
} else {
|
2006-10-22 06:17:35 +08:00
|
|
|
memcpy(dst, src, len);
|
2007-10-15 23:30:24 +08:00
|
|
|
if (cpu_has_dc_aliases)
|
|
|
|
SetPageDcacheDirty(page);
|
|
|
|
}
|
2006-10-22 06:17:35 +08:00
|
|
|
}
|
2013-09-05 17:22:45 +08:00
|
|
|
EXPORT_SYMBOL_GPL(copy_from_user_page);
|
2006-10-22 06:17:35 +08:00
|
|
|
|
2005-02-08 00:13:07 +08:00
|
|
|
void __init fixrange_init(unsigned long start, unsigned long end,
|
2005-04-17 06:20:36 +08:00
|
|
|
pgd_t *pgd_base)
|
|
|
|
{
|
2014-05-23 22:29:44 +08:00
|
|
|
#ifdef CONFIG_HIGHMEM
|
2005-04-17 06:20:36 +08:00
|
|
|
pgd_t *pgd;
|
2005-02-10 20:19:59 +08:00
|
|
|
pud_t *pud;
|
2005-04-17 06:20:36 +08:00
|
|
|
pmd_t *pmd;
|
|
|
|
pte_t *pte;
|
2005-02-10 20:19:59 +08:00
|
|
|
int i, j, k;
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned long vaddr;
|
|
|
|
|
|
|
|
vaddr = start;
|
2019-11-22 00:21:32 +08:00
|
|
|
i = pgd_index(vaddr);
|
|
|
|
j = pud_index(vaddr);
|
|
|
|
k = pmd_index(vaddr);
|
2005-04-17 06:20:36 +08:00
|
|
|
pgd = pgd_base + i;
|
|
|
|
|
2011-01-06 15:31:30 +08:00
|
|
|
for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
|
2005-02-10 20:19:59 +08:00
|
|
|
pud = (pud_t *)pgd;
|
2011-01-06 15:31:30 +08:00
|
|
|
for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
|
2005-02-10 20:19:59 +08:00
|
|
|
pmd = (pmd_t *)pud;
|
2011-01-06 15:31:30 +08:00
|
|
|
for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
|
2005-02-10 20:19:59 +08:00
|
|
|
if (pmd_none(*pmd)) {
|
2018-10-31 06:08:54 +08:00
|
|
|
pte = (pte_t *) memblock_alloc_low(PAGE_SIZE,
|
|
|
|
PAGE_SIZE);
|
2019-03-12 14:30:31 +08:00
|
|
|
if (!pte)
|
|
|
|
panic("%s: Failed to allocate %lu bytes align=%lx\n",
|
|
|
|
__func__, PAGE_SIZE,
|
|
|
|
PAGE_SIZE);
|
|
|
|
|
2006-10-22 06:17:35 +08:00
|
|
|
set_pmd(pmd, __pmd((unsigned long)pte));
|
2009-03-30 20:49:44 +08:00
|
|
|
BUG_ON(pte != pte_offset_kernel(pmd, 0));
|
2005-02-10 20:19:59 +08:00
|
|
|
}
|
|
|
|
vaddr += PMD_SIZE;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2005-02-10 20:19:59 +08:00
|
|
|
k = 0;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
j = 0;
|
|
|
|
}
|
2006-10-22 06:17:35 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2019-08-19 22:23:12 +08:00
|
|
|
struct maar_walk_info {
|
|
|
|
struct maar_config cfg[16];
|
|
|
|
unsigned int num_cfg;
|
|
|
|
};
|
|
|
|
|
|
|
|
static int maar_res_walk(unsigned long start_pfn, unsigned long nr_pages,
|
|
|
|
void *data)
|
2015-09-25 23:59:36 +08:00
|
|
|
{
|
2019-08-19 22:23:12 +08:00
|
|
|
struct maar_walk_info *wi = data;
|
|
|
|
struct maar_config *cfg = &wi->cfg[wi->num_cfg];
|
|
|
|
unsigned int maar_align;
|
2015-09-25 23:59:36 +08:00
|
|
|
|
2019-08-19 22:23:12 +08:00
|
|
|
/* MAAR registers hold physical addresses right shifted by 4 bits */
|
|
|
|
maar_align = BIT(MIPS_MAAR_ADDR_SHIFT + 4);
|
2015-09-25 23:59:36 +08:00
|
|
|
|
2019-08-19 22:23:12 +08:00
|
|
|
/* Fill in the MAAR config entry */
|
|
|
|
cfg->lower = ALIGN(PFN_PHYS(start_pfn), maar_align);
|
|
|
|
cfg->upper = ALIGN_DOWN(PFN_PHYS(start_pfn + nr_pages), maar_align) - 1;
|
|
|
|
cfg->attrs = MIPS_MAAR_S;
|
2015-09-25 23:59:36 +08:00
|
|
|
|
2019-08-19 22:23:12 +08:00
|
|
|
/* Ensure we don't overflow the cfg array */
|
|
|
|
if (!WARN_ON(wi->num_cfg >= ARRAY_SIZE(wi->cfg)))
|
|
|
|
wi->num_cfg++;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
unsigned __weak platform_maar_init(unsigned num_pairs)
|
|
|
|
{
|
|
|
|
unsigned int num_configured;
|
|
|
|
struct maar_walk_info wi;
|
|
|
|
|
|
|
|
wi.num_cfg = 0;
|
|
|
|
walk_system_ram_range(0, max_pfn, &wi, maar_res_walk);
|
2015-09-25 23:59:36 +08:00
|
|
|
|
2019-08-19 22:23:12 +08:00
|
|
|
num_configured = maar_config(wi.cfg, wi.num_cfg, num_pairs);
|
|
|
|
if (num_configured < wi.num_cfg)
|
|
|
|
pr_warn("Not enough MAAR pairs (%u) for all memory regions (%u)\n",
|
|
|
|
num_pairs, wi.num_cfg);
|
2015-09-25 23:59:36 +08:00
|
|
|
|
|
|
|
return num_configured;
|
|
|
|
}
|
|
|
|
|
2015-09-25 23:59:38 +08:00
|
|
|
void maar_init(void)
|
2015-09-25 23:59:36 +08:00
|
|
|
{
|
|
|
|
unsigned num_maars, used, i;
|
2015-09-25 23:59:37 +08:00
|
|
|
phys_addr_t lower, upper, attr;
|
2015-09-25 23:59:38 +08:00
|
|
|
static struct {
|
|
|
|
struct maar_config cfgs[3];
|
|
|
|
unsigned used;
|
|
|
|
} recorded = { { { 0 } }, 0 };
|
2015-09-25 23:59:36 +08:00
|
|
|
|
|
|
|
if (!cpu_has_maar)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Detect the number of MAARs */
|
|
|
|
write_c0_maari(~0);
|
|
|
|
back_to_back_c0_hazard();
|
|
|
|
num_maars = read_c0_maari() + 1;
|
|
|
|
|
|
|
|
/* MAARs should be in pairs */
|
|
|
|
WARN_ON(num_maars % 2);
|
|
|
|
|
2015-09-25 23:59:38 +08:00
|
|
|
/* Set MAARs using values we recorded already */
|
|
|
|
if (recorded.used) {
|
|
|
|
used = maar_config(recorded.cfgs, recorded.used, num_maars / 2);
|
|
|
|
BUG_ON(used != recorded.used);
|
|
|
|
} else {
|
|
|
|
/* Configure the required MAARs */
|
|
|
|
used = platform_maar_init(num_maars / 2);
|
|
|
|
}
|
2015-09-25 23:59:36 +08:00
|
|
|
|
|
|
|
/* Disable any further MAARs */
|
|
|
|
for (i = (used * 2); i < num_maars; i++) {
|
|
|
|
write_c0_maari(i);
|
|
|
|
back_to_back_c0_hazard();
|
|
|
|
write_c0_maar(0);
|
|
|
|
back_to_back_c0_hazard();
|
|
|
|
}
|
2015-09-25 23:59:37 +08:00
|
|
|
|
2015-09-25 23:59:38 +08:00
|
|
|
if (recorded.used)
|
|
|
|
return;
|
|
|
|
|
2015-09-25 23:59:37 +08:00
|
|
|
pr_info("MAAR configuration:\n");
|
|
|
|
for (i = 0; i < num_maars; i += 2) {
|
|
|
|
write_c0_maari(i);
|
|
|
|
back_to_back_c0_hazard();
|
|
|
|
upper = read_c0_maar();
|
|
|
|
|
|
|
|
write_c0_maari(i + 1);
|
|
|
|
back_to_back_c0_hazard();
|
|
|
|
lower = read_c0_maar();
|
|
|
|
|
|
|
|
attr = lower & upper;
|
|
|
|
lower = (lower & MIPS_MAAR_ADDR) << 4;
|
|
|
|
upper = ((upper & MIPS_MAAR_ADDR) << 4) | 0xffff;
|
|
|
|
|
|
|
|
pr_info(" [%d]: ", i / 2);
|
2017-03-14 18:15:09 +08:00
|
|
|
if (!(attr & MIPS_MAAR_VL)) {
|
2015-09-25 23:59:37 +08:00
|
|
|
pr_cont("disabled\n");
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
pr_cont("%pa-%pa", &lower, &upper);
|
|
|
|
|
|
|
|
if (attr & MIPS_MAAR_S)
|
|
|
|
pr_cont(" speculate");
|
|
|
|
|
|
|
|
pr_cont("\n");
|
2015-09-25 23:59:38 +08:00
|
|
|
|
|
|
|
/* Record the setup for use on secondary CPUs */
|
|
|
|
if (used <= ARRAY_SIZE(recorded.cfgs)) {
|
|
|
|
recorded.cfgs[recorded.used].lower = lower;
|
|
|
|
recorded.cfgs[recorded.used].upper = upper;
|
|
|
|
recorded.cfgs[recorded.used].attrs = attr;
|
|
|
|
recorded.used++;
|
|
|
|
}
|
2015-09-25 23:59:37 +08:00
|
|
|
}
|
2015-09-25 23:59:36 +08:00
|
|
|
}
|
|
|
|
|
2005-06-26 05:54:31 +08:00
|
|
|
#ifndef CONFIG_NEED_MULTIPLE_NODES
|
2005-04-17 06:20:36 +08:00
|
|
|
void __init paging_init(void)
|
|
|
|
{
|
2007-11-03 10:05:43 +08:00
|
|
|
unsigned long max_zone_pfns[MAX_NR_ZONES];
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
pagetable_init();
|
|
|
|
|
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
|
|
kmap_init();
|
|
|
|
#endif
|
2007-03-20 23:36:02 +08:00
|
|
|
#ifdef CONFIG_ZONE_DMA
|
2007-11-03 10:05:43 +08:00
|
|
|
max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif
|
2007-11-03 10:05:43 +08:00
|
|
|
#ifdef CONFIG_ZONE_DMA32
|
|
|
|
max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
|
|
|
|
#endif
|
|
|
|
max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
|
2005-04-17 06:20:36 +08:00
|
|
|
#ifdef CONFIG_HIGHMEM
|
2007-11-03 10:05:43 +08:00
|
|
|
max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
|
2006-12-06 23:48:28 +08:00
|
|
|
|
2007-11-03 10:05:43 +08:00
|
|
|
if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
|
2006-12-06 23:48:28 +08:00
|
|
|
printk(KERN_WARNING "This processor doesn't support highmem."
|
2007-11-03 10:05:43 +08:00
|
|
|
" %ldk highmem ignored\n",
|
|
|
|
(highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
|
|
|
|
max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
|
2006-12-06 23:48:28 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif
|
|
|
|
|
2007-11-03 10:05:43 +08:00
|
|
|
free_area_init_nodes(max_zone_pfns);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2005-01-21 08:59:54 +08:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
static struct kcore_list kcore_kseg0;
|
|
|
|
#endif
|
|
|
|
|
2019-08-19 22:23:12 +08:00
|
|
|
static inline void __init mem_init_free_highmem(void)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2013-07-04 06:04:04 +08:00
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
|
|
unsigned long tmp;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2016-09-02 22:17:31 +08:00
|
|
|
if (cpu_has_dc_aliases)
|
|
|
|
return;
|
|
|
|
|
2013-07-04 06:04:04 +08:00
|
|
|
for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
|
2019-08-24 00:48:58 +08:00
|
|
|
struct page *page = pfn_to_page(tmp);
|
|
|
|
|
2019-08-19 22:23:12 +08:00
|
|
|
if (!memblock_is_memory(PFN_PHYS(tmp)))
|
2013-07-04 06:04:04 +08:00
|
|
|
SetPageReserved(page);
|
|
|
|
else
|
|
|
|
free_highmem_page(page);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init mem_init(void)
|
|
|
|
{
|
2019-09-19 06:03:30 +08:00
|
|
|
/*
|
|
|
|
* When _PFN_SHIFT is greater than PAGE_SHIFT we won't have enough PTE
|
|
|
|
* bits to hold a full 32b physical address on MIPS32 systems.
|
|
|
|
*/
|
|
|
|
BUILD_BUG_ON(IS_ENABLED(CONFIG_32BIT) && (_PFN_SHIFT > PAGE_SHIFT));
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
|
|
#ifdef CONFIG_DISCONTIGMEM
|
|
|
|
#error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
|
|
|
|
#endif
|
2010-05-30 15:32:51 +08:00
|
|
|
max_mapnr = highend_pfn ? highend_pfn : max_low_pfn;
|
2005-04-17 06:20:36 +08:00
|
|
|
#else
|
[MIPS] Do not count pages in holes with sparsemem
With some memory model other than FLATMEM, the single node can
contains some holes so there might be many invalid pages. For
example, with two 256M memory and one 256M hole, some variables
(num_physpage, totalpages, nr_kernel_pages, nr_all_pages, etc.) will
indicate that there are 768MB on this system. This is not desired
because, for example, alloc_large_system_hash() allocates too many
entries.
Use free_area_init_node() with counted zholes_size[] instead of
free_area_init().
For num_physpages, use number of ram pages instead of max_low_pfn.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-06 23:26:02 +08:00
|
|
|
max_mapnr = max_low_pfn;
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif
|
|
|
|
high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
|
|
|
|
|
2014-07-14 17:32:15 +08:00
|
|
|
maar_init();
|
2018-10-31 06:09:30 +08:00
|
|
|
memblock_free_all();
|
2013-04-30 06:06:43 +08:00
|
|
|
setup_zero_pages(); /* Setup zeroed pages. */
|
2013-07-04 06:04:04 +08:00
|
|
|
mem_init_free_highmem();
|
|
|
|
mem_init_print_info(NULL);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-01-21 08:59:54 +08:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
if ((unsigned long) &_text > (unsigned long) CKSEG0)
|
|
|
|
/* The -4 is a hack so that user tools don't have to handle
|
|
|
|
the overflow. */
|
2009-09-23 07:45:43 +08:00
|
|
|
kclist_add(&kcore_kseg0, (void *) CKSEG0,
|
|
|
|
0x80000000 - 4, KCORE_TEXT);
|
2005-01-21 08:59:54 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2005-06-26 05:54:31 +08:00
|
|
|
#endif /* !CONFIG_NEED_MULTIPLE_NODES */
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-12-29 23:43:59 +08:00
|
|
|
void free_init_pages(const char *what, unsigned long begin, unsigned long end)
|
2006-03-24 21:21:50 +08:00
|
|
|
{
|
2006-10-19 19:20:05 +08:00
|
|
|
unsigned long pfn;
|
2006-03-24 21:21:50 +08:00
|
|
|
|
2006-10-19 19:20:05 +08:00
|
|
|
for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
|
|
|
|
struct page *page = pfn_to_page(pfn);
|
|
|
|
void *addr = phys_to_virt(PFN_PHYS(pfn));
|
|
|
|
|
|
|
|
memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
|
2013-04-30 06:06:43 +08:00
|
|
|
free_reserved_page(page);
|
2006-03-24 21:21:50 +08:00
|
|
|
}
|
|
|
|
printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
|
|
|
|
}
|
|
|
|
|
2014-01-15 22:06:03 +08:00
|
|
|
void (*free_init_pages_eva)(void *begin, void *end) = NULL;
|
|
|
|
|
2016-08-03 05:03:33 +08:00
|
|
|
void __ref free_initmem(void)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2006-12-29 23:43:59 +08:00
|
|
|
prom_free_prom_memory();
|
2014-01-15 22:06:03 +08:00
|
|
|
/*
|
|
|
|
* Let the platform define a specific function to free the
|
|
|
|
* init section since EVA may have used any possible mapping
|
|
|
|
* between virtual and physical addresses.
|
|
|
|
*/
|
|
|
|
if (free_init_pages_eva)
|
|
|
|
free_init_pages_eva((void *)&__init_begin, (void *)&__init_end);
|
|
|
|
else
|
|
|
|
free_initmem_default(POISON_FREE_INITMEM);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2007-01-24 00:21:05 +08:00
|
|
|
|
2009-10-15 03:16:56 +08:00
|
|
|
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
|
2007-01-24 00:21:05 +08:00
|
|
|
unsigned long pgd_current[NR_CPUS];
|
2009-10-15 03:16:56 +08:00
|
|
|
#endif
|
2007-08-13 19:44:41 +08:00
|
|
|
|
|
|
|
/*
|
2012-08-15 02:08:01 +08:00
|
|
|
* Align swapper_pg_dir in to 64K, allows its address to be loaded
|
|
|
|
* with a single LUI instruction in the TLB handlers. If we used
|
|
|
|
* __aligned(64K), its size would get rounded up to the alignment
|
|
|
|
* size, and waste space. So we place it in its own section and align
|
|
|
|
* it in the linker script.
|
2007-08-13 19:44:41 +08:00
|
|
|
*/
|
2018-09-28 17:32:02 +08:00
|
|
|
pgd_t swapper_pg_dir[PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
|
2017-02-17 09:27:34 +08:00
|
|
|
#ifndef __PAGETABLE_PUD_FOLDED
|
|
|
|
pud_t invalid_pud_table[PTRS_PER_PUD] __page_aligned_bss;
|
|
|
|
#endif
|
2009-12-05 05:52:36 +08:00
|
|
|
#ifndef __PAGETABLE_PMD_FOLDED
|
2012-08-15 02:08:01 +08:00
|
|
|
pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
|
2015-10-16 23:33:13 +08:00
|
|
|
EXPORT_SYMBOL_GPL(invalid_pmd_table);
|
2007-01-24 00:21:05 +08:00
|
|
|
#endif
|
2012-08-15 02:08:01 +08:00
|
|
|
pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;
|
2016-11-07 19:14:12 +08:00
|
|
|
EXPORT_SYMBOL(invalid_pte_table);
|