2005-04-17 06:20:36 +08:00
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/*
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*
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* device driver for Conexant 2388x based TV cards
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* driver core
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*
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* (c) 2003 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
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*
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2007-01-21 00:58:17 +08:00
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* (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
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* - Multituner support
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* - video_ioctl2 conversion
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* - PAL/M fixes
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*
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2005-04-17 06:20:36 +08:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/kmod.h>
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#include <linux/sound.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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2005-11-09 13:37:17 +08:00
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#include <linux/videodev2.h>
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2006-01-15 17:52:23 +08:00
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#include <linux/mutex.h>
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2005-04-17 06:20:36 +08:00
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#include "cx88.h"
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2006-01-10 01:32:31 +08:00
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#include <media/v4l2-common.h>
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2008-07-20 19:12:02 +08:00
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#include <media/v4l2-ioctl.h>
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2005-04-17 06:20:36 +08:00
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MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
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MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
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MODULE_LICENSE("GPL");
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/* ------------------------------------------------------------------ */
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2013-04-28 18:15:41 +08:00
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unsigned int cx88_core_debug;
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module_param_named(core_debug, cx88_core_debug, int, 0644);
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MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
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2005-04-17 06:20:36 +08:00
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2008-04-23 01:41:48 +08:00
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static unsigned int nicam;
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2005-04-17 06:20:36 +08:00
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module_param(nicam,int,0644);
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MODULE_PARM_DESC(nicam,"tv audio is nicam");
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2008-04-23 01:41:48 +08:00
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static unsigned int nocomb;
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2005-04-17 06:20:36 +08:00
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module_param(nocomb,int,0644);
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MODULE_PARM_DESC(nocomb,"disable comb filter");
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2013-04-28 18:15:41 +08:00
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#define dprintk(level,fmt, arg...) do { \
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if (cx88_core_debug >= level) \
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printk(KERN_DEBUG "%s: " fmt, core->name , ## arg); \
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} while(0)
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2005-04-17 06:20:36 +08:00
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static unsigned int cx88_devcount;
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static LIST_HEAD(cx88_devlist);
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2006-01-15 17:52:23 +08:00
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static DEFINE_MUTEX(devlist);
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2005-04-17 06:20:36 +08:00
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#define NO_SYNC_LINE (-1U)
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V4L/DVB (6083): cx88-alsa: Rework buffer handling
Rework the way the DMA buffer is handled and IRQs are generated.
ALSA uses a ring-buffer of multiple periods. Each period is supposed to
corrispond to one IRQ.
The existing driver was generating one interrupt per ring-buffer, as opposed
to per period. This meant that as soon as the IRQ was generated, the hardware
was already starting to re-write the beginning of the buffer. Since the DMA
happens on a per-line basis, there was only a narrow window to copy the data
out before the buffer was overwritten.
The cx88 core RISC program generator is modified so that it can set the IRQ
and counter flags to count every X lines of DMA transfer. This way we can
generate an interrupt every period instead of every full ring-buffer. Right
now only period of one line are supported, but it should be possible to
support longer periods. Note that a WRITE instruction generates an IRQ when
it starts, not when the transfer is finished. Thus to generate an IRQ when
line X is done, one must set the IRQ flag on the instruction that starts line
X+1, not the one that ends line X.
Change the line size so that there are four lines in the SRAM FIFO. If there
are not four lines, the analog output from the cx88's internal DACs is full of
clicks and pops.
Try to handle FIFO sync errors. Sometimes the chip generates many of these
errors before audio data starts. Up to 50 sync errors will be ignored and the
counter reset.
Have the IRQ handler save the RISC counter to the chip struct, and then have
the pointer callback use this to calculate the pointer position. We could
read the counter from the pointer callback, but sometimes the sync errors on
start up cause the counter to go crazy. ALSA sees this and thinks there has
been an overrun. The IRQ hander can avoid saving the counter position on
sync errors.
The chip "opened" flag wasn't necessary. ALSA won't try to open the same
substream multiple times. Probably this code was cut&pasted from the bt87x
driver, which has multiple sub-streams for one chip.
Do error checking for the videobuf mapping functions.
snd_card_cx88_runtime_free() is useless and can be deleted.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2007-08-24 12:06:34 +08:00
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/* @lpi: lines per IRQ, or 0 to not generate irqs. Note: IRQ to be
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generated _after_ lpi lines are transferred. */
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2008-05-21 11:31:51 +08:00
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static __le32* cx88_risc_field(__le32 *rp, struct scatterlist *sglist,
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2005-04-17 06:20:36 +08:00
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unsigned int offset, u32 sync_line,
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unsigned int bpl, unsigned int padding,
|
V4L/DVB (6083): cx88-alsa: Rework buffer handling
Rework the way the DMA buffer is handled and IRQs are generated.
ALSA uses a ring-buffer of multiple periods. Each period is supposed to
corrispond to one IRQ.
The existing driver was generating one interrupt per ring-buffer, as opposed
to per period. This meant that as soon as the IRQ was generated, the hardware
was already starting to re-write the beginning of the buffer. Since the DMA
happens on a per-line basis, there was only a narrow window to copy the data
out before the buffer was overwritten.
The cx88 core RISC program generator is modified so that it can set the IRQ
and counter flags to count every X lines of DMA transfer. This way we can
generate an interrupt every period instead of every full ring-buffer. Right
now only period of one line are supported, but it should be possible to
support longer periods. Note that a WRITE instruction generates an IRQ when
it starts, not when the transfer is finished. Thus to generate an IRQ when
line X is done, one must set the IRQ flag on the instruction that starts line
X+1, not the one that ends line X.
Change the line size so that there are four lines in the SRAM FIFO. If there
are not four lines, the analog output from the cx88's internal DACs is full of
clicks and pops.
Try to handle FIFO sync errors. Sometimes the chip generates many of these
errors before audio data starts. Up to 50 sync errors will be ignored and the
counter reset.
Have the IRQ handler save the RISC counter to the chip struct, and then have
the pointer callback use this to calculate the pointer position. We could
read the counter from the pointer callback, but sometimes the sync errors on
start up cause the counter to go crazy. ALSA sees this and thinks there has
been an overrun. The IRQ hander can avoid saving the counter position on
sync errors.
The chip "opened" flag wasn't necessary. ALSA won't try to open the same
substream multiple times. Probably this code was cut&pasted from the bt87x
driver, which has multiple sub-streams for one chip.
Do error checking for the videobuf mapping functions.
snd_card_cx88_runtime_free() is useless and can be deleted.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2007-08-24 12:06:34 +08:00
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unsigned int lines, unsigned int lpi)
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2005-04-17 06:20:36 +08:00
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{
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struct scatterlist *sg;
|
V4L/DVB (6083): cx88-alsa: Rework buffer handling
Rework the way the DMA buffer is handled and IRQs are generated.
ALSA uses a ring-buffer of multiple periods. Each period is supposed to
corrispond to one IRQ.
The existing driver was generating one interrupt per ring-buffer, as opposed
to per period. This meant that as soon as the IRQ was generated, the hardware
was already starting to re-write the beginning of the buffer. Since the DMA
happens on a per-line basis, there was only a narrow window to copy the data
out before the buffer was overwritten.
The cx88 core RISC program generator is modified so that it can set the IRQ
and counter flags to count every X lines of DMA transfer. This way we can
generate an interrupt every period instead of every full ring-buffer. Right
now only period of one line are supported, but it should be possible to
support longer periods. Note that a WRITE instruction generates an IRQ when
it starts, not when the transfer is finished. Thus to generate an IRQ when
line X is done, one must set the IRQ flag on the instruction that starts line
X+1, not the one that ends line X.
Change the line size so that there are four lines in the SRAM FIFO. If there
are not four lines, the analog output from the cx88's internal DACs is full of
clicks and pops.
Try to handle FIFO sync errors. Sometimes the chip generates many of these
errors before audio data starts. Up to 50 sync errors will be ignored and the
counter reset.
Have the IRQ handler save the RISC counter to the chip struct, and then have
the pointer callback use this to calculate the pointer position. We could
read the counter from the pointer callback, but sometimes the sync errors on
start up cause the counter to go crazy. ALSA sees this and thinks there has
been an overrun. The IRQ hander can avoid saving the counter position on
sync errors.
The chip "opened" flag wasn't necessary. ALSA won't try to open the same
substream multiple times. Probably this code was cut&pasted from the bt87x
driver, which has multiple sub-streams for one chip.
Do error checking for the videobuf mapping functions.
snd_card_cx88_runtime_free() is useless and can be deleted.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2007-08-24 12:06:34 +08:00
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unsigned int line,todo,sol;
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2005-04-17 06:20:36 +08:00
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/* sync instruction */
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if (sync_line != NO_SYNC_LINE)
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*(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
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/* scan lines */
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sg = sglist;
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for (line = 0; line < lines; line++) {
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while (offset && offset >= sg_dma_len(sg)) {
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offset -= sg_dma_len(sg);
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sg++;
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}
|
V4L/DVB (6083): cx88-alsa: Rework buffer handling
Rework the way the DMA buffer is handled and IRQs are generated.
ALSA uses a ring-buffer of multiple periods. Each period is supposed to
corrispond to one IRQ.
The existing driver was generating one interrupt per ring-buffer, as opposed
to per period. This meant that as soon as the IRQ was generated, the hardware
was already starting to re-write the beginning of the buffer. Since the DMA
happens on a per-line basis, there was only a narrow window to copy the data
out before the buffer was overwritten.
The cx88 core RISC program generator is modified so that it can set the IRQ
and counter flags to count every X lines of DMA transfer. This way we can
generate an interrupt every period instead of every full ring-buffer. Right
now only period of one line are supported, but it should be possible to
support longer periods. Note that a WRITE instruction generates an IRQ when
it starts, not when the transfer is finished. Thus to generate an IRQ when
line X is done, one must set the IRQ flag on the instruction that starts line
X+1, not the one that ends line X.
Change the line size so that there are four lines in the SRAM FIFO. If there
are not four lines, the analog output from the cx88's internal DACs is full of
clicks and pops.
Try to handle FIFO sync errors. Sometimes the chip generates many of these
errors before audio data starts. Up to 50 sync errors will be ignored and the
counter reset.
Have the IRQ handler save the RISC counter to the chip struct, and then have
the pointer callback use this to calculate the pointer position. We could
read the counter from the pointer callback, but sometimes the sync errors on
start up cause the counter to go crazy. ALSA sees this and thinks there has
been an overrun. The IRQ hander can avoid saving the counter position on
sync errors.
The chip "opened" flag wasn't necessary. ALSA won't try to open the same
substream multiple times. Probably this code was cut&pasted from the bt87x
driver, which has multiple sub-streams for one chip.
Do error checking for the videobuf mapping functions.
snd_card_cx88_runtime_free() is useless and can be deleted.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2007-08-24 12:06:34 +08:00
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if (lpi && line>0 && !(line % lpi))
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sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
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else
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sol = RISC_SOL;
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2005-04-17 06:20:36 +08:00
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if (bpl <= sg_dma_len(sg)-offset) {
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/* fits into current chunk */
|
V4L/DVB (6083): cx88-alsa: Rework buffer handling
Rework the way the DMA buffer is handled and IRQs are generated.
ALSA uses a ring-buffer of multiple periods. Each period is supposed to
corrispond to one IRQ.
The existing driver was generating one interrupt per ring-buffer, as opposed
to per period. This meant that as soon as the IRQ was generated, the hardware
was already starting to re-write the beginning of the buffer. Since the DMA
happens on a per-line basis, there was only a narrow window to copy the data
out before the buffer was overwritten.
The cx88 core RISC program generator is modified so that it can set the IRQ
and counter flags to count every X lines of DMA transfer. This way we can
generate an interrupt every period instead of every full ring-buffer. Right
now only period of one line are supported, but it should be possible to
support longer periods. Note that a WRITE instruction generates an IRQ when
it starts, not when the transfer is finished. Thus to generate an IRQ when
line X is done, one must set the IRQ flag on the instruction that starts line
X+1, not the one that ends line X.
Change the line size so that there are four lines in the SRAM FIFO. If there
are not four lines, the analog output from the cx88's internal DACs is full of
clicks and pops.
Try to handle FIFO sync errors. Sometimes the chip generates many of these
errors before audio data starts. Up to 50 sync errors will be ignored and the
counter reset.
Have the IRQ handler save the RISC counter to the chip struct, and then have
the pointer callback use this to calculate the pointer position. We could
read the counter from the pointer callback, but sometimes the sync errors on
start up cause the counter to go crazy. ALSA sees this and thinks there has
been an overrun. The IRQ hander can avoid saving the counter position on
sync errors.
The chip "opened" flag wasn't necessary. ALSA won't try to open the same
substream multiple times. Probably this code was cut&pasted from the bt87x
driver, which has multiple sub-streams for one chip.
Do error checking for the videobuf mapping functions.
snd_card_cx88_runtime_free() is useless and can be deleted.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2007-08-24 12:06:34 +08:00
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*(rp++)=cpu_to_le32(RISC_WRITE|sol|RISC_EOL|bpl);
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2005-11-09 13:37:43 +08:00
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*(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
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offset+=bpl;
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2005-04-17 06:20:36 +08:00
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} else {
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2006-08-08 20:10:05 +08:00
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/* scanline needs to be split */
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2005-11-09 13:37:43 +08:00
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todo = bpl;
|
V4L/DVB (6083): cx88-alsa: Rework buffer handling
Rework the way the DMA buffer is handled and IRQs are generated.
ALSA uses a ring-buffer of multiple periods. Each period is supposed to
corrispond to one IRQ.
The existing driver was generating one interrupt per ring-buffer, as opposed
to per period. This meant that as soon as the IRQ was generated, the hardware
was already starting to re-write the beginning of the buffer. Since the DMA
happens on a per-line basis, there was only a narrow window to copy the data
out before the buffer was overwritten.
The cx88 core RISC program generator is modified so that it can set the IRQ
and counter flags to count every X lines of DMA transfer. This way we can
generate an interrupt every period instead of every full ring-buffer. Right
now only period of one line are supported, but it should be possible to
support longer periods. Note that a WRITE instruction generates an IRQ when
it starts, not when the transfer is finished. Thus to generate an IRQ when
line X is done, one must set the IRQ flag on the instruction that starts line
X+1, not the one that ends line X.
Change the line size so that there are four lines in the SRAM FIFO. If there
are not four lines, the analog output from the cx88's internal DACs is full of
clicks and pops.
Try to handle FIFO sync errors. Sometimes the chip generates many of these
errors before audio data starts. Up to 50 sync errors will be ignored and the
counter reset.
Have the IRQ handler save the RISC counter to the chip struct, and then have
the pointer callback use this to calculate the pointer position. We could
read the counter from the pointer callback, but sometimes the sync errors on
start up cause the counter to go crazy. ALSA sees this and thinks there has
been an overrun. The IRQ hander can avoid saving the counter position on
sync errors.
The chip "opened" flag wasn't necessary. ALSA won't try to open the same
substream multiple times. Probably this code was cut&pasted from the bt87x
driver, which has multiple sub-streams for one chip.
Do error checking for the videobuf mapping functions.
snd_card_cx88_runtime_free() is useless and can be deleted.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2007-08-24 12:06:34 +08:00
|
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*(rp++)=cpu_to_le32(RISC_WRITE|sol|
|
2005-04-17 06:20:36 +08:00
|
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(sg_dma_len(sg)-offset));
|
2005-11-09 13:37:43 +08:00
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*(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
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todo -= (sg_dma_len(sg)-offset);
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offset = 0;
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sg++;
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while (todo > sg_dma_len(sg)) {
|
2005-11-09 13:37:45 +08:00
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*(rp++)=cpu_to_le32(RISC_WRITE|
|
2005-04-17 06:20:36 +08:00
|
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sg_dma_len(sg));
|
2005-11-09 13:37:45 +08:00
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*(rp++)=cpu_to_le32(sg_dma_address(sg));
|
2005-04-17 06:20:36 +08:00
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todo -= sg_dma_len(sg);
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sg++;
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}
|
2005-11-09 13:37:43 +08:00
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*(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
|
2005-04-17 06:20:36 +08:00
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*(rp++)=cpu_to_le32(sg_dma_address(sg));
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offset += todo;
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}
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offset += padding;
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}
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return rp;
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}
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int cx88_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
|
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struct scatterlist *sglist,
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unsigned int top_offset, unsigned int bottom_offset,
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unsigned int bpl, unsigned int padding, unsigned int lines)
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{
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u32 instructions,fields;
|
2008-05-21 11:31:51 +08:00
|
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|
__le32 *rp;
|
2005-04-17 06:20:36 +08:00
|
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|
int rc;
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fields = 0;
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if (UNSET != top_offset)
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fields++;
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if (UNSET != bottom_offset)
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fields++;
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/* estimate risc mem: worst case is one write per page border +
|
2006-04-11 21:18:57 +08:00
|
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|
one write per scan line + syncs + jump (all 2 dwords). Padding
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can cause next bpl to start close to a page border. First DMA
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region may be smaller than PAGE_SIZE */
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instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
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instructions += 2;
|
2005-04-17 06:20:36 +08:00
|
|
|
if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
|
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
|
|
/* write risc instructions */
|
|
|
|
|
rp = risc->cpu;
|
|
|
|
|
if (UNSET != top_offset)
|
|
|
|
|
rp = cx88_risc_field(rp, sglist, top_offset, 0,
|
V4L/DVB (6083): cx88-alsa: Rework buffer handling
Rework the way the DMA buffer is handled and IRQs are generated.
ALSA uses a ring-buffer of multiple periods. Each period is supposed to
corrispond to one IRQ.
The existing driver was generating one interrupt per ring-buffer, as opposed
to per period. This meant that as soon as the IRQ was generated, the hardware
was already starting to re-write the beginning of the buffer. Since the DMA
happens on a per-line basis, there was only a narrow window to copy the data
out before the buffer was overwritten.
The cx88 core RISC program generator is modified so that it can set the IRQ
and counter flags to count every X lines of DMA transfer. This way we can
generate an interrupt every period instead of every full ring-buffer. Right
now only period of one line are supported, but it should be possible to
support longer periods. Note that a WRITE instruction generates an IRQ when
it starts, not when the transfer is finished. Thus to generate an IRQ when
line X is done, one must set the IRQ flag on the instruction that starts line
X+1, not the one that ends line X.
Change the line size so that there are four lines in the SRAM FIFO. If there
are not four lines, the analog output from the cx88's internal DACs is full of
clicks and pops.
Try to handle FIFO sync errors. Sometimes the chip generates many of these
errors before audio data starts. Up to 50 sync errors will be ignored and the
counter reset.
Have the IRQ handler save the RISC counter to the chip struct, and then have
the pointer callback use this to calculate the pointer position. We could
read the counter from the pointer callback, but sometimes the sync errors on
start up cause the counter to go crazy. ALSA sees this and thinks there has
been an overrun. The IRQ hander can avoid saving the counter position on
sync errors.
The chip "opened" flag wasn't necessary. ALSA won't try to open the same
substream multiple times. Probably this code was cut&pasted from the bt87x
driver, which has multiple sub-streams for one chip.
Do error checking for the videobuf mapping functions.
snd_card_cx88_runtime_free() is useless and can be deleted.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2007-08-24 12:06:34 +08:00
|
|
|
bpl, padding, lines, 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (UNSET != bottom_offset)
|
|
|
|
|
rp = cx88_risc_field(rp, sglist, bottom_offset, 0x200,
|
V4L/DVB (6083): cx88-alsa: Rework buffer handling
Rework the way the DMA buffer is handled and IRQs are generated.
ALSA uses a ring-buffer of multiple periods. Each period is supposed to
corrispond to one IRQ.
The existing driver was generating one interrupt per ring-buffer, as opposed
to per period. This meant that as soon as the IRQ was generated, the hardware
was already starting to re-write the beginning of the buffer. Since the DMA
happens on a per-line basis, there was only a narrow window to copy the data
out before the buffer was overwritten.
The cx88 core RISC program generator is modified so that it can set the IRQ
and counter flags to count every X lines of DMA transfer. This way we can
generate an interrupt every period instead of every full ring-buffer. Right
now only period of one line are supported, but it should be possible to
support longer periods. Note that a WRITE instruction generates an IRQ when
it starts, not when the transfer is finished. Thus to generate an IRQ when
line X is done, one must set the IRQ flag on the instruction that starts line
X+1, not the one that ends line X.
Change the line size so that there are four lines in the SRAM FIFO. If there
are not four lines, the analog output from the cx88's internal DACs is full of
clicks and pops.
Try to handle FIFO sync errors. Sometimes the chip generates many of these
errors before audio data starts. Up to 50 sync errors will be ignored and the
counter reset.
Have the IRQ handler save the RISC counter to the chip struct, and then have
the pointer callback use this to calculate the pointer position. We could
read the counter from the pointer callback, but sometimes the sync errors on
start up cause the counter to go crazy. ALSA sees this and thinks there has
been an overrun. The IRQ hander can avoid saving the counter position on
sync errors.
The chip "opened" flag wasn't necessary. ALSA won't try to open the same
substream multiple times. Probably this code was cut&pasted from the bt87x
driver, which has multiple sub-streams for one chip.
Do error checking for the videobuf mapping functions.
snd_card_cx88_runtime_free() is useless and can be deleted.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2007-08-24 12:06:34 +08:00
|
|
|
bpl, padding, lines, 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/* save pointer to jmp instruction address */
|
|
|
|
|
risc->jmp = rp;
|
V4L/DVB (3394): Bttv: correct bttv_risc_packed buffer size
This patch fixes the strange crashes I was seeing after using
bttv card, caused by a buffer overflow in bttv_risc_packed.
The instruction buffer size calculation contains two errors:
(a) a non-zero padding value can push the start of the next bpl
section to just before a page border, leading to more scanline
splits and thus additional instructions.
(b) the first DMA region can be smaller than one page, so there can
be a scanline split even if bpl*lines is smaller than PAGE_SIZE.
For example, consider the case where offset is 0, bpl is 2, padding
is 4094, lines is smaller than 2048, the first DMA region has size 1
and all others have size PAGE_SIZE, assumed to equal 4096. Then
all bpl regions cross page borders and the number of instructions
written is 2*lines+2, rather than lines+2 (the current estimate).
With this patch the number of instructions for this example is
estimated to be 2*lines+3.
Also, the BUG_ON that was supposed to catch buffer overflows contained
a thinko causing it fire only if the buffer was overrun by a factor of
16 or more, so it fixes the the BUG_ON's (using sizeof rather than "4").
Signed-off-by: Duncan Sands <baldrick@free.fr>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2006-02-27 11:09:48 +08:00
|
|
|
BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
|
2005-04-17 06:20:36 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int cx88_risc_databuffer(struct pci_dev *pci, struct btcx_riscmem *risc,
|
|
|
|
|
struct scatterlist *sglist, unsigned int bpl,
|
V4L/DVB (6083): cx88-alsa: Rework buffer handling
Rework the way the DMA buffer is handled and IRQs are generated.
ALSA uses a ring-buffer of multiple periods. Each period is supposed to
corrispond to one IRQ.
The existing driver was generating one interrupt per ring-buffer, as opposed
to per period. This meant that as soon as the IRQ was generated, the hardware
was already starting to re-write the beginning of the buffer. Since the DMA
happens on a per-line basis, there was only a narrow window to copy the data
out before the buffer was overwritten.
The cx88 core RISC program generator is modified so that it can set the IRQ
and counter flags to count every X lines of DMA transfer. This way we can
generate an interrupt every period instead of every full ring-buffer. Right
now only period of one line are supported, but it should be possible to
support longer periods. Note that a WRITE instruction generates an IRQ when
it starts, not when the transfer is finished. Thus to generate an IRQ when
line X is done, one must set the IRQ flag on the instruction that starts line
X+1, not the one that ends line X.
Change the line size so that there are four lines in the SRAM FIFO. If there
are not four lines, the analog output from the cx88's internal DACs is full of
clicks and pops.
Try to handle FIFO sync errors. Sometimes the chip generates many of these
errors before audio data starts. Up to 50 sync errors will be ignored and the
counter reset.
Have the IRQ handler save the RISC counter to the chip struct, and then have
the pointer callback use this to calculate the pointer position. We could
read the counter from the pointer callback, but sometimes the sync errors on
start up cause the counter to go crazy. ALSA sees this and thinks there has
been an overrun. The IRQ hander can avoid saving the counter position on
sync errors.
The chip "opened" flag wasn't necessary. ALSA won't try to open the same
substream multiple times. Probably this code was cut&pasted from the bt87x
driver, which has multiple sub-streams for one chip.
Do error checking for the videobuf mapping functions.
snd_card_cx88_runtime_free() is useless and can be deleted.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2007-08-24 12:06:34 +08:00
|
|
|
unsigned int lines, unsigned int lpi)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
u32 instructions;
|
2008-05-21 11:31:51 +08:00
|
|
|
__le32 *rp;
|
2005-04-17 06:20:36 +08:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
|
|
/* estimate risc mem: worst case is one write per page border +
|
2006-04-11 21:18:57 +08:00
|
|
|
one write per scan line + syncs + jump (all 2 dwords). Here
|
|
|
|
|
there is no padding and no sync. First DMA region may be smaller
|
|
|
|
|
than PAGE_SIZE */
|
|
|
|
|
instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
|
|
|
|
|
instructions += 1;
|
2005-04-17 06:20:36 +08:00
|
|
|
if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
|
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
|
|
/* write risc instructions */
|
|
|
|
|
rp = risc->cpu;
|
V4L/DVB (6083): cx88-alsa: Rework buffer handling
Rework the way the DMA buffer is handled and IRQs are generated.
ALSA uses a ring-buffer of multiple periods. Each period is supposed to
corrispond to one IRQ.
The existing driver was generating one interrupt per ring-buffer, as opposed
to per period. This meant that as soon as the IRQ was generated, the hardware
was already starting to re-write the beginning of the buffer. Since the DMA
happens on a per-line basis, there was only a narrow window to copy the data
out before the buffer was overwritten.
The cx88 core RISC program generator is modified so that it can set the IRQ
and counter flags to count every X lines of DMA transfer. This way we can
generate an interrupt every period instead of every full ring-buffer. Right
now only period of one line are supported, but it should be possible to
support longer periods. Note that a WRITE instruction generates an IRQ when
it starts, not when the transfer is finished. Thus to generate an IRQ when
line X is done, one must set the IRQ flag on the instruction that starts line
X+1, not the one that ends line X.
Change the line size so that there are four lines in the SRAM FIFO. If there
are not four lines, the analog output from the cx88's internal DACs is full of
clicks and pops.
Try to handle FIFO sync errors. Sometimes the chip generates many of these
errors before audio data starts. Up to 50 sync errors will be ignored and the
counter reset.
Have the IRQ handler save the RISC counter to the chip struct, and then have
the pointer callback use this to calculate the pointer position. We could
read the counter from the pointer callback, but sometimes the sync errors on
start up cause the counter to go crazy. ALSA sees this and thinks there has
been an overrun. The IRQ hander can avoid saving the counter position on
sync errors.
The chip "opened" flag wasn't necessary. ALSA won't try to open the same
substream multiple times. Probably this code was cut&pasted from the bt87x
driver, which has multiple sub-streams for one chip.
Do error checking for the videobuf mapping functions.
snd_card_cx88_runtime_free() is useless and can be deleted.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2007-08-24 12:06:34 +08:00
|
|
|
rp = cx88_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines, lpi);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/* save pointer to jmp instruction address */
|
|
|
|
|
risc->jmp = rp;
|
V4L/DVB (3394): Bttv: correct bttv_risc_packed buffer size
This patch fixes the strange crashes I was seeing after using
bttv card, caused by a buffer overflow in bttv_risc_packed.
The instruction buffer size calculation contains two errors:
(a) a non-zero padding value can push the start of the next bpl
section to just before a page border, leading to more scanline
splits and thus additional instructions.
(b) the first DMA region can be smaller than one page, so there can
be a scanline split even if bpl*lines is smaller than PAGE_SIZE.
For example, consider the case where offset is 0, bpl is 2, padding
is 4094, lines is smaller than 2048, the first DMA region has size 1
and all others have size PAGE_SIZE, assumed to equal 4096. Then
all bpl regions cross page borders and the number of instructions
written is 2*lines+2, rather than lines+2 (the current estimate).
With this patch the number of instructions for this example is
estimated to be 2*lines+3.
Also, the BUG_ON that was supposed to catch buffer overflows contained
a thinko causing it fire only if the buffer was overrun by a factor of
16 or more, so it fixes the the BUG_ON's (using sizeof rather than "4").
Signed-off-by: Duncan Sands <baldrick@free.fr>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2006-02-27 11:09:48 +08:00
|
|
|
BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
|
2005-04-17 06:20:36 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int cx88_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
|
|
|
|
|
u32 reg, u32 mask, u32 value)
|
|
|
|
|
{
|
2008-05-21 11:31:51 +08:00
|
|
|
__le32 *rp;
|
2005-04-17 06:20:36 +08:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
|
|
if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
|
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
|
|
/* write risc instructions */
|
|
|
|
|
rp = risc->cpu;
|
|
|
|
|
*(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2 | RISC_IMM);
|
|
|
|
|
*(rp++) = cpu_to_le32(reg);
|
|
|
|
|
*(rp++) = cpu_to_le32(value);
|
|
|
|
|
*(rp++) = cpu_to_le32(mask);
|
|
|
|
|
*(rp++) = cpu_to_le32(RISC_JUMP);
|
|
|
|
|
*(rp++) = cpu_to_le32(risc->dma);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2006-03-10 23:29:15 +08:00
|
|
|
cx88_free_buffer(struct videobuf_queue *q, struct cx88_buffer *buf)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2007-08-24 03:37:49 +08:00
|
|
|
struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb);
|
|
|
|
|
|
2006-03-14 00:17:11 +08:00
|
|
|
BUG_ON(in_interrupt());
|
2010-09-26 20:01:26 +08:00
|
|
|
videobuf_waiton(q, &buf->vb, 0, 0);
|
2010-05-11 21:36:30 +08:00
|
|
|
videobuf_dma_unmap(q->dev, dma);
|
2007-08-24 03:37:49 +08:00
|
|
|
videobuf_dma_free(dma);
|
2008-04-23 01:46:02 +08:00
|
|
|
btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
|
2007-11-07 07:02:36 +08:00
|
|
|
buf->vb.state = VIDEOBUF_NEEDS_INIT;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------ */
|
|
|
|
|
/* our SRAM memory layout */
|
|
|
|
|
|
|
|
|
|
/* we are going to put all thr risc programs into host memory, so we
|
|
|
|
|
* can use the whole SDRAM for the DMA fifos. To simplify things, we
|
|
|
|
|
* use a static memory layout. That surely will waste memory in case
|
|
|
|
|
* we don't use all DMA channels at the same time (which will be the
|
2009-04-01 06:01:51 +08:00
|
|
|
* case most of the time). But that still gives us enough FIFO space
|
2005-04-17 06:20:36 +08:00
|
|
|
* to be able to deal with insane long pci latencies ...
|
|
|
|
|
*
|
|
|
|
|
* FIFO space allocations:
|
|
|
|
|
* channel 21 (y video) - 10.0k
|
|
|
|
|
* channel 22 (u video) - 2.0k
|
|
|
|
|
* channel 23 (v video) - 2.0k
|
|
|
|
|
* channel 24 (vbi) - 4.0k
|
2006-01-10 01:32:44 +08:00
|
|
|
* channels 25+26 (audio) - 4.0k
|
2005-04-17 06:20:36 +08:00
|
|
|
* channel 28 (mpeg) - 4.0k
|
2009-04-01 06:01:51 +08:00
|
|
|
* channel 27 (audio rds)- 3.0k
|
2006-01-10 01:32:44 +08:00
|
|
|
* TOTAL = 29.0k
|
2005-04-17 06:20:36 +08:00
|
|
|
*
|
|
|
|
|
* Every channel has 160 bytes control data (64 bytes instruction
|
|
|
|
|
* queue and 6 CDT entries), which is close to 2k total.
|
|
|
|
|
*
|
|
|
|
|
* Address layout:
|
|
|
|
|
* 0x0000 - 0x03ff CMDs / reserved
|
|
|
|
|
* 0x0400 - 0x0bff instruction queues + CDs
|
|
|
|
|
* 0x0c00 - FIFOs
|
|
|
|
|
*/
|
|
|
|
|
|
2012-05-04 16:33:37 +08:00
|
|
|
const struct sram_channel cx88_sram_channels[] = {
|
2005-04-17 06:20:36 +08:00
|
|
|
[SRAM_CH21] = {
|
|
|
|
|
.name = "video y / packed",
|
|
|
|
|
.cmds_start = 0x180040,
|
|
|
|
|
.ctrl_start = 0x180400,
|
2005-11-09 13:37:43 +08:00
|
|
|
.cdt = 0x180400 + 64,
|
2005-04-17 06:20:36 +08:00
|
|
|
.fifo_start = 0x180c00,
|
|
|
|
|
.fifo_size = 0x002800,
|
|
|
|
|
.ptr1_reg = MO_DMA21_PTR1,
|
|
|
|
|
.ptr2_reg = MO_DMA21_PTR2,
|
|
|
|
|
.cnt1_reg = MO_DMA21_CNT1,
|
|
|
|
|
.cnt2_reg = MO_DMA21_CNT2,
|
|
|
|
|
},
|
|
|
|
|
[SRAM_CH22] = {
|
|
|
|
|
.name = "video u",
|
|
|
|
|
.cmds_start = 0x180080,
|
|
|
|
|
.ctrl_start = 0x1804a0,
|
2005-11-09 13:37:43 +08:00
|
|
|
.cdt = 0x1804a0 + 64,
|
2005-04-17 06:20:36 +08:00
|
|
|
.fifo_start = 0x183400,
|
|
|
|
|
.fifo_size = 0x000800,
|
|
|
|
|
.ptr1_reg = MO_DMA22_PTR1,
|
|
|
|
|
.ptr2_reg = MO_DMA22_PTR2,
|
|
|
|
|
.cnt1_reg = MO_DMA22_CNT1,
|
|
|
|
|
.cnt2_reg = MO_DMA22_CNT2,
|
|
|
|
|
},
|
|
|
|
|
[SRAM_CH23] = {
|
|
|
|
|
.name = "video v",
|
|
|
|
|
.cmds_start = 0x1800c0,
|
|
|
|
|
.ctrl_start = 0x180540,
|
2005-11-09 13:37:43 +08:00
|
|
|
.cdt = 0x180540 + 64,
|
2005-04-17 06:20:36 +08:00
|
|
|
.fifo_start = 0x183c00,
|
|
|
|
|
.fifo_size = 0x000800,
|
|
|
|
|
.ptr1_reg = MO_DMA23_PTR1,
|
|
|
|
|
.ptr2_reg = MO_DMA23_PTR2,
|
|
|
|
|
.cnt1_reg = MO_DMA23_CNT1,
|
|
|
|
|
.cnt2_reg = MO_DMA23_CNT2,
|
|
|
|
|
},
|
|
|
|
|
[SRAM_CH24] = {
|
|
|
|
|
.name = "vbi",
|
|
|
|
|
.cmds_start = 0x180100,
|
|
|
|
|
.ctrl_start = 0x1805e0,
|
2005-11-09 13:37:43 +08:00
|
|
|
.cdt = 0x1805e0 + 64,
|
2005-04-17 06:20:36 +08:00
|
|
|
.fifo_start = 0x184400,
|
|
|
|
|
.fifo_size = 0x001000,
|
|
|
|
|
.ptr1_reg = MO_DMA24_PTR1,
|
|
|
|
|
.ptr2_reg = MO_DMA24_PTR2,
|
|
|
|
|
.cnt1_reg = MO_DMA24_CNT1,
|
|
|
|
|
.cnt2_reg = MO_DMA24_CNT2,
|
|
|
|
|
},
|
|
|
|
|
[SRAM_CH25] = {
|
|
|
|
|
.name = "audio from",
|
|
|
|
|
.cmds_start = 0x180140,
|
|
|
|
|
.ctrl_start = 0x180680,
|
2005-11-09 13:37:43 +08:00
|
|
|
.cdt = 0x180680 + 64,
|
2005-04-17 06:20:36 +08:00
|
|
|
.fifo_start = 0x185400,
|
2006-01-10 01:32:44 +08:00
|
|
|
.fifo_size = 0x001000,
|
2005-04-17 06:20:36 +08:00
|
|
|
.ptr1_reg = MO_DMA25_PTR1,
|
|
|
|
|
.ptr2_reg = MO_DMA25_PTR2,
|
|
|
|
|
.cnt1_reg = MO_DMA25_CNT1,
|
|
|
|
|
.cnt2_reg = MO_DMA25_CNT2,
|
|
|
|
|
},
|
|
|
|
|
[SRAM_CH26] = {
|
|
|
|
|
.name = "audio to",
|
|
|
|
|
.cmds_start = 0x180180,
|
|
|
|
|
.ctrl_start = 0x180720,
|
2005-11-09 13:37:43 +08:00
|
|
|
.cdt = 0x180680 + 64, /* same as audio IN */
|
2005-04-17 06:20:36 +08:00
|
|
|
.fifo_start = 0x185400, /* same as audio IN */
|
2006-01-10 01:32:44 +08:00
|
|
|
.fifo_size = 0x001000, /* same as audio IN */
|
2005-04-17 06:20:36 +08:00
|
|
|
.ptr1_reg = MO_DMA26_PTR1,
|
|
|
|
|
.ptr2_reg = MO_DMA26_PTR2,
|
|
|
|
|
.cnt1_reg = MO_DMA26_CNT1,
|
|
|
|
|
.cnt2_reg = MO_DMA26_CNT2,
|
|
|
|
|
},
|
|
|
|
|
[SRAM_CH28] = {
|
|
|
|
|
.name = "mpeg",
|
|
|
|
|
.cmds_start = 0x180200,
|
|
|
|
|
.ctrl_start = 0x1807C0,
|
|
|
|
|
.cdt = 0x1807C0 + 64,
|
2006-01-10 01:32:44 +08:00
|
|
|
.fifo_start = 0x186400,
|
2005-04-17 06:20:36 +08:00
|
|
|
.fifo_size = 0x001000,
|
|
|
|
|
.ptr1_reg = MO_DMA28_PTR1,
|
|
|
|
|
.ptr2_reg = MO_DMA28_PTR2,
|
|
|
|
|
.cnt1_reg = MO_DMA28_CNT1,
|
|
|
|
|
.cnt2_reg = MO_DMA28_CNT2,
|
|
|
|
|
},
|
2009-04-01 06:01:51 +08:00
|
|
|
[SRAM_CH27] = {
|
|
|
|
|
.name = "audio rds",
|
|
|
|
|
.cmds_start = 0x1801C0,
|
|
|
|
|
.ctrl_start = 0x180860,
|
|
|
|
|
.cdt = 0x180860 + 64,
|
|
|
|
|
.fifo_start = 0x187400,
|
|
|
|
|
.fifo_size = 0x000C00,
|
|
|
|
|
.ptr1_reg = MO_DMA27_PTR1,
|
|
|
|
|
.ptr2_reg = MO_DMA27_PTR2,
|
|
|
|
|
.cnt1_reg = MO_DMA27_CNT1,
|
|
|
|
|
.cnt2_reg = MO_DMA27_CNT2,
|
|
|
|
|
},
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int cx88_sram_channel_setup(struct cx88_core *core,
|
2010-08-25 20:50:20 +08:00
|
|
|
const struct sram_channel *ch,
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned int bpl, u32 risc)
|
|
|
|
|
{
|
|
|
|
|
unsigned int i,lines;
|
|
|
|
|
u32 cdt;
|
|
|
|
|
|
|
|
|
|
bpl = (bpl + 7) & ~7; /* alignment */
|
|
|
|
|
cdt = ch->cdt;
|
|
|
|
|
lines = ch->fifo_size / bpl;
|
|
|
|
|
if (lines > 6)
|
|
|
|
|
lines = 6;
|
|
|
|
|
BUG_ON(lines < 2);
|
|
|
|
|
|
|
|
|
|
/* write CDT */
|
|
|
|
|
for (i = 0; i < lines; i++)
|
|
|
|
|
cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
|
|
|
|
|
|
|
|
|
|
/* write CMDS */
|
|
|
|
|
cx_write(ch->cmds_start + 0, risc);
|
|
|
|
|
cx_write(ch->cmds_start + 4, cdt);
|
|
|
|
|
cx_write(ch->cmds_start + 8, (lines*16) >> 3);
|
|
|
|
|
cx_write(ch->cmds_start + 12, ch->ctrl_start);
|
|
|
|
|
cx_write(ch->cmds_start + 16, 64 >> 2);
|
|
|
|
|
for (i = 20; i < 64; i += 4)
|
|
|
|
|
cx_write(ch->cmds_start + i, 0);
|
|
|
|
|
|
|
|
|
|
/* fill registers */
|
|
|
|
|
cx_write(ch->ptr1_reg, ch->fifo_start);
|
|
|
|
|
cx_write(ch->ptr2_reg, cdt);
|
|
|
|
|
cx_write(ch->cnt1_reg, (bpl >> 3) -1);
|
|
|
|
|
cx_write(ch->cnt2_reg, (lines*16) >> 3);
|
|
|
|
|
|
|
|
|
|
dprintk(2,"sram setup %s: bpl=%d lines=%d\n", ch->name, bpl, lines);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------ */
|
|
|
|
|
/* debug helper code */
|
|
|
|
|
|
2005-11-09 13:36:29 +08:00
|
|
|
static int cx88_risc_decode(u32 risc)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2010-08-25 20:50:20 +08:00
|
|
|
static const char * const instr[16] = {
|
2005-04-17 06:20:36 +08:00
|
|
|
[ RISC_SYNC >> 28 ] = "sync",
|
|
|
|
|
[ RISC_WRITE >> 28 ] = "write",
|
|
|
|
|
[ RISC_WRITEC >> 28 ] = "writec",
|
|
|
|
|
[ RISC_READ >> 28 ] = "read",
|
|
|
|
|
[ RISC_READC >> 28 ] = "readc",
|
|
|
|
|
[ RISC_JUMP >> 28 ] = "jump",
|
|
|
|
|
[ RISC_SKIP >> 28 ] = "skip",
|
|
|
|
|
[ RISC_WRITERM >> 28 ] = "writerm",
|
|
|
|
|
[ RISC_WRITECM >> 28 ] = "writecm",
|
|
|
|
|
[ RISC_WRITECR >> 28 ] = "writecr",
|
|
|
|
|
};
|
2010-08-25 20:50:20 +08:00
|
|
|
static int const incr[16] = {
|
2005-04-17 06:20:36 +08:00
|
|
|
[ RISC_WRITE >> 28 ] = 2,
|
|
|
|
|
[ RISC_JUMP >> 28 ] = 2,
|
|
|
|
|
[ RISC_WRITERM >> 28 ] = 3,
|
|
|
|
|
[ RISC_WRITECM >> 28 ] = 3,
|
|
|
|
|
[ RISC_WRITECR >> 28 ] = 4,
|
|
|
|
|
};
|
2010-08-25 20:50:20 +08:00
|
|
|
static const char * const bits[] = {
|
2005-04-17 06:20:36 +08:00
|
|
|
"12", "13", "14", "resync",
|
|
|
|
|
"cnt0", "cnt1", "18", "19",
|
|
|
|
|
"20", "21", "22", "23",
|
|
|
|
|
"irq1", "irq2", "eol", "sol",
|
|
|
|
|
};
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
printk("0x%08x [ %s", risc,
|
|
|
|
|
instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
|
|
|
|
|
for (i = ARRAY_SIZE(bits)-1; i >= 0; i--)
|
|
|
|
|
if (risc & (1 << (i + 12)))
|
|
|
|
|
printk(" %s",bits[i]);
|
|
|
|
|
printk(" count=%d ]\n", risc & 0xfff);
|
|
|
|
|
return incr[risc >> 28] ? incr[risc >> 28] : 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void cx88_sram_channel_dump(struct cx88_core *core,
|
2010-08-25 20:50:20 +08:00
|
|
|
const struct sram_channel *ch)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2010-08-25 20:50:20 +08:00
|
|
|
static const char * const name[] = {
|
2005-04-17 06:20:36 +08:00
|
|
|
"initial risc",
|
|
|
|
|
"cdt base",
|
|
|
|
|
"cdt size",
|
|
|
|
|
"iq base",
|
|
|
|
|
"iq size",
|
|
|
|
|
"risc pc",
|
|
|
|
|
"iq wr ptr",
|
|
|
|
|
"iq rd ptr",
|
|
|
|
|
"cdt current",
|
|
|
|
|
"pci target",
|
|
|
|
|
"line / byte",
|
|
|
|
|
};
|
|
|
|
|
u32 risc;
|
|
|
|
|
unsigned int i,j,n;
|
|
|
|
|
|
|
|
|
|
printk("%s: %s - dma channel status dump\n",
|
|
|
|
|
core->name,ch->name);
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(name); i++)
|
|
|
|
|
printk("%s: cmds: %-12s: 0x%08x\n",
|
|
|
|
|
core->name,name[i],
|
|
|
|
|
cx_read(ch->cmds_start + 4*i));
|
2007-08-21 19:19:16 +08:00
|
|
|
for (n = 1, i = 0; i < 4; i++) {
|
2005-04-17 06:20:36 +08:00
|
|
|
risc = cx_read(ch->cmds_start + 4 * (i+11));
|
|
|
|
|
printk("%s: risc%d: ", core->name, i);
|
2007-08-21 19:19:16 +08:00
|
|
|
if (--n)
|
|
|
|
|
printk("0x%08x [ arg #%d ]\n", risc, n);
|
|
|
|
|
else
|
|
|
|
|
n = cx88_risc_decode(risc);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
for (i = 0; i < 16; i += n) {
|
|
|
|
|
risc = cx_read(ch->ctrl_start + 4 * i);
|
|
|
|
|
printk("%s: iq %x: ", core->name, i);
|
|
|
|
|
n = cx88_risc_decode(risc);
|
|
|
|
|
for (j = 1; j < n; j++) {
|
|
|
|
|
risc = cx_read(ch->ctrl_start + 4 * (i+j));
|
|
|
|
|
printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
|
|
|
|
|
core->name, i+j, risc, j);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printk("%s: fifo: 0x%08x -> 0x%x\n",
|
|
|
|
|
core->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
|
|
|
|
|
printk("%s: ctrl: 0x%08x -> 0x%x\n",
|
|
|
|
|
core->name, ch->ctrl_start, ch->ctrl_start+6*16);
|
|
|
|
|
printk("%s: ptr1_reg: 0x%08x\n",
|
|
|
|
|
core->name,cx_read(ch->ptr1_reg));
|
|
|
|
|
printk("%s: ptr2_reg: 0x%08x\n",
|
|
|
|
|
core->name,cx_read(ch->ptr2_reg));
|
|
|
|
|
printk("%s: cnt1_reg: 0x%08x\n",
|
|
|
|
|
core->name,cx_read(ch->cnt1_reg));
|
|
|
|
|
printk("%s: cnt2_reg: 0x%08x\n",
|
|
|
|
|
core->name,cx_read(ch->cnt2_reg));
|
|
|
|
|
}
|
|
|
|
|
|
2010-08-25 20:50:20 +08:00
|
|
|
static const char *cx88_pci_irqs[32] = {
|
2005-04-17 06:20:36 +08:00
|
|
|
"vid", "aud", "ts", "vip", "hst", "5", "6", "tm1",
|
|
|
|
|
"src_dma", "dst_dma", "risc_rd_err", "risc_wr_err",
|
|
|
|
|
"brdg_err", "src_dma_err", "dst_dma_err", "ipb_dma_err",
|
|
|
|
|
"i2c", "i2c_rack", "ir_smp", "gpio0", "gpio1"
|
|
|
|
|
};
|
|
|
|
|
|
2010-08-25 20:50:20 +08:00
|
|
|
void cx88_print_irqbits(const char *name, const char *tag, const char *strings[],
|
2007-03-29 19:47:04 +08:00
|
|
|
int len, u32 bits, u32 mask)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
|
|
printk(KERN_DEBUG "%s: %s [0x%x]", name, tag, bits);
|
2007-03-29 19:47:04 +08:00
|
|
|
for (i = 0; i < len; i++) {
|
2005-04-17 06:20:36 +08:00
|
|
|
if (!(bits & (1 << i)))
|
|
|
|
|
continue;
|
|
|
|
|
if (strings[i])
|
|
|
|
|
printk(" %s", strings[i]);
|
|
|
|
|
else
|
|
|
|
|
printk(" %d", i);
|
|
|
|
|
if (!(mask & (1 << i)))
|
|
|
|
|
continue;
|
|
|
|
|
printk("*");
|
|
|
|
|
}
|
|
|
|
|
printk("\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------ */
|
|
|
|
|
|
|
|
|
|
int cx88_core_irq(struct cx88_core *core, u32 status)
|
|
|
|
|
{
|
|
|
|
|
int handled = 0;
|
|
|
|
|
|
2007-08-18 17:57:55 +08:00
|
|
|
if (status & PCI_INT_IR_SMPINT) {
|
2005-04-17 06:20:36 +08:00
|
|
|
cx88_ir_irq(core);
|
|
|
|
|
handled++;
|
|
|
|
|
}
|
|
|
|
|
if (!handled)
|
|
|
|
|
cx88_print_irqbits(core->name, "irq pci",
|
2007-03-29 19:47:04 +08:00
|
|
|
cx88_pci_irqs, ARRAY_SIZE(cx88_pci_irqs),
|
|
|
|
|
status, core->pci_irqmask);
|
2005-04-17 06:20:36 +08:00
|
|
|
return handled;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void cx88_wakeup(struct cx88_core *core,
|
|
|
|
|
struct cx88_dmaqueue *q, u32 count)
|
|
|
|
|
{
|
|
|
|
|
struct cx88_buffer *buf;
|
|
|
|
|
int bc;
|
|
|
|
|
|
|
|
|
|
for (bc = 0;; bc++) {
|
|
|
|
|
if (list_empty(&q->active))
|
|
|
|
|
break;
|
|
|
|
|
buf = list_entry(q->active.next,
|
|
|
|
|
struct cx88_buffer, vb.queue);
|
|
|
|
|
/* count comes from the hw and is is 16bit wide --
|
|
|
|
|
* this trick handles wrap-arounds correctly for
|
|
|
|
|
* up to 32767 buffers in flight... */
|
|
|
|
|
if ((s16) (count - buf->count) < 0)
|
|
|
|
|
break;
|
2012-09-16 02:14:42 +08:00
|
|
|
v4l2_get_timestamp(&buf->vb.ts);
|
2005-04-17 06:20:36 +08:00
|
|
|
dprintk(2,"[%p/%d] wakeup reg=%d buf=%d\n",buf,buf->vb.i,
|
|
|
|
|
count, buf->count);
|
2007-11-07 07:02:36 +08:00
|
|
|
buf->vb.state = VIDEOBUF_DONE;
|
2005-04-17 06:20:36 +08:00
|
|
|
list_del(&buf->vb.queue);
|
|
|
|
|
wake_up(&buf->vb.done);
|
|
|
|
|
}
|
|
|
|
|
if (list_empty(&q->active)) {
|
|
|
|
|
del_timer(&q->timeout);
|
|
|
|
|
} else {
|
|
|
|
|
mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
|
|
|
|
|
}
|
|
|
|
|
if (bc != 1)
|
2008-10-17 07:30:45 +08:00
|
|
|
dprintk(2, "%s: %d buffers handled (should be 1)\n",
|
|
|
|
|
__func__, bc);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void cx88_shutdown(struct cx88_core *core)
|
|
|
|
|
{
|
|
|
|
|
/* disable RISC controller + IRQs */
|
|
|
|
|
cx_write(MO_DEV_CNTRL2, 0);
|
|
|
|
|
|
|
|
|
|
/* stop dma transfers */
|
|
|
|
|
cx_write(MO_VID_DMACNTRL, 0x0);
|
|
|
|
|
cx_write(MO_AUD_DMACNTRL, 0x0);
|
|
|
|
|
cx_write(MO_TS_DMACNTRL, 0x0);
|
|
|
|
|
cx_write(MO_VIP_DMACNTRL, 0x0);
|
|
|
|
|
cx_write(MO_GPHST_DMACNTRL, 0x0);
|
|
|
|
|
|
|
|
|
|
/* stop interrupts */
|
|
|
|
|
cx_write(MO_PCI_INTMSK, 0x0);
|
|
|
|
|
cx_write(MO_VID_INTMSK, 0x0);
|
|
|
|
|
cx_write(MO_AUD_INTMSK, 0x0);
|
|
|
|
|
cx_write(MO_TS_INTMSK, 0x0);
|
|
|
|
|
cx_write(MO_VIP_INTMSK, 0x0);
|
|
|
|
|
cx_write(MO_GPHST_INTMSK, 0x0);
|
|
|
|
|
|
|
|
|
|
/* stop capturing */
|
|
|
|
|
cx_write(VID_CAPTURE_CONTROL, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int cx88_reset(struct cx88_core *core)
|
|
|
|
|
{
|
2008-04-09 10:20:00 +08:00
|
|
|
dprintk(1,"%s\n",__func__);
|
2005-04-17 06:20:36 +08:00
|
|
|
cx88_shutdown(core);
|
|
|
|
|
|
|
|
|
|
/* clear irq status */
|
|
|
|
|
cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int
|
|
|
|
|
cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int
|
|
|
|
|
cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int
|
|
|
|
|
|
|
|
|
|
/* wait a bit */
|
|
|
|
|
msleep(100);
|
|
|
|
|
|
|
|
|
|
/* init sram */
|
|
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], 720*4, 0);
|
|
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH22], 128, 0);
|
|
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH23], 128, 0);
|
|
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH24], 128, 0);
|
|
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], 128, 0);
|
|
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], 128, 0);
|
|
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28], 188*4, 0);
|
2009-04-01 06:01:51 +08:00
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], 128, 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/* misc init ... */
|
|
|
|
|
cx_write(MO_INPUT_FORMAT, ((1 << 13) | // agc enable
|
|
|
|
|
(1 << 12) | // agc gain
|
|
|
|
|
(1 << 11) | // adaptibe agc
|
|
|
|
|
(0 << 10) | // chroma agc
|
|
|
|
|
(0 << 9) | // ckillen
|
|
|
|
|
(7)));
|
|
|
|
|
|
|
|
|
|
/* setup image format */
|
|
|
|
|
cx_andor(MO_COLOR_CTRL, 0x4000, 0x4000);
|
|
|
|
|
|
tree-wide: fix assorted typos all over the place
That is "success", "unknown", "through", "performance", "[re|un]mapping"
, "access", "default", "reasonable", "[con]currently", "temperature"
, "channel", "[un]used", "application", "example","hierarchy", "therefore"
, "[over|under]flow", "contiguous", "threshold", "enough" and others.
Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2009-11-14 23:09:05 +08:00
|
|
|
/* setup FIFO Thresholds */
|
2005-04-17 06:20:36 +08:00
|
|
|
cx_write(MO_PDMA_STHRSH, 0x0807);
|
|
|
|
|
cx_write(MO_PDMA_DTHRSH, 0x0807);
|
|
|
|
|
|
|
|
|
|
/* fixes flashing of image */
|
|
|
|
|
cx_write(MO_AGC_SYNC_TIP1, 0x0380000F);
|
|
|
|
|
cx_write(MO_AGC_BACK_VBI, 0x00E00555);
|
|
|
|
|
|
|
|
|
|
cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int
|
|
|
|
|
cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int
|
|
|
|
|
cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int
|
|
|
|
|
|
|
|
|
|
/* Reset on-board parts */
|
|
|
|
|
cx_write(MO_SRST_IO, 0);
|
|
|
|
|
msleep(10);
|
|
|
|
|
cx_write(MO_SRST_IO, 1);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------ */
|
|
|
|
|
|
2012-10-28 02:18:16 +08:00
|
|
|
static inline unsigned int norm_swidth(v4l2_std_id norm)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2007-01-21 00:58:33 +08:00
|
|
|
return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2012-10-28 02:18:16 +08:00
|
|
|
static inline unsigned int norm_hdelay(v4l2_std_id norm)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2007-01-21 00:58:33 +08:00
|
|
|
return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 135 : 186;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2012-10-28 02:18:16 +08:00
|
|
|
static inline unsigned int norm_vdelay(v4l2_std_id norm)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2007-01-21 00:58:33 +08:00
|
|
|
return (norm & V4L2_STD_625_50) ? 0x24 : 0x18;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2012-10-28 02:18:16 +08:00
|
|
|
static inline unsigned int norm_fsc8(v4l2_std_id norm)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2007-01-21 00:58:33 +08:00
|
|
|
if (norm & V4L2_STD_PAL_M)
|
2006-12-18 10:30:47 +08:00
|
|
|
return 28604892; // 3.575611 MHz
|
|
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
if (norm & (V4L2_STD_PAL_Nc))
|
2006-12-18 10:30:47 +08:00
|
|
|
return 28656448; // 3.582056 MHz
|
|
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
if (norm & V4L2_STD_NTSC) // All NTSC/M and variants
|
2006-12-18 10:30:47 +08:00
|
|
|
return 28636360; // 3.57954545 MHz +/- 10 Hz
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-12-18 10:30:47 +08:00
|
|
|
/* SECAM have also different sub carrier for chroma,
|
|
|
|
|
but step_db and step_dr, at cx88_set_tvnorm already handles that.
|
|
|
|
|
|
|
|
|
|
The same FSC applies to PAL/BGDKIH, PAL/60, NTSC/4.43 and PAL/N
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
return 35468950; // 4.43361875 MHz +/- 5 Hz
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2012-10-28 02:18:16 +08:00
|
|
|
static inline unsigned int norm_htotal(v4l2_std_id norm)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2005-06-24 13:04:50 +08:00
|
|
|
|
2006-12-18 10:30:47 +08:00
|
|
|
unsigned int fsc4=norm_fsc8(norm)/2;
|
2005-06-24 13:04:50 +08:00
|
|
|
|
2006-12-18 10:30:47 +08:00
|
|
|
/* returns 4*FSC / vtotal / frames per seconds */
|
2007-01-21 00:58:33 +08:00
|
|
|
return (norm & V4L2_STD_625_50) ?
|
2006-12-18 10:30:47 +08:00
|
|
|
((fsc4+312)/625+12)/25 :
|
|
|
|
|
((fsc4+262)/525*1001+15000)/30000;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2012-10-28 02:18:16 +08:00
|
|
|
static inline unsigned int norm_vbipack(v4l2_std_id norm)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2007-01-21 00:58:33 +08:00
|
|
|
return (norm & V4L2_STD_625_50) ? 511 : 400;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int cx88_set_scale(struct cx88_core *core, unsigned int width, unsigned int height,
|
|
|
|
|
enum v4l2_field field)
|
|
|
|
|
{
|
|
|
|
|
unsigned int swidth = norm_swidth(core->tvnorm);
|
|
|
|
|
unsigned int sheight = norm_maxh(core->tvnorm);
|
|
|
|
|
u32 value;
|
|
|
|
|
|
|
|
|
|
dprintk(1,"set_scale: %dx%d [%s%s,%s]\n", width, height,
|
|
|
|
|
V4L2_FIELD_HAS_TOP(field) ? "T" : "",
|
|
|
|
|
V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "",
|
2007-01-21 00:58:33 +08:00
|
|
|
v4l2_norm_to_name(core->tvnorm));
|
2005-04-17 06:20:36 +08:00
|
|
|
if (!V4L2_FIELD_HAS_BOTH(field))
|
|
|
|
|
height *= 2;
|
|
|
|
|
|
|
|
|
|
// recalc H delay and scale registers
|
|
|
|
|
value = (width * norm_hdelay(core->tvnorm)) / swidth;
|
|
|
|
|
value &= 0x3fe;
|
|
|
|
|
cx_write(MO_HDELAY_EVEN, value);
|
|
|
|
|
cx_write(MO_HDELAY_ODD, value);
|
2006-12-18 10:30:47 +08:00
|
|
|
dprintk(1,"set_scale: hdelay 0x%04x (width %d)\n", value,swidth);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
value = (swidth * 4096 / width) - 4096;
|
|
|
|
|
cx_write(MO_HSCALE_EVEN, value);
|
|
|
|
|
cx_write(MO_HSCALE_ODD, value);
|
|
|
|
|
dprintk(1,"set_scale: hscale 0x%04x\n", value);
|
|
|
|
|
|
|
|
|
|
cx_write(MO_HACTIVE_EVEN, width);
|
|
|
|
|
cx_write(MO_HACTIVE_ODD, width);
|
|
|
|
|
dprintk(1,"set_scale: hactive 0x%04x\n", width);
|
|
|
|
|
|
|
|
|
|
// recalc V scale Register (delay is constant)
|
|
|
|
|
cx_write(MO_VDELAY_EVEN, norm_vdelay(core->tvnorm));
|
|
|
|
|
cx_write(MO_VDELAY_ODD, norm_vdelay(core->tvnorm));
|
|
|
|
|
dprintk(1,"set_scale: vdelay 0x%04x\n", norm_vdelay(core->tvnorm));
|
|
|
|
|
|
|
|
|
|
value = (0x10000 - (sheight * 512 / height - 512)) & 0x1fff;
|
|
|
|
|
cx_write(MO_VSCALE_EVEN, value);
|
|
|
|
|
cx_write(MO_VSCALE_ODD, value);
|
|
|
|
|
dprintk(1,"set_scale: vscale 0x%04x\n", value);
|
|
|
|
|
|
|
|
|
|
cx_write(MO_VACTIVE_EVEN, sheight);
|
|
|
|
|
cx_write(MO_VACTIVE_ODD, sheight);
|
|
|
|
|
dprintk(1,"set_scale: vactive 0x%04x\n", sheight);
|
|
|
|
|
|
|
|
|
|
// setup filters
|
|
|
|
|
value = 0;
|
|
|
|
|
value |= (1 << 19); // CFILT (default)
|
2007-01-21 00:58:33 +08:00
|
|
|
if (core->tvnorm & V4L2_STD_SECAM) {
|
2005-04-17 06:20:36 +08:00
|
|
|
value |= (1 << 15);
|
|
|
|
|
value |= (1 << 16);
|
|
|
|
|
}
|
2007-08-16 01:41:57 +08:00
|
|
|
if (INPUT(core->input).type == CX88_VMUX_SVIDEO)
|
2005-04-17 06:20:36 +08:00
|
|
|
value |= (1 << 13) | (1 << 5);
|
|
|
|
|
if (V4L2_FIELD_INTERLACED == field)
|
|
|
|
|
value |= (1 << 3); // VINT (interlaced vertical scaling)
|
|
|
|
|
if (width < 385)
|
|
|
|
|
value |= (1 << 0); // 3-tap interpolation
|
|
|
|
|
if (width < 193)
|
|
|
|
|
value |= (1 << 1); // 5-tap interpolation
|
|
|
|
|
if (nocomb)
|
|
|
|
|
value |= (3 << 5); // disable comb filter
|
|
|
|
|
|
2011-07-11 22:02:19 +08:00
|
|
|
cx_andor(MO_FILTER_EVEN, 0x7ffc7f, value); /* preserve PEAKEN, PSEL */
|
|
|
|
|
cx_andor(MO_FILTER_ODD, 0x7ffc7f, value);
|
2005-04-17 06:20:36 +08:00
|
|
|
dprintk(1,"set_scale: filter 0x%04x\n", value);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const u32 xtal = 28636363;
|
|
|
|
|
|
|
|
|
|
static int set_pll(struct cx88_core *core, int prescale, u32 ofreq)
|
|
|
|
|
{
|
2010-08-25 20:50:20 +08:00
|
|
|
static const u32 pre[] = { 0, 0, 0, 3, 2, 1 };
|
2005-04-17 06:20:36 +08:00
|
|
|
u64 pll;
|
|
|
|
|
u32 reg;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
if (prescale < 2)
|
|
|
|
|
prescale = 2;
|
|
|
|
|
if (prescale > 5)
|
|
|
|
|
prescale = 5;
|
|
|
|
|
|
|
|
|
|
pll = ofreq * 8 * prescale * (u64)(1 << 20);
|
|
|
|
|
do_div(pll,xtal);
|
|
|
|
|
reg = (pll & 0x3ffffff) | (pre[prescale] << 26);
|
|
|
|
|
if (((reg >> 20) & 0x3f) < 14) {
|
|
|
|
|
printk("%s/0: pll out of range\n",core->name);
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dprintk(1,"set_pll: MO_PLL_REG 0x%08x [old=0x%08x,freq=%d]\n",
|
|
|
|
|
reg, cx_read(MO_PLL_REG), ofreq);
|
|
|
|
|
cx_write(MO_PLL_REG, reg);
|
|
|
|
|
for (i = 0; i < 100; i++) {
|
|
|
|
|
reg = cx_read(MO_DEVICE_STATUS);
|
|
|
|
|
if (reg & (1<<2)) {
|
|
|
|
|
dprintk(1,"pll locked [pre=%d,ofreq=%d]\n",
|
|
|
|
|
prescale,ofreq);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
dprintk(1,"pll not locked yet, waiting ...\n");
|
|
|
|
|
msleep(10);
|
|
|
|
|
}
|
|
|
|
|
dprintk(1,"pll NOT locked [pre=%d,ofreq=%d]\n",prescale,ofreq);
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
2005-12-01 16:51:34 +08:00
|
|
|
int cx88_start_audio_dma(struct cx88_core *core)
|
|
|
|
|
{
|
2006-02-06 19:15:14 +08:00
|
|
|
/* constant 128 made buzz in analog Nicam-stereo for bigger fifo_size */
|
|
|
|
|
int bpl = cx88_sram_channels[SRAM_CH25].fifo_size/4;
|
2006-08-18 05:40:28 +08:00
|
|
|
|
2009-04-01 06:01:51 +08:00
|
|
|
int rds_bpl = cx88_sram_channels[SRAM_CH27].fifo_size/AUD_RDS_LINES;
|
|
|
|
|
|
2006-08-18 05:40:28 +08:00
|
|
|
/* If downstream RISC is enabled, bail out; ALSA is managing DMA */
|
|
|
|
|
if (cx_read(MO_AUD_DMACNTRL) & 0x10)
|
|
|
|
|
return 0;
|
|
|
|
|
|
2005-12-01 16:51:34 +08:00
|
|
|
/* setup fifo + format */
|
2006-02-06 19:15:14 +08:00
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], bpl, 0);
|
|
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], bpl, 0);
|
2009-04-01 06:01:51 +08:00
|
|
|
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27],
|
|
|
|
|
rds_bpl, 0);
|
2005-12-01 16:51:34 +08:00
|
|
|
|
2006-02-06 19:15:14 +08:00
|
|
|
cx_write(MO_AUDD_LNGTH, bpl); /* fifo bpl size */
|
2009-04-01 06:01:51 +08:00
|
|
|
cx_write(MO_AUDR_LNGTH, rds_bpl); /* fifo bpl size */
|
2005-12-01 16:51:34 +08:00
|
|
|
|
2009-04-01 06:01:51 +08:00
|
|
|
/* enable Up, Down and Audio RDS fifo */
|
|
|
|
|
cx_write(MO_AUD_DMACNTRL, 0x0007);
|
2006-08-18 05:40:28 +08:00
|
|
|
|
2005-12-01 16:51:34 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int cx88_stop_audio_dma(struct cx88_core *core)
|
|
|
|
|
{
|
2006-08-18 05:40:28 +08:00
|
|
|
/* If downstream RISC is enabled, bail out; ALSA is managing DMA */
|
|
|
|
|
if (cx_read(MO_AUD_DMACNTRL) & 0x10)
|
|
|
|
|
return 0;
|
|
|
|
|
|
2005-12-01 16:51:34 +08:00
|
|
|
/* stop dma */
|
|
|
|
|
cx_write(MO_AUD_DMACNTRL, 0x0000);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static int set_tvaudio(struct cx88_core *core)
|
|
|
|
|
{
|
2007-01-21 00:58:33 +08:00
|
|
|
v4l2_std_id norm = core->tvnorm;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2010-03-27 20:31:32 +08:00
|
|
|
if (CX88_VMUX_TELEVISION != INPUT(core->input).type &&
|
|
|
|
|
CX88_VMUX_CABLE != INPUT(core->input).type)
|
2005-04-17 06:20:36 +08:00
|
|
|
return 0;
|
|
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
if (V4L2_STD_PAL_BG & norm) {
|
2005-11-09 13:36:27 +08:00
|
|
|
core->tvaudio = WW_BG;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (V4L2_STD_PAL_DK & norm) {
|
2005-11-09 13:36:27 +08:00
|
|
|
core->tvaudio = WW_DK;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (V4L2_STD_PAL_I & norm) {
|
2005-11-09 13:36:27 +08:00
|
|
|
core->tvaudio = WW_I;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (V4L2_STD_SECAM_L & norm) {
|
2005-11-09 13:36:27 +08:00
|
|
|
core->tvaudio = WW_L;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-10-30 15:53:07 +08:00
|
|
|
} else if ((V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H) & norm) {
|
|
|
|
|
core->tvaudio = WW_BG;
|
|
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (V4L2_STD_SECAM_DK & norm) {
|
2005-11-09 13:36:27 +08:00
|
|
|
core->tvaudio = WW_DK;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if ((V4L2_STD_NTSC_M & norm) ||
|
|
|
|
|
(V4L2_STD_PAL_M & norm)) {
|
2005-04-17 06:20:36 +08:00
|
|
|
core->tvaudio = WW_BTSC;
|
|
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (V4L2_STD_NTSC_M_JP & norm) {
|
2005-04-17 06:20:36 +08:00
|
|
|
core->tvaudio = WW_EIAJ;
|
|
|
|
|
|
|
|
|
|
} else {
|
|
|
|
|
printk("%s/0: tvaudio support needs work for this tv norm [%s], sorry\n",
|
2007-01-21 00:58:33 +08:00
|
|
|
core->name, v4l2_norm_to_name(core->tvnorm));
|
2010-08-23 18:49:58 +08:00
|
|
|
core->tvaudio = WW_NONE;
|
2005-04-17 06:20:36 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
cx_andor(MO_AFECFG_IO, 0x1f, 0x0);
|
|
|
|
|
cx88_set_tvaudio(core);
|
2005-09-10 04:03:41 +08:00
|
|
|
/* cx88_set_stereo(dev,V4L2_TUNER_MODE_STEREO); */
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-12-01 16:51:34 +08:00
|
|
|
/*
|
|
|
|
|
This should be needed only on cx88-alsa. It seems that some cx88 chips have
|
|
|
|
|
bugs and does require DMA enabled for it to work.
|
|
|
|
|
*/
|
|
|
|
|
cx88_start_audio_dma(core);
|
2005-04-17 06:20:36 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2005-12-01 16:51:34 +08:00
|
|
|
|
|
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
int cx88_set_tvnorm(struct cx88_core *core, v4l2_std_id norm)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
u32 fsc8;
|
|
|
|
|
u32 adc_clock;
|
|
|
|
|
u32 vdec_clock;
|
|
|
|
|
u32 step_db,step_dr;
|
|
|
|
|
u64 tmp64;
|
|
|
|
|
u32 bdelay,agcdelay,htotal;
|
2007-01-21 00:58:17 +08:00
|
|
|
u32 cxiformat, cxoformat;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
core->tvnorm = norm;
|
|
|
|
|
fsc8 = norm_fsc8(norm);
|
|
|
|
|
adc_clock = xtal;
|
|
|
|
|
vdec_clock = fsc8;
|
|
|
|
|
step_db = fsc8;
|
|
|
|
|
step_dr = fsc8;
|
|
|
|
|
|
2007-01-21 00:58:33 +08:00
|
|
|
if (norm & V4L2_STD_NTSC_M_JP) {
|
2007-01-21 00:58:17 +08:00
|
|
|
cxiformat = VideoFormatNTSCJapan;
|
|
|
|
|
cxoformat = 0x181f0008;
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (norm & V4L2_STD_NTSC_443) {
|
2007-01-21 00:58:20 +08:00
|
|
|
cxiformat = VideoFormatNTSC443;
|
|
|
|
|
cxoformat = 0x181f0008;
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (norm & V4L2_STD_PAL_M) {
|
2007-01-21 00:58:17 +08:00
|
|
|
cxiformat = VideoFormatPALM;
|
|
|
|
|
cxoformat = 0x1c1f0008;
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (norm & V4L2_STD_PAL_N) {
|
2007-01-21 00:58:17 +08:00
|
|
|
cxiformat = VideoFormatPALN;
|
|
|
|
|
cxoformat = 0x1c1f0008;
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (norm & V4L2_STD_PAL_Nc) {
|
2007-01-21 00:58:17 +08:00
|
|
|
cxiformat = VideoFormatPALNC;
|
|
|
|
|
cxoformat = 0x1c1f0008;
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (norm & V4L2_STD_PAL_60) {
|
2007-01-21 00:58:17 +08:00
|
|
|
cxiformat = VideoFormatPAL60;
|
|
|
|
|
cxoformat = 0x181f0008;
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (norm & V4L2_STD_NTSC) {
|
2007-01-21 00:58:17 +08:00
|
|
|
cxiformat = VideoFormatNTSC;
|
|
|
|
|
cxoformat = 0x181f0008;
|
2007-01-21 00:58:33 +08:00
|
|
|
} else if (norm & V4L2_STD_SECAM) {
|
2005-04-17 06:20:36 +08:00
|
|
|
step_db = 4250000 * 8;
|
|
|
|
|
step_dr = 4406250 * 8;
|
2007-01-21 00:58:20 +08:00
|
|
|
|
|
|
|
|
cxiformat = VideoFormatSECAM;
|
|
|
|
|
cxoformat = 0x181f0008;
|
2007-01-21 00:58:17 +08:00
|
|
|
} else { /* PAL */
|
|
|
|
|
cxiformat = VideoFormatPAL;
|
|
|
|
|
cxoformat = 0x181f0008;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dprintk(1,"set_tvnorm: \"%s\" fsc8=%d adc=%d vdec=%d db/dr=%d/%d\n",
|
2007-01-21 00:58:33 +08:00
|
|
|
v4l2_norm_to_name(core->tvnorm), fsc8, adc_clock, vdec_clock,
|
|
|
|
|
step_db, step_dr);
|
2005-04-17 06:20:36 +08:00
|
|
|
set_pll(core,2,vdec_clock);
|
|
|
|
|
|
|
|
|
|
dprintk(1,"set_tvnorm: MO_INPUT_FORMAT 0x%08x [old=0x%08x]\n",
|
2007-01-21 00:58:17 +08:00
|
|
|
cxiformat, cx_read(MO_INPUT_FORMAT) & 0x0f);
|
2008-03-24 09:43:22 +08:00
|
|
|
/* Chroma AGC must be disabled if SECAM is used, we enable it
|
|
|
|
|
by default on PAL and NTSC */
|
|
|
|
|
cx_andor(MO_INPUT_FORMAT, 0x40f,
|
|
|
|
|
norm & V4L2_STD_SECAM ? cxiformat : cxiformat | 0x400);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
// FIXME: as-is from DScaler
|
|
|
|
|
dprintk(1,"set_tvnorm: MO_OUTPUT_FORMAT 0x%08x [old=0x%08x]\n",
|
2007-01-21 00:58:17 +08:00
|
|
|
cxoformat, cx_read(MO_OUTPUT_FORMAT));
|
|
|
|
|
cx_write(MO_OUTPUT_FORMAT, cxoformat);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
// MO_SCONV_REG = adc clock / video dec clock * 2^17
|
|
|
|
|
tmp64 = adc_clock * (u64)(1 << 17);
|
|
|
|
|
do_div(tmp64, vdec_clock);
|
|
|
|
|
dprintk(1,"set_tvnorm: MO_SCONV_REG 0x%08x [old=0x%08x]\n",
|
|
|
|
|
(u32)tmp64, cx_read(MO_SCONV_REG));
|
|
|
|
|
cx_write(MO_SCONV_REG, (u32)tmp64);
|
|
|
|
|
|
|
|
|
|
// MO_SUB_STEP = 8 * fsc / video dec clock * 2^22
|
|
|
|
|
tmp64 = step_db * (u64)(1 << 22);
|
|
|
|
|
do_div(tmp64, vdec_clock);
|
|
|
|
|
dprintk(1,"set_tvnorm: MO_SUB_STEP 0x%08x [old=0x%08x]\n",
|
|
|
|
|
(u32)tmp64, cx_read(MO_SUB_STEP));
|
|
|
|
|
cx_write(MO_SUB_STEP, (u32)tmp64);
|
|
|
|
|
|
|
|
|
|
// MO_SUB_STEP_DR = 8 * 4406250 / video dec clock * 2^22
|
|
|
|
|
tmp64 = step_dr * (u64)(1 << 22);
|
|
|
|
|
do_div(tmp64, vdec_clock);
|
|
|
|
|
dprintk(1,"set_tvnorm: MO_SUB_STEP_DR 0x%08x [old=0x%08x]\n",
|
|
|
|
|
(u32)tmp64, cx_read(MO_SUB_STEP_DR));
|
|
|
|
|
cx_write(MO_SUB_STEP_DR, (u32)tmp64);
|
|
|
|
|
|
|
|
|
|
// bdelay + agcdelay
|
|
|
|
|
bdelay = vdec_clock * 65 / 20000000 + 21;
|
|
|
|
|
agcdelay = vdec_clock * 68 / 20000000 + 15;
|
|
|
|
|
dprintk(1,"set_tvnorm: MO_AGC_BURST 0x%08x [old=0x%08x,bdelay=%d,agcdelay=%d]\n",
|
|
|
|
|
(bdelay << 8) | agcdelay, cx_read(MO_AGC_BURST), bdelay, agcdelay);
|
|
|
|
|
cx_write(MO_AGC_BURST, (bdelay << 8) | agcdelay);
|
|
|
|
|
|
|
|
|
|
// htotal
|
|
|
|
|
tmp64 = norm_htotal(norm) * (u64)vdec_clock;
|
|
|
|
|
do_div(tmp64, fsc8);
|
2011-07-11 22:07:43 +08:00
|
|
|
htotal = (u32)tmp64;
|
2005-04-17 06:20:36 +08:00
|
|
|
dprintk(1,"set_tvnorm: MO_HTOTAL 0x%08x [old=0x%08x,htotal=%d]\n",
|
|
|
|
|
htotal, cx_read(MO_HTOTAL), (u32)tmp64);
|
2011-07-11 22:07:43 +08:00
|
|
|
cx_andor(MO_HTOTAL, 0x07ff, htotal);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-05-24 10:54:44 +08:00
|
|
|
// vbi stuff, set vbi offset to 10 (for 20 Clk*2 pixels), this makes
|
|
|
|
|
// the effective vbi offset ~244 samples, the same as the Bt8x8
|
|
|
|
|
cx_write(MO_VBI_PACKET, (10<<11) | norm_vbipack(norm));
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
// this is needed as well to set all tvnorm parameter
|
|
|
|
|
cx88_set_scale(core, 320, 240, V4L2_FIELD_INTERLACED);
|
|
|
|
|
|
|
|
|
|
// audio
|
|
|
|
|
set_tvaudio(core);
|
|
|
|
|
|
|
|
|
|
// tell i2c chips
|
2009-04-01 14:52:39 +08:00
|
|
|
call_all(core, core, s_std, norm);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2012-05-11 20:07:45 +08:00
|
|
|
/* The chroma_agc control should be inaccessible if the video format is SECAM */
|
|
|
|
|
v4l2_ctrl_grab(core->chroma_agc, cxiformat == VideoFormatSECAM);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
// done
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------ */
|
|
|
|
|
|
|
|
|
|
struct video_device *cx88_vdev_init(struct cx88_core *core,
|
|
|
|
|
struct pci_dev *pci,
|
2010-08-25 20:50:20 +08:00
|
|
|
const struct video_device *template_,
|
|
|
|
|
const char *type)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
struct video_device *vfd;
|
|
|
|
|
|
|
|
|
|
vfd = video_device_alloc();
|
|
|
|
|
if (NULL == vfd)
|
|
|
|
|
return NULL;
|
2010-08-25 20:50:20 +08:00
|
|
|
*vfd = *template_;
|
2009-03-14 23:40:51 +08:00
|
|
|
vfd->v4l2_dev = &core->v4l2_dev;
|
2005-04-17 06:20:36 +08:00
|
|
|
vfd->release = video_device_release;
|
|
|
|
|
snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)",
|
2007-08-16 01:41:57 +08:00
|
|
|
core->name, type, core->board.name);
|
2012-05-11 21:57:59 +08:00
|
|
|
set_bit(V4L2_FL_USE_FH_PRIO, &vfd->flags);
|
2005-04-17 06:20:36 +08:00
|
|
|
return vfd;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
struct cx88_core* cx88_core_get(struct pci_dev *pci)
|
|
|
|
|
{
|
|
|
|
|
struct cx88_core *core;
|
|
|
|
|
|
2006-01-15 17:52:23 +08:00
|
|
|
mutex_lock(&devlist);
|
2007-10-10 16:37:40 +08:00
|
|
|
list_for_each_entry(core, &cx88_devlist, devlist) {
|
2005-04-17 06:20:36 +08:00
|
|
|
if (pci->bus->number != core->pci_bus)
|
|
|
|
|
continue;
|
|
|
|
|
if (PCI_SLOT(pci->devfn) != core->pci_slot)
|
|
|
|
|
continue;
|
|
|
|
|
|
2007-08-16 01:41:58 +08:00
|
|
|
if (0 != cx88_get_resources(core, pci)) {
|
|
|
|
|
mutex_unlock(&devlist);
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
atomic_inc(&core->refcount);
|
2006-01-15 17:52:23 +08:00
|
|
|
mutex_unlock(&devlist);
|
2005-04-17 06:20:36 +08:00
|
|
|
return core;
|
|
|
|
|
}
|
2005-06-24 13:05:03 +08:00
|
|
|
|
2007-08-16 01:41:58 +08:00
|
|
|
core = cx88_core_create(pci, cx88_devcount);
|
|
|
|
|
if (NULL != core) {
|
|
|
|
|
cx88_devcount++;
|
|
|
|
|
list_add_tail(&core->devlist, &cx88_devlist);
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-01-15 17:52:23 +08:00
|
|
|
mutex_unlock(&devlist);
|
2005-04-17 06:20:36 +08:00
|
|
|
return core;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void cx88_core_put(struct cx88_core *core, struct pci_dev *pci)
|
|
|
|
|
{
|
|
|
|
|
release_mem_region(pci_resource_start(pci,0),
|
|
|
|
|
pci_resource_len(pci,0));
|
|
|
|
|
|
|
|
|
|
if (!atomic_dec_and_test(&core->refcount))
|
|
|
|
|
return;
|
|
|
|
|
|
2006-01-15 17:52:23 +08:00
|
|
|
mutex_lock(&devlist);
|
2005-04-17 06:20:36 +08:00
|
|
|
cx88_ir_fini(core);
|
2009-03-29 19:26:01 +08:00
|
|
|
if (0 == core->i2c_rc) {
|
|
|
|
|
if (core->i2c_rtc)
|
|
|
|
|
i2c_unregister_device(core->i2c_rtc);
|
2006-12-11 04:21:33 +08:00
|
|
|
i2c_del_adapter(&core->i2c_adap);
|
2009-03-29 19:26:01 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
list_del(&core->devlist);
|
|
|
|
|
iounmap(core->lmmio);
|
|
|
|
|
cx88_devcount--;
|
2006-01-15 17:52:23 +08:00
|
|
|
mutex_unlock(&devlist);
|
2012-05-11 20:07:45 +08:00
|
|
|
v4l2_ctrl_handler_free(&core->video_hdl);
|
|
|
|
|
v4l2_ctrl_handler_free(&core->audio_hdl);
|
2009-03-14 23:40:51 +08:00
|
|
|
v4l2_device_unregister(&core->v4l2_dev);
|
2005-04-17 06:20:36 +08:00
|
|
|
kfree(core);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------ */
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EXPORT_SYMBOL(cx88_print_irqbits);
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EXPORT_SYMBOL(cx88_core_irq);
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EXPORT_SYMBOL(cx88_wakeup);
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EXPORT_SYMBOL(cx88_reset);
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EXPORT_SYMBOL(cx88_shutdown);
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EXPORT_SYMBOL(cx88_risc_buffer);
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EXPORT_SYMBOL(cx88_risc_databuffer);
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EXPORT_SYMBOL(cx88_risc_stopper);
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EXPORT_SYMBOL(cx88_free_buffer);
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EXPORT_SYMBOL(cx88_sram_channels);
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EXPORT_SYMBOL(cx88_sram_channel_setup);
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EXPORT_SYMBOL(cx88_sram_channel_dump);
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EXPORT_SYMBOL(cx88_set_tvnorm);
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EXPORT_SYMBOL(cx88_set_scale);
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EXPORT_SYMBOL(cx88_vdev_init);
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EXPORT_SYMBOL(cx88_core_get);
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EXPORT_SYMBOL(cx88_core_put);
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2007-10-01 19:51:39 +08:00
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EXPORT_SYMBOL(cx88_ir_start);
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EXPORT_SYMBOL(cx88_ir_stop);
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2005-04-17 06:20:36 +08:00
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/*
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* Local variables:
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* c-basic-offset: 8
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* End:
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2005-09-10 04:03:41 +08:00
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* kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
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2005-04-17 06:20:36 +08:00
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*/
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