2005-04-17 06:20:36 +08:00
|
|
|
/*
|
2007-07-12 02:04:50 +08:00
|
|
|
* linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
|
2005-04-17 06:20:36 +08:00
|
|
|
*
|
|
|
|
|
* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
|
ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij.
Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface. The changes over Linus' driver are:
- rename txsize_threshold to dmasize_threshold, as this reflects the
purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer. Some DMA controllers
(eg, PL08x) are unable to be configured for scatter DMA and also listen
to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the
final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
its own restrictions on buffer alignment, not the individual DMA engine
users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
causes LBREQ to be asserted for the last seven transfers, rather than
six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
transfer size required to complete the DMA operation.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-12 03:35:53 +08:00
|
|
|
* Copyright (C) 2010 ST-Ericsson SA
|
2005-04-17 06:20:36 +08:00
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
|
*/
|
|
|
|
|
#include <linux/module.h>
|
|
|
|
|
#include <linux/moduleparam.h>
|
|
|
|
|
#include <linux/init.h>
|
|
|
|
|
#include <linux/ioport.h>
|
|
|
|
|
#include <linux/device.h>
|
|
|
|
|
#include <linux/interrupt.h>
|
2011-01-31 05:06:53 +08:00
|
|
|
#include <linux/kernel.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <linux/delay.h>
|
|
|
|
|
#include <linux/err.h>
|
|
|
|
|
#include <linux/highmem.h>
|
2007-10-11 13:06:03 +08:00
|
|
|
#include <linux/log2.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <linux/mmc/host.h>
|
2010-10-19 19:43:58 +08:00
|
|
|
#include <linux/mmc/card.h>
|
2006-01-07 21:52:45 +08:00
|
|
|
#include <linux/amba/bus.h>
|
2006-01-08 00:15:52 +08:00
|
|
|
#include <linux/clk.h>
|
2007-10-24 15:01:09 +08:00
|
|
|
#include <linux/scatterlist.h>
|
2009-07-09 22:16:07 +08:00
|
|
|
#include <linux/gpio.h>
|
2009-09-22 21:41:40 +08:00
|
|
|
#include <linux/regulator/consumer.h>
|
ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij.
Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface. The changes over Linus' driver are:
- rename txsize_threshold to dmasize_threshold, as this reflects the
purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer. Some DMA controllers
(eg, PL08x) are unable to be configured for scatter DMA and also listen
to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the
final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
its own restrictions on buffer alignment, not the individual DMA engine
users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
causes LBREQ to be asserted for the last seven transfers, rather than
six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
transfer size required to complete the DMA operation.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-12 03:35:53 +08:00
|
|
|
#include <linux/dmaengine.h>
|
|
|
|
|
#include <linux/dma-mapping.h>
|
|
|
|
|
#include <linux/amba/mmci.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-07-01 19:02:59 +08:00
|
|
|
#include <asm/div64.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <asm/io.h>
|
2005-10-28 21:05:16 +08:00
|
|
|
#include <asm/sizes.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
#include "mmci.h"
|
|
|
|
|
|
|
|
|
|
#define DRIVER_NAME "mmci-pl18x"
|
|
|
|
|
|
|
|
|
|
static unsigned int fmax = 515633;
|
|
|
|
|
|
2010-07-21 19:54:40 +08:00
|
|
|
/**
|
|
|
|
|
* struct variant_data - MMCI variant-specific quirks
|
|
|
|
|
* @clkreg: default value for MCICLOCK register
|
2010-07-21 19:55:18 +08:00
|
|
|
* @clkreg_enable: enable value for MMCICLOCK register
|
2010-07-21 19:55:59 +08:00
|
|
|
* @datalength_bits: number of bits in the MMCIDATALENGTH register
|
2010-08-09 19:57:30 +08:00
|
|
|
* @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
|
|
|
|
|
* is asserted (likewise for RX)
|
|
|
|
|
* @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
|
|
|
|
|
* is asserted (likewise for RX)
|
2010-10-19 19:43:58 +08:00
|
|
|
* @sdio: variant supports SDIO
|
2010-12-06 16:24:14 +08:00
|
|
|
* @st_clkdiv: true if using a ST-specific clock divider algorithm
|
2010-07-21 19:54:40 +08:00
|
|
|
*/
|
|
|
|
|
struct variant_data {
|
|
|
|
|
unsigned int clkreg;
|
2010-07-21 19:55:18 +08:00
|
|
|
unsigned int clkreg_enable;
|
2010-07-21 19:55:59 +08:00
|
|
|
unsigned int datalength_bits;
|
2010-08-09 19:57:30 +08:00
|
|
|
unsigned int fifosize;
|
|
|
|
|
unsigned int fifohalfsize;
|
2010-10-19 19:43:58 +08:00
|
|
|
bool sdio;
|
2010-12-06 16:24:14 +08:00
|
|
|
bool st_clkdiv;
|
2010-07-21 19:54:40 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct variant_data variant_arm = {
|
2010-08-09 19:57:30 +08:00
|
|
|
.fifosize = 16 * 4,
|
|
|
|
|
.fifohalfsize = 8 * 4,
|
2010-07-21 19:55:59 +08:00
|
|
|
.datalength_bits = 16,
|
2010-07-21 19:54:40 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct variant_data variant_u300 = {
|
2010-08-09 19:57:30 +08:00
|
|
|
.fifosize = 16 * 4,
|
|
|
|
|
.fifohalfsize = 8 * 4,
|
2010-07-21 19:55:18 +08:00
|
|
|
.clkreg_enable = 1 << 13, /* HWFCEN */
|
2010-07-21 19:55:59 +08:00
|
|
|
.datalength_bits = 16,
|
2010-10-19 19:43:58 +08:00
|
|
|
.sdio = true,
|
2010-07-21 19:54:40 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct variant_data variant_ux500 = {
|
2010-08-09 19:57:30 +08:00
|
|
|
.fifosize = 30 * 4,
|
|
|
|
|
.fifohalfsize = 8 * 4,
|
2010-07-21 19:54:40 +08:00
|
|
|
.clkreg = MCI_CLK_ENABLE,
|
2010-07-21 19:55:18 +08:00
|
|
|
.clkreg_enable = 1 << 14, /* HWFCEN */
|
2010-07-21 19:55:59 +08:00
|
|
|
.datalength_bits = 24,
|
2010-10-19 19:43:58 +08:00
|
|
|
.sdio = true,
|
2010-12-06 16:24:14 +08:00
|
|
|
.st_clkdiv = true,
|
2010-07-21 19:54:40 +08:00
|
|
|
};
|
2010-12-06 16:24:14 +08:00
|
|
|
|
2009-09-14 19:56:14 +08:00
|
|
|
/*
|
|
|
|
|
* This must be called with host->lock held
|
|
|
|
|
*/
|
|
|
|
|
static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
|
|
|
|
|
{
|
2010-07-21 19:54:40 +08:00
|
|
|
struct variant_data *variant = host->variant;
|
|
|
|
|
u32 clk = variant->clkreg;
|
2009-09-14 19:56:14 +08:00
|
|
|
|
|
|
|
|
if (desired) {
|
|
|
|
|
if (desired >= host->mclk) {
|
2010-12-10 16:35:53 +08:00
|
|
|
clk = MCI_CLK_BYPASS;
|
2009-09-14 19:56:14 +08:00
|
|
|
host->cclk = host->mclk;
|
2010-12-06 16:24:14 +08:00
|
|
|
} else if (variant->st_clkdiv) {
|
|
|
|
|
/*
|
|
|
|
|
* DB8500 TRM says f = mclk / (clkdiv + 2)
|
|
|
|
|
* => clkdiv = (mclk / f) - 2
|
|
|
|
|
* Round the divider up so we don't exceed the max
|
|
|
|
|
* frequency
|
|
|
|
|
*/
|
|
|
|
|
clk = DIV_ROUND_UP(host->mclk, desired) - 2;
|
|
|
|
|
if (clk >= 256)
|
|
|
|
|
clk = 255;
|
|
|
|
|
host->cclk = host->mclk / (clk + 2);
|
2009-09-14 19:56:14 +08:00
|
|
|
} else {
|
2010-12-06 16:24:14 +08:00
|
|
|
/*
|
|
|
|
|
* PL180 TRM says f = mclk / (2 * (clkdiv + 1))
|
|
|
|
|
* => clkdiv = mclk / (2 * f) - 1
|
|
|
|
|
*/
|
2009-09-14 19:56:14 +08:00
|
|
|
clk = host->mclk / (2 * desired) - 1;
|
|
|
|
|
if (clk >= 256)
|
|
|
|
|
clk = 255;
|
|
|
|
|
host->cclk = host->mclk / (2 * (clk + 1));
|
|
|
|
|
}
|
2010-07-21 19:55:18 +08:00
|
|
|
|
|
|
|
|
clk |= variant->clkreg_enable;
|
2009-09-14 19:56:14 +08:00
|
|
|
clk |= MCI_CLK_ENABLE;
|
|
|
|
|
/* This hasn't proven to be worthwhile */
|
|
|
|
|
/* clk |= MCI_CLK_PWRSAVE; */
|
|
|
|
|
}
|
|
|
|
|
|
2009-09-14 19:57:11 +08:00
|
|
|
if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
|
2010-04-08 14:38:52 +08:00
|
|
|
clk |= MCI_4BIT_BUS;
|
|
|
|
|
if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
|
|
|
|
|
clk |= MCI_ST_8BIT_BUS;
|
2009-09-14 19:57:11 +08:00
|
|
|
|
2009-09-14 19:56:14 +08:00
|
|
|
writel(clk, host->base + MMCICLOCK);
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static void
|
|
|
|
|
mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
|
|
|
|
|
{
|
|
|
|
|
writel(0, host->base + MMCICOMMAND);
|
|
|
|
|
|
2007-01-09 00:42:51 +08:00
|
|
|
BUG_ON(host->data);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
host->mrq = NULL;
|
|
|
|
|
host->cmd = NULL;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Need to drop the host lock here; mmc_request_done may call
|
|
|
|
|
* back into the driver...
|
|
|
|
|
*/
|
|
|
|
|
spin_unlock(&host->lock);
|
|
|
|
|
mmc_request_done(host->mmc, mrq);
|
|
|
|
|
spin_lock(&host->lock);
|
|
|
|
|
}
|
|
|
|
|
|
2010-10-19 19:39:48 +08:00
|
|
|
static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
|
|
|
|
|
{
|
|
|
|
|
void __iomem *base = host->base;
|
|
|
|
|
|
|
|
|
|
if (host->singleirq) {
|
|
|
|
|
unsigned int mask0 = readl(base + MMCIMASK0);
|
|
|
|
|
|
|
|
|
|
mask0 &= ~MCI_IRQ1MASK;
|
|
|
|
|
mask0 |= mask;
|
|
|
|
|
|
|
|
|
|
writel(mask0, base + MMCIMASK0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
writel(mask, base + MMCIMASK1);
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static void mmci_stop_data(struct mmci_host *host)
|
|
|
|
|
{
|
|
|
|
|
writel(0, host->base + MMCIDATACTRL);
|
2010-10-19 19:39:48 +08:00
|
|
|
mmci_set_mask1(host, 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
host->data = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2010-07-21 19:44:58 +08:00
|
|
|
static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
|
|
|
|
|
{
|
|
|
|
|
unsigned int flags = SG_MITER_ATOMIC;
|
|
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
|
|
|
flags |= SG_MITER_TO_SG;
|
|
|
|
|
else
|
|
|
|
|
flags |= SG_MITER_FROM_SG;
|
|
|
|
|
|
|
|
|
|
sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
|
|
|
|
|
}
|
|
|
|
|
|
ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij.
Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface. The changes over Linus' driver are:
- rename txsize_threshold to dmasize_threshold, as this reflects the
purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer. Some DMA controllers
(eg, PL08x) are unable to be configured for scatter DMA and also listen
to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the
final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
its own restrictions on buffer alignment, not the individual DMA engine
users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
causes LBREQ to be asserted for the last seven transfers, rather than
six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
transfer size required to complete the DMA operation.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-12 03:35:53 +08:00
|
|
|
/*
|
|
|
|
|
* All the DMA operation mode stuff goes inside this ifdef.
|
|
|
|
|
* This assumes that you have a generic DMA device interface,
|
|
|
|
|
* no custom DMA interfaces are supported.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
|
|
|
|
static void __devinit mmci_dma_setup(struct mmci_host *host)
|
|
|
|
|
{
|
|
|
|
|
struct mmci_platform_data *plat = host->plat;
|
|
|
|
|
const char *rxname, *txname;
|
|
|
|
|
dma_cap_mask_t mask;
|
|
|
|
|
|
|
|
|
|
if (!plat || !plat->dma_filter) {
|
|
|
|
|
dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Try to acquire a generic DMA engine slave channel */
|
|
|
|
|
dma_cap_zero(mask);
|
|
|
|
|
dma_cap_set(DMA_SLAVE, mask);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If only an RX channel is specified, the driver will
|
|
|
|
|
* attempt to use it bidirectionally, however if it is
|
|
|
|
|
* is specified but cannot be located, DMA will be disabled.
|
|
|
|
|
*/
|
|
|
|
|
if (plat->dma_rx_param) {
|
|
|
|
|
host->dma_rx_channel = dma_request_channel(mask,
|
|
|
|
|
plat->dma_filter,
|
|
|
|
|
plat->dma_rx_param);
|
|
|
|
|
/* E.g if no DMA hardware is present */
|
|
|
|
|
if (!host->dma_rx_channel)
|
|
|
|
|
dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (plat->dma_tx_param) {
|
|
|
|
|
host->dma_tx_channel = dma_request_channel(mask,
|
|
|
|
|
plat->dma_filter,
|
|
|
|
|
plat->dma_tx_param);
|
|
|
|
|
if (!host->dma_tx_channel)
|
|
|
|
|
dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
|
|
|
|
|
} else {
|
|
|
|
|
host->dma_tx_channel = host->dma_rx_channel;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (host->dma_rx_channel)
|
|
|
|
|
rxname = dma_chan_name(host->dma_rx_channel);
|
|
|
|
|
else
|
|
|
|
|
rxname = "none";
|
|
|
|
|
|
|
|
|
|
if (host->dma_tx_channel)
|
|
|
|
|
txname = dma_chan_name(host->dma_tx_channel);
|
|
|
|
|
else
|
|
|
|
|
txname = "none";
|
|
|
|
|
|
|
|
|
|
dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
|
|
|
|
|
rxname, txname);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Limit the maximum segment size in any SG entry according to
|
|
|
|
|
* the parameters of the DMA engine device.
|
|
|
|
|
*/
|
|
|
|
|
if (host->dma_tx_channel) {
|
|
|
|
|
struct device *dev = host->dma_tx_channel->device->dev;
|
|
|
|
|
unsigned int max_seg_size = dma_get_max_seg_size(dev);
|
|
|
|
|
|
|
|
|
|
if (max_seg_size < host->mmc->max_seg_size)
|
|
|
|
|
host->mmc->max_seg_size = max_seg_size;
|
|
|
|
|
}
|
|
|
|
|
if (host->dma_rx_channel) {
|
|
|
|
|
struct device *dev = host->dma_rx_channel->device->dev;
|
|
|
|
|
unsigned int max_seg_size = dma_get_max_seg_size(dev);
|
|
|
|
|
|
|
|
|
|
if (max_seg_size < host->mmc->max_seg_size)
|
|
|
|
|
host->mmc->max_seg_size = max_seg_size;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This is used in __devinit or __devexit so inline it
|
|
|
|
|
* so it can be discarded.
|
|
|
|
|
*/
|
|
|
|
|
static inline void mmci_dma_release(struct mmci_host *host)
|
|
|
|
|
{
|
|
|
|
|
struct mmci_platform_data *plat = host->plat;
|
|
|
|
|
|
|
|
|
|
if (host->dma_rx_channel)
|
|
|
|
|
dma_release_channel(host->dma_rx_channel);
|
|
|
|
|
if (host->dma_tx_channel && plat->dma_tx_param)
|
|
|
|
|
dma_release_channel(host->dma_tx_channel);
|
|
|
|
|
host->dma_rx_channel = host->dma_tx_channel = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
|
|
|
|
|
{
|
|
|
|
|
struct dma_chan *chan = host->dma_current;
|
|
|
|
|
enum dma_data_direction dir;
|
|
|
|
|
u32 status;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
/* Wait up to 1ms for the DMA to complete */
|
|
|
|
|
for (i = 0; ; i++) {
|
|
|
|
|
status = readl(host->base + MMCISTATUS);
|
|
|
|
|
if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
|
|
|
|
|
break;
|
|
|
|
|
udelay(10);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Check to see whether we still have some data left in the FIFO -
|
|
|
|
|
* this catches DMA controllers which are unable to monitor the
|
|
|
|
|
* DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
|
|
|
|
|
* contiguous buffers. On TX, we'll get a FIFO underrun error.
|
|
|
|
|
*/
|
|
|
|
|
if (status & MCI_RXDATAAVLBLMASK) {
|
|
|
|
|
dmaengine_terminate_all(chan);
|
|
|
|
|
if (!data->error)
|
|
|
|
|
data->error = -EIO;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_WRITE) {
|
|
|
|
|
dir = DMA_TO_DEVICE;
|
|
|
|
|
} else {
|
|
|
|
|
dir = DMA_FROM_DEVICE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Use of DMA with scatter-gather is impossible.
|
|
|
|
|
* Give up with DMA and switch back to PIO mode.
|
|
|
|
|
*/
|
|
|
|
|
if (status & MCI_RXDATAAVLBLMASK) {
|
|
|
|
|
dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
|
|
|
|
|
mmci_dma_release(host);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mmci_dma_data_error(struct mmci_host *host)
|
|
|
|
|
{
|
|
|
|
|
dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
|
|
|
|
|
dmaengine_terminate_all(host->dma_current);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
|
|
|
|
|
{
|
|
|
|
|
struct variant_data *variant = host->variant;
|
|
|
|
|
struct dma_slave_config conf = {
|
|
|
|
|
.src_addr = host->phybase + MMCIFIFO,
|
|
|
|
|
.dst_addr = host->phybase + MMCIFIFO,
|
|
|
|
|
.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
|
|
|
|
|
.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
|
|
|
|
|
.src_maxburst = variant->fifohalfsize >> 2, /* # of words */
|
|
|
|
|
.dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
|
|
|
|
|
};
|
|
|
|
|
struct mmc_data *data = host->data;
|
|
|
|
|
struct dma_chan *chan;
|
|
|
|
|
struct dma_device *device;
|
|
|
|
|
struct dma_async_tx_descriptor *desc;
|
|
|
|
|
int nr_sg;
|
|
|
|
|
|
|
|
|
|
host->dma_current = NULL;
|
|
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ) {
|
|
|
|
|
conf.direction = DMA_FROM_DEVICE;
|
|
|
|
|
chan = host->dma_rx_channel;
|
|
|
|
|
} else {
|
|
|
|
|
conf.direction = DMA_TO_DEVICE;
|
|
|
|
|
chan = host->dma_tx_channel;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If there's no DMA channel, fall back to PIO */
|
|
|
|
|
if (!chan)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
/* If less than or equal to the fifo size, don't bother with DMA */
|
|
|
|
|
if (host->size <= variant->fifosize)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
device = chan->device;
|
|
|
|
|
nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction);
|
|
|
|
|
if (nr_sg == 0)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
dmaengine_slave_config(chan, &conf);
|
|
|
|
|
desc = device->device_prep_slave_sg(chan, data->sg, nr_sg,
|
|
|
|
|
conf.direction, DMA_CTRL_ACK);
|
|
|
|
|
if (!desc)
|
|
|
|
|
goto unmap_exit;
|
|
|
|
|
|
|
|
|
|
/* Okay, go for it. */
|
|
|
|
|
host->dma_current = chan;
|
|
|
|
|
|
|
|
|
|
dev_vdbg(mmc_dev(host->mmc),
|
|
|
|
|
"Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
|
|
|
|
|
data->sg_len, data->blksz, data->blocks, data->flags);
|
|
|
|
|
dmaengine_submit(desc);
|
|
|
|
|
dma_async_issue_pending(chan);
|
|
|
|
|
|
|
|
|
|
datactrl |= MCI_DPSM_DMAENABLE;
|
|
|
|
|
|
|
|
|
|
/* Trigger the DMA transfer */
|
|
|
|
|
writel(datactrl, host->base + MMCIDATACTRL);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Let the MMCI say when the data is ended and it's time
|
|
|
|
|
* to fire next DMA request. When that happens, MMCI will
|
|
|
|
|
* call mmci_data_end()
|
|
|
|
|
*/
|
|
|
|
|
writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
|
|
|
|
|
host->base + MMCIMASK0);
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
unmap_exit:
|
|
|
|
|
dmaengine_terminate_all(chan);
|
|
|
|
|
dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction);
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
/* Blank functions if the DMA engine is not available */
|
|
|
|
|
static inline void mmci_dma_setup(struct mmci_host *host)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void mmci_dma_release(struct mmci_host *host)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void mmci_dma_data_error(struct mmci_host *host)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
|
|
|
|
|
{
|
|
|
|
|
return -ENOSYS;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
|
|
|
|
|
{
|
2010-08-09 19:57:30 +08:00
|
|
|
struct variant_data *variant = host->variant;
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned int datactrl, timeout, irqmask;
|
2005-07-01 19:02:59 +08:00
|
|
|
unsigned long long clks;
|
2005-04-17 06:20:36 +08:00
|
|
|
void __iomem *base;
|
2006-08-27 20:51:28 +08:00
|
|
|
int blksz_bits;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2010-02-19 08:09:10 +08:00
|
|
|
dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
|
|
|
|
|
data->blksz, data->blocks, data->flags);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
host->data = data;
|
2010-07-21 19:49:49 +08:00
|
|
|
host->size = data->blksz * data->blocks;
|
2011-01-27 18:56:52 +08:00
|
|
|
data->bytes_xfered = 0;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-07-01 19:02:59 +08:00
|
|
|
clks = (unsigned long long)data->timeout_ns * host->cclk;
|
|
|
|
|
do_div(clks, 1000000000UL);
|
|
|
|
|
|
|
|
|
|
timeout = data->timeout_clks + (unsigned int)clks;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
base = host->base;
|
|
|
|
|
writel(timeout, base + MMCIDATATIMER);
|
|
|
|
|
writel(host->size, base + MMCIDATALENGTH);
|
|
|
|
|
|
2006-08-27 20:51:28 +08:00
|
|
|
blksz_bits = ffs(data->blksz) - 1;
|
|
|
|
|
BUG_ON(1 << blksz_bits != data->blksz);
|
|
|
|
|
|
|
|
|
|
datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
|
ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij.
Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface. The changes over Linus' driver are:
- rename txsize_threshold to dmasize_threshold, as this reflects the
purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer. Some DMA controllers
(eg, PL08x) are unable to be configured for scatter DMA and also listen
to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the
final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
its own restrictions on buffer alignment, not the individual DMA engine
users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
causes LBREQ to be asserted for the last seven transfers, rather than
six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
transfer size required to complete the DMA operation.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-12 03:35:53 +08:00
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
2005-04-17 06:20:36 +08:00
|
|
|
datactrl |= MCI_DPSM_DIRECTION;
|
ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij.
Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface. The changes over Linus' driver are:
- rename txsize_threshold to dmasize_threshold, as this reflects the
purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer. Some DMA controllers
(eg, PL08x) are unable to be configured for scatter DMA and also listen
to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the
final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
its own restrictions on buffer alignment, not the individual DMA engine
users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
causes LBREQ to be asserted for the last seven transfers, rather than
six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
transfer size required to complete the DMA operation.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-12 03:35:53 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Attempt to use DMA operation mode, if this
|
|
|
|
|
* should fail, fall back to PIO mode
|
|
|
|
|
*/
|
|
|
|
|
if (!mmci_dma_start_data(host, datactrl))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* IRQ mode, map the SG list for CPU reading/writing */
|
|
|
|
|
mmci_init_sg(host, data);
|
|
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ) {
|
2005-04-17 06:20:36 +08:00
|
|
|
irqmask = MCI_RXFIFOHALFFULLMASK;
|
2006-02-17 00:48:31 +08:00
|
|
|
|
|
|
|
|
/*
|
2011-01-27 17:50:13 +08:00
|
|
|
* If we have less than the fifo 'half-full' threshold to
|
|
|
|
|
* transfer, trigger a PIO interrupt as soon as any data
|
|
|
|
|
* is available.
|
2006-02-17 00:48:31 +08:00
|
|
|
*/
|
2011-01-27 17:50:13 +08:00
|
|
|
if (host->size < variant->fifohalfsize)
|
2006-02-17 00:48:31 +08:00
|
|
|
irqmask |= MCI_RXDATAAVLBLMASK;
|
2005-04-17 06:20:36 +08:00
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* We don't actually need to include "FIFO empty" here
|
|
|
|
|
* since its implicit in "FIFO half empty".
|
|
|
|
|
*/
|
|
|
|
|
irqmask = MCI_TXFIFOHALFEMPTYMASK;
|
|
|
|
|
}
|
|
|
|
|
|
2010-10-19 19:43:58 +08:00
|
|
|
/* The ST Micro variants has a special bit to enable SDIO */
|
|
|
|
|
if (variant->sdio && host->mmc->card)
|
|
|
|
|
if (mmc_card_sdio(host->mmc->card))
|
|
|
|
|
datactrl |= MCI_ST_DPSM_SDIOEN;
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
writel(datactrl, base + MMCIDATACTRL);
|
|
|
|
|
writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
|
2010-10-19 19:39:48 +08:00
|
|
|
mmci_set_mask1(host, irqmask);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
|
|
|
|
|
{
|
|
|
|
|
void __iomem *base = host->base;
|
|
|
|
|
|
2010-02-19 08:09:10 +08:00
|
|
|
dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
|
2005-04-17 06:20:36 +08:00
|
|
|
cmd->opcode, cmd->arg, cmd->flags);
|
|
|
|
|
|
|
|
|
|
if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
|
|
|
|
|
writel(0, base + MMCICOMMAND);
|
|
|
|
|
udelay(1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
c |= cmd->opcode | MCI_CPSM_ENABLE;
|
2006-02-02 20:23:12 +08:00
|
|
|
if (cmd->flags & MMC_RSP_PRESENT) {
|
|
|
|
|
if (cmd->flags & MMC_RSP_136)
|
|
|
|
|
c |= MCI_CPSM_LONGRSP;
|
2005-04-17 06:20:36 +08:00
|
|
|
c |= MCI_CPSM_RESPONSE;
|
|
|
|
|
}
|
|
|
|
|
if (/*interrupt*/0)
|
|
|
|
|
c |= MCI_CPSM_INTERRUPT;
|
|
|
|
|
|
|
|
|
|
host->cmd = cmd;
|
|
|
|
|
|
|
|
|
|
writel(cmd->arg, base + MMCIARGUMENT);
|
|
|
|
|
writel(c, base + MMCICOMMAND);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
|
|
|
|
|
unsigned int status)
|
|
|
|
|
{
|
2010-10-19 20:41:24 +08:00
|
|
|
/* First check for errors */
|
2005-04-17 06:20:36 +08:00
|
|
|
if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
|
2011-01-24 22:22:13 +08:00
|
|
|
u32 remain, success;
|
2010-10-19 20:41:24 +08:00
|
|
|
|
ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij.
Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface. The changes over Linus' driver are:
- rename txsize_threshold to dmasize_threshold, as this reflects the
purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer. Some DMA controllers
(eg, PL08x) are unable to be configured for scatter DMA and also listen
to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the
final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
its own restrictions on buffer alignment, not the individual DMA engine
users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
causes LBREQ to be asserted for the last seven transfers, rather than
six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
transfer size required to complete the DMA operation.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-12 03:35:53 +08:00
|
|
|
/* Terminate the DMA transfer */
|
|
|
|
|
if (dma_inprogress(host))
|
|
|
|
|
mmci_dma_data_error(host);
|
2006-01-05 00:24:05 +08:00
|
|
|
|
|
|
|
|
/*
|
2011-02-04 17:19:46 +08:00
|
|
|
* Calculate how far we are into the transfer. Note that
|
|
|
|
|
* the data counter gives the number of bytes transferred
|
|
|
|
|
* on the MMC bus, not on the host side. On reads, this
|
|
|
|
|
* can be as much as a FIFO-worth of data ahead. This
|
|
|
|
|
* matters for FIFO overruns only.
|
2006-01-05 00:24:05 +08:00
|
|
|
*/
|
2011-01-28 00:44:34 +08:00
|
|
|
remain = readl(host->base + MMCIDATACNT);
|
2011-01-24 22:22:13 +08:00
|
|
|
success = data->blksz * data->blocks - remain;
|
|
|
|
|
|
2011-02-04 17:19:46 +08:00
|
|
|
dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
|
|
|
|
|
status, success);
|
2011-01-24 22:22:13 +08:00
|
|
|
if (status & MCI_DATACRCFAIL) {
|
|
|
|
|
/* Last block was not successful */
|
2011-02-04 17:19:46 +08:00
|
|
|
success -= 1;
|
2007-07-23 04:18:46 +08:00
|
|
|
data->error = -EILSEQ;
|
2011-01-24 22:22:13 +08:00
|
|
|
} else if (status & MCI_DATATIMEOUT) {
|
2007-07-23 04:18:46 +08:00
|
|
|
data->error = -ETIMEDOUT;
|
2011-02-04 17:19:46 +08:00
|
|
|
} else if (status & MCI_TXUNDERRUN) {
|
|
|
|
|
data->error = -EIO;
|
|
|
|
|
} else if (status & MCI_RXOVERRUN) {
|
|
|
|
|
if (success > host->variant->fifosize)
|
|
|
|
|
success -= host->variant->fifosize;
|
|
|
|
|
else
|
|
|
|
|
success = 0;
|
2007-07-23 04:18:46 +08:00
|
|
|
data->error = -EIO;
|
2010-07-21 19:44:58 +08:00
|
|
|
}
|
2011-01-27 18:56:52 +08:00
|
|
|
data->bytes_xfered = round_down(success, data->blksz);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2010-10-19 20:41:24 +08:00
|
|
|
|
2011-01-24 22:22:13 +08:00
|
|
|
if (status & MCI_DATABLOCKEND)
|
|
|
|
|
dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
|
2010-10-19 20:41:24 +08:00
|
|
|
|
2011-01-31 05:03:50 +08:00
|
|
|
if (status & MCI_DATAEND || data->error) {
|
ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij.
Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface. The changes over Linus' driver are:
- rename txsize_threshold to dmasize_threshold, as this reflects the
purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer. Some DMA controllers
(eg, PL08x) are unable to be configured for scatter DMA and also listen
to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the
final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
its own restrictions on buffer alignment, not the individual DMA engine
users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
causes LBREQ to be asserted for the last seven transfers, rather than
six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
transfer size required to complete the DMA operation.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-12 03:35:53 +08:00
|
|
|
if (dma_inprogress(host))
|
|
|
|
|
mmci_dma_unmap(host, data);
|
2005-04-17 06:20:36 +08:00
|
|
|
mmci_stop_data(host);
|
|
|
|
|
|
2011-01-24 22:22:13 +08:00
|
|
|
if (!data->error)
|
|
|
|
|
/* The error clause is handled above, success! */
|
2011-01-27 18:56:52 +08:00
|
|
|
data->bytes_xfered = data->blksz * data->blocks;
|
2010-10-19 20:41:24 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
if (!data->stop) {
|
|
|
|
|
mmci_request_end(host, data->mrq);
|
|
|
|
|
} else {
|
|
|
|
|
mmci_start_command(host, data->stop, 0);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
|
|
|
|
|
unsigned int status)
|
|
|
|
|
{
|
|
|
|
|
void __iomem *base = host->base;
|
|
|
|
|
|
|
|
|
|
host->cmd = NULL;
|
|
|
|
|
|
|
|
|
|
if (status & MCI_CMDTIMEOUT) {
|
2007-07-23 04:18:46 +08:00
|
|
|
cmd->error = -ETIMEDOUT;
|
2005-04-17 06:20:36 +08:00
|
|
|
} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
|
2007-07-23 04:18:46 +08:00
|
|
|
cmd->error = -EILSEQ;
|
2011-01-12 00:35:56 +08:00
|
|
|
} else {
|
|
|
|
|
cmd->resp[0] = readl(base + MMCIRESPONSE0);
|
|
|
|
|
cmd->resp[1] = readl(base + MMCIRESPONSE1);
|
|
|
|
|
cmd->resp[2] = readl(base + MMCIRESPONSE2);
|
|
|
|
|
cmd->resp[3] = readl(base + MMCIRESPONSE3);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2007-07-23 04:18:46 +08:00
|
|
|
if (!cmd->data || cmd->error) {
|
2007-01-09 00:42:51 +08:00
|
|
|
if (host->data)
|
|
|
|
|
mmci_stop_data(host);
|
2005-04-17 06:20:36 +08:00
|
|
|
mmci_request_end(host, cmd->mrq);
|
|
|
|
|
} else if (!(cmd->data->flags & MMC_DATA_READ)) {
|
|
|
|
|
mmci_start_data(host, cmd->data);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
|
|
|
|
|
{
|
|
|
|
|
void __iomem *base = host->base;
|
|
|
|
|
char *ptr = buffer;
|
|
|
|
|
u32 status;
|
2008-04-27 06:39:44 +08:00
|
|
|
int host_remain = host->size;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
do {
|
2008-04-27 06:39:44 +08:00
|
|
|
int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
if (count > remain)
|
|
|
|
|
count = remain;
|
|
|
|
|
|
|
|
|
|
if (count <= 0)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
readsl(base + MMCIFIFO, ptr, count >> 2);
|
|
|
|
|
|
|
|
|
|
ptr += count;
|
|
|
|
|
remain -= count;
|
2008-04-27 06:39:44 +08:00
|
|
|
host_remain -= count;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
if (remain == 0)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
status = readl(base + MMCISTATUS);
|
|
|
|
|
} while (status & MCI_RXDATAAVLBL);
|
|
|
|
|
|
|
|
|
|
return ptr - buffer;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
|
|
|
|
|
{
|
2010-08-09 19:57:30 +08:00
|
|
|
struct variant_data *variant = host->variant;
|
2005-04-17 06:20:36 +08:00
|
|
|
void __iomem *base = host->base;
|
|
|
|
|
char *ptr = buffer;
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
unsigned int count, maxcnt;
|
|
|
|
|
|
2010-08-09 19:57:30 +08:00
|
|
|
maxcnt = status & MCI_TXFIFOEMPTY ?
|
|
|
|
|
variant->fifosize : variant->fifohalfsize;
|
2005-04-17 06:20:36 +08:00
|
|
|
count = min(remain, maxcnt);
|
|
|
|
|
|
2010-10-19 19:43:58 +08:00
|
|
|
/*
|
|
|
|
|
* The ST Micro variant for SDIO transfer sizes
|
|
|
|
|
* less then 8 bytes should have clock H/W flow
|
|
|
|
|
* control disabled.
|
|
|
|
|
*/
|
|
|
|
|
if (variant->sdio &&
|
|
|
|
|
mmc_card_sdio(host->mmc->card)) {
|
|
|
|
|
if (count < 8)
|
|
|
|
|
writel(readl(host->base + MMCICLOCK) &
|
|
|
|
|
~variant->clkreg_enable,
|
|
|
|
|
host->base + MMCICLOCK);
|
|
|
|
|
else
|
|
|
|
|
writel(readl(host->base + MMCICLOCK) |
|
|
|
|
|
variant->clkreg_enable,
|
|
|
|
|
host->base + MMCICLOCK);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* SDIO especially may want to send something that is
|
|
|
|
|
* not divisible by 4 (as opposed to card sectors
|
|
|
|
|
* etc), and the FIFO only accept full 32-bit writes.
|
|
|
|
|
* So compensate by adding +3 on the count, a single
|
|
|
|
|
* byte become a 32bit write, 7 bytes will be two
|
|
|
|
|
* 32bit writes etc.
|
|
|
|
|
*/
|
|
|
|
|
writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
ptr += count;
|
|
|
|
|
remain -= count;
|
|
|
|
|
|
|
|
|
|
if (remain == 0)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
status = readl(base + MMCISTATUS);
|
|
|
|
|
} while (status & MCI_TXFIFOHALFEMPTY);
|
|
|
|
|
|
|
|
|
|
return ptr - buffer;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* PIO data transfer IRQ handler.
|
|
|
|
|
*/
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 21:55:46 +08:00
|
|
|
static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
struct mmci_host *host = dev_id;
|
2010-07-21 19:44:58 +08:00
|
|
|
struct sg_mapping_iter *sg_miter = &host->sg_miter;
|
2010-08-09 19:57:30 +08:00
|
|
|
struct variant_data *variant = host->variant;
|
2005-04-17 06:20:36 +08:00
|
|
|
void __iomem *base = host->base;
|
2010-07-21 19:44:58 +08:00
|
|
|
unsigned long flags;
|
2005-04-17 06:20:36 +08:00
|
|
|
u32 status;
|
|
|
|
|
|
|
|
|
|
status = readl(base + MMCISTATUS);
|
|
|
|
|
|
2010-02-19 08:09:10 +08:00
|
|
|
dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2010-07-21 19:44:58 +08:00
|
|
|
local_irq_save(flags);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
do {
|
|
|
|
|
unsigned int remain, len;
|
|
|
|
|
char *buffer;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* For write, we only need to test the half-empty flag
|
|
|
|
|
* here - if the FIFO is completely empty, then by
|
|
|
|
|
* definition it is more than half empty.
|
|
|
|
|
*
|
|
|
|
|
* For read, check for data available.
|
|
|
|
|
*/
|
|
|
|
|
if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
|
|
|
|
|
break;
|
|
|
|
|
|
2010-07-21 19:44:58 +08:00
|
|
|
if (!sg_miter_next(sg_miter))
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
buffer = sg_miter->addr;
|
|
|
|
|
remain = sg_miter->length;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
len = 0;
|
|
|
|
|
if (status & MCI_RXACTIVE)
|
|
|
|
|
len = mmci_pio_read(host, buffer, remain);
|
|
|
|
|
if (status & MCI_TXACTIVE)
|
|
|
|
|
len = mmci_pio_write(host, buffer, remain, status);
|
|
|
|
|
|
2010-07-21 19:44:58 +08:00
|
|
|
sg_miter->consumed = len;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
host->size -= len;
|
|
|
|
|
remain -= len;
|
|
|
|
|
|
|
|
|
|
if (remain)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
status = readl(base + MMCISTATUS);
|
|
|
|
|
} while (1);
|
|
|
|
|
|
2010-07-21 19:44:58 +08:00
|
|
|
sg_miter_stop(sg_miter);
|
|
|
|
|
|
|
|
|
|
local_irq_restore(flags);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
2011-01-27 17:50:13 +08:00
|
|
|
* If we have less than the fifo 'half-full' threshold to transfer,
|
|
|
|
|
* trigger a PIO interrupt as soon as any data is available.
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
2011-01-27 17:50:13 +08:00
|
|
|
if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
|
2010-10-19 19:39:48 +08:00
|
|
|
mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If we run out of data, disable the data IRQs; this
|
|
|
|
|
* prevents a race where the FIFO becomes empty before
|
|
|
|
|
* the chip itself has disabled the data path, and
|
|
|
|
|
* stops us racing with our data end IRQ.
|
|
|
|
|
*/
|
|
|
|
|
if (host->size == 0) {
|
2010-10-19 19:39:48 +08:00
|
|
|
mmci_set_mask1(host, 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Handle completion of command and data transfers.
|
|
|
|
|
*/
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 21:55:46 +08:00
|
|
|
static irqreturn_t mmci_irq(int irq, void *dev_id)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
struct mmci_host *host = dev_id;
|
|
|
|
|
u32 status;
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
spin_lock(&host->lock);
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
struct mmc_command *cmd;
|
|
|
|
|
struct mmc_data *data;
|
|
|
|
|
|
|
|
|
|
status = readl(host->base + MMCISTATUS);
|
2010-10-19 19:39:48 +08:00
|
|
|
|
|
|
|
|
if (host->singleirq) {
|
|
|
|
|
if (status & readl(host->base + MMCIMASK1))
|
|
|
|
|
mmci_pio_irq(irq, dev_id);
|
|
|
|
|
|
|
|
|
|
status &= ~MCI_IRQ1MASK;
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
status &= readl(host->base + MMCIMASK0);
|
|
|
|
|
writel(status, host->base + MMCICLEAR);
|
|
|
|
|
|
2010-02-19 08:09:10 +08:00
|
|
|
dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
data = host->data;
|
|
|
|
|
if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
|
|
|
|
|
MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
|
|
|
|
|
mmci_data_irq(host, data, status);
|
|
|
|
|
|
|
|
|
|
cmd = host->cmd;
|
|
|
|
|
if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
|
|
|
|
|
mmci_cmd_irq(host, cmd, status);
|
|
|
|
|
|
|
|
|
|
ret = 1;
|
|
|
|
|
} while (status);
|
|
|
|
|
|
|
|
|
|
spin_unlock(&host->lock);
|
|
|
|
|
|
|
|
|
|
return IRQ_RETVAL(ret);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
|
|
|
{
|
|
|
|
|
struct mmci_host *host = mmc_priv(mmc);
|
2008-10-25 04:17:50 +08:00
|
|
|
unsigned long flags;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
WARN_ON(host->mrq != NULL);
|
|
|
|
|
|
2007-10-11 13:06:03 +08:00
|
|
|
if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
|
2010-02-19 08:09:10 +08:00
|
|
|
dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
|
|
|
|
|
mrq->data->blksz);
|
2007-07-25 02:38:53 +08:00
|
|
|
mrq->cmd->error = -EINVAL;
|
|
|
|
|
mmc_request_done(mmc, mrq);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2008-10-25 04:17:50 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
host->mrq = mrq;
|
|
|
|
|
|
|
|
|
|
if (mrq->data && mrq->data->flags & MMC_DATA_READ)
|
|
|
|
|
mmci_start_data(host, mrq->data);
|
|
|
|
|
|
|
|
|
|
mmci_start_command(host, mrq->cmd, 0);
|
|
|
|
|
|
2008-10-25 04:17:50 +08:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
|
|
|
{
|
|
|
|
|
struct mmci_host *host = mmc_priv(mmc);
|
2009-09-14 19:56:14 +08:00
|
|
|
u32 pwr = 0;
|
|
|
|
|
unsigned long flags;
|
2010-09-29 13:08:27 +08:00
|
|
|
int ret;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
switch (ios->power_mode) {
|
|
|
|
|
case MMC_POWER_OFF:
|
2010-09-29 13:08:27 +08:00
|
|
|
if (host->vcc)
|
|
|
|
|
ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
break;
|
|
|
|
|
case MMC_POWER_UP:
|
2010-09-29 13:08:27 +08:00
|
|
|
if (host->vcc) {
|
|
|
|
|
ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(mmc_dev(mmc), "unable to set OCR\n");
|
|
|
|
|
/*
|
|
|
|
|
* The .set_ios() function in the mmc_host_ops
|
|
|
|
|
* struct return void, and failing to set the
|
|
|
|
|
* power should be rare so we print an error
|
|
|
|
|
* and return here.
|
|
|
|
|
*/
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
2010-07-21 19:53:57 +08:00
|
|
|
if (host->plat->vdd_handler)
|
|
|
|
|
pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
|
|
|
|
|
ios->power_mode);
|
2009-01-04 22:18:54 +08:00
|
|
|
/* The ST version does not have this, fall through to POWER_ON */
|
2009-08-04 08:01:02 +08:00
|
|
|
if (host->hw_designer != AMBA_VENDOR_ST) {
|
2009-01-04 22:18:54 +08:00
|
|
|
pwr |= MCI_PWR_UP;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
case MMC_POWER_ON:
|
|
|
|
|
pwr |= MCI_PWR_ON;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2009-01-04 22:18:54 +08:00
|
|
|
if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
|
2009-08-04 08:01:02 +08:00
|
|
|
if (host->hw_designer != AMBA_VENDOR_ST)
|
2009-01-04 22:18:54 +08:00
|
|
|
pwr |= MCI_ROD;
|
|
|
|
|
else {
|
|
|
|
|
/*
|
|
|
|
|
* The ST Micro variant use the ROD bit for something
|
|
|
|
|
* else and only has OD (Open Drain).
|
|
|
|
|
*/
|
|
|
|
|
pwr |= MCI_OD;
|
|
|
|
|
}
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2009-09-14 19:56:14 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
|
|
mmci_set_clkreg(host, ios->clock);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
if (host->pwr != pwr) {
|
|
|
|
|
host->pwr = pwr;
|
|
|
|
|
writel(pwr, host->base + MMCIPOWER);
|
|
|
|
|
}
|
2009-09-14 19:56:14 +08:00
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2009-07-09 22:16:07 +08:00
|
|
|
static int mmci_get_ro(struct mmc_host *mmc)
|
|
|
|
|
{
|
|
|
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
|
|
if (host->gpio_wp == -ENOSYS)
|
|
|
|
|
return -ENOSYS;
|
|
|
|
|
|
2010-09-12 19:56:44 +08:00
|
|
|
return gpio_get_value_cansleep(host->gpio_wp);
|
2009-07-09 22:16:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mmci_get_cd(struct mmc_host *mmc)
|
|
|
|
|
{
|
|
|
|
|
struct mmci_host *host = mmc_priv(mmc);
|
2010-08-09 19:54:43 +08:00
|
|
|
struct mmci_platform_data *plat = host->plat;
|
2009-07-09 22:16:07 +08:00
|
|
|
unsigned int status;
|
|
|
|
|
|
2010-08-09 19:56:40 +08:00
|
|
|
if (host->gpio_cd == -ENOSYS) {
|
|
|
|
|
if (!plat->status)
|
|
|
|
|
return 1; /* Assume always present */
|
|
|
|
|
|
2010-08-09 19:54:43 +08:00
|
|
|
status = plat->status(mmc_dev(host->mmc));
|
2010-08-09 19:56:40 +08:00
|
|
|
} else
|
2010-09-12 19:56:44 +08:00
|
|
|
status = !!gpio_get_value_cansleep(host->gpio_cd)
|
|
|
|
|
^ plat->cd_invert;
|
2009-07-09 22:16:07 +08:00
|
|
|
|
2010-07-29 22:58:59 +08:00
|
|
|
/*
|
|
|
|
|
* Use positive logic throughout - status is zero for no card,
|
|
|
|
|
* non-zero for card inserted.
|
|
|
|
|
*/
|
|
|
|
|
return status;
|
2009-07-09 22:16:07 +08:00
|
|
|
}
|
|
|
|
|
|
2010-08-09 19:55:48 +08:00
|
|
|
static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
|
|
|
|
|
{
|
|
|
|
|
struct mmci_host *host = dev_id;
|
|
|
|
|
|
|
|
|
|
mmc_detect_change(host->mmc, msecs_to_jiffies(500));
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
2006-11-13 09:55:30 +08:00
|
|
|
static const struct mmc_host_ops mmci_ops = {
|
2005-04-17 06:20:36 +08:00
|
|
|
.request = mmci_request,
|
|
|
|
|
.set_ios = mmci_set_ios,
|
2009-07-09 22:16:07 +08:00
|
|
|
.get_ro = mmci_get_ro,
|
|
|
|
|
.get_cd = mmci_get_cd,
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
|
2011-02-19 23:55:00 +08:00
|
|
|
static int __devinit mmci_probe(struct amba_device *dev,
|
|
|
|
|
const struct amba_id *id)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2009-09-22 21:29:36 +08:00
|
|
|
struct mmci_platform_data *plat = dev->dev.platform_data;
|
2010-07-21 19:54:40 +08:00
|
|
|
struct variant_data *variant = id->data;
|
2005-04-17 06:20:36 +08:00
|
|
|
struct mmci_host *host;
|
|
|
|
|
struct mmc_host *mmc;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
/* must have platform data */
|
|
|
|
|
if (!plat) {
|
|
|
|
|
ret = -EINVAL;
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = amba_request_regions(dev, DRIVER_NAME);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
|
|
|
|
|
if (!mmc) {
|
|
|
|
|
ret = -ENOMEM;
|
|
|
|
|
goto rel_regions;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
host = mmc_priv(mmc);
|
2009-04-17 11:14:19 +08:00
|
|
|
host->mmc = mmc;
|
2009-07-09 22:13:56 +08:00
|
|
|
|
2009-07-09 22:16:07 +08:00
|
|
|
host->gpio_wp = -ENOSYS;
|
|
|
|
|
host->gpio_cd = -ENOSYS;
|
2010-08-09 19:55:48 +08:00
|
|
|
host->gpio_cd_irq = -1;
|
2009-07-09 22:16:07 +08:00
|
|
|
|
2009-07-09 22:13:56 +08:00
|
|
|
host->hw_designer = amba_manf(dev);
|
|
|
|
|
host->hw_revision = amba_rev(dev);
|
2010-02-19 08:09:10 +08:00
|
|
|
dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
|
|
|
|
|
dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
|
2009-07-09 22:13:56 +08:00
|
|
|
|
2008-12-01 01:38:14 +08:00
|
|
|
host->clk = clk_get(&dev->dev, NULL);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (IS_ERR(host->clk)) {
|
|
|
|
|
ret = PTR_ERR(host->clk);
|
|
|
|
|
host->clk = NULL;
|
|
|
|
|
goto host_free;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = clk_enable(host->clk);
|
|
|
|
|
if (ret)
|
2006-01-04 02:41:37 +08:00
|
|
|
goto clk_free;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
host->plat = plat;
|
2010-07-21 19:54:40 +08:00
|
|
|
host->variant = variant;
|
2005-04-17 06:20:36 +08:00
|
|
|
host->mclk = clk_get_rate(host->clk);
|
2008-04-29 16:34:07 +08:00
|
|
|
/*
|
|
|
|
|
* According to the spec, mclk is max 100 MHz,
|
|
|
|
|
* so we try to adjust the clock down to this,
|
|
|
|
|
* (if possible).
|
|
|
|
|
*/
|
|
|
|
|
if (host->mclk > 100000000) {
|
|
|
|
|
ret = clk_set_rate(host->clk, 100000000);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
goto clk_disable;
|
|
|
|
|
host->mclk = clk_get_rate(host->clk);
|
2010-02-19 08:09:10 +08:00
|
|
|
dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
|
|
|
|
|
host->mclk);
|
2008-04-29 16:34:07 +08:00
|
|
|
}
|
ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij.
Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface. The changes over Linus' driver are:
- rename txsize_threshold to dmasize_threshold, as this reflects the
purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer. Some DMA controllers
(eg, PL08x) are unable to be configured for scatter DMA and also listen
to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the
final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
its own restrictions on buffer alignment, not the individual DMA engine
users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
causes LBREQ to be asserted for the last seven transfers, rather than
six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
transfer size required to complete the DMA operation.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-12 03:35:53 +08:00
|
|
|
host->phybase = dev->res.start;
|
2009-06-08 06:27:31 +08:00
|
|
|
host->base = ioremap(dev->res.start, resource_size(&dev->res));
|
2005-04-17 06:20:36 +08:00
|
|
|
if (!host->base) {
|
|
|
|
|
ret = -ENOMEM;
|
|
|
|
|
goto clk_disable;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mmc->ops = &mmci_ops;
|
|
|
|
|
mmc->f_min = (host->mclk + 511) / 512;
|
2010-04-08 14:39:38 +08:00
|
|
|
/*
|
|
|
|
|
* If the platform data supplies a maximum operating
|
|
|
|
|
* frequency, this takes precedence. Else, we fall back
|
|
|
|
|
* to using the module parameter, which has a (low)
|
|
|
|
|
* default value in case it is not specified. Either
|
|
|
|
|
* value must not exceed the clock rate into the block,
|
|
|
|
|
* of course.
|
|
|
|
|
*/
|
|
|
|
|
if (plat->f_max)
|
|
|
|
|
mmc->f_max = min(host->mclk, plat->f_max);
|
|
|
|
|
else
|
|
|
|
|
mmc->f_max = min(host->mclk, fmax);
|
2010-02-19 08:09:10 +08:00
|
|
|
dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
|
|
|
|
|
|
2009-09-22 21:41:40 +08:00
|
|
|
#ifdef CONFIG_REGULATOR
|
|
|
|
|
/* If we're using the regulator framework, try to fetch a regulator */
|
|
|
|
|
host->vcc = regulator_get(&dev->dev, "vmmc");
|
|
|
|
|
if (IS_ERR(host->vcc))
|
|
|
|
|
host->vcc = NULL;
|
|
|
|
|
else {
|
|
|
|
|
int mask = mmc_regulator_get_ocrmask(host->vcc);
|
|
|
|
|
|
|
|
|
|
if (mask < 0)
|
|
|
|
|
dev_err(&dev->dev, "error getting OCR mask (%d)\n",
|
|
|
|
|
mask);
|
|
|
|
|
else {
|
|
|
|
|
host->mmc->ocr_avail = (u32) mask;
|
|
|
|
|
if (plat->ocr_mask)
|
|
|
|
|
dev_warn(&dev->dev,
|
|
|
|
|
"Provided ocr_mask/setpower will not be used "
|
|
|
|
|
"(using regulator instead)\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
/* Fall back to platform data if no regulator is found */
|
|
|
|
|
if (host->vcc == NULL)
|
|
|
|
|
mmc->ocr_avail = plat->ocr_mask;
|
2009-09-14 19:57:11 +08:00
|
|
|
mmc->caps = plat->capabilities;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We can do SGIO
|
|
|
|
|
*/
|
2010-09-10 13:33:59 +08:00
|
|
|
mmc->max_segs = NR_SG;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/*
|
2010-07-21 19:55:59 +08:00
|
|
|
* Since only a certain number of bits are valid in the data length
|
|
|
|
|
* register, we must ensure that we don't exceed 2^num-1 bytes in a
|
|
|
|
|
* single request.
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
2010-07-21 19:55:59 +08:00
|
|
|
mmc->max_req_size = (1 << variant->datalength_bits) - 1;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Set the maximum segment size. Since we aren't doing DMA
|
|
|
|
|
* (yet) we are only limited by the data length register.
|
|
|
|
|
*/
|
2006-11-22 00:55:45 +08:00
|
|
|
mmc->max_seg_size = mmc->max_req_size;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-11-22 00:54:23 +08:00
|
|
|
/*
|
|
|
|
|
* Block size can be up to 2048 bytes, but must be a power of two.
|
|
|
|
|
*/
|
|
|
|
|
mmc->max_blk_size = 2048;
|
|
|
|
|
|
2006-11-22 00:55:45 +08:00
|
|
|
/*
|
|
|
|
|
* No limit on the number of blocks transferred.
|
|
|
|
|
*/
|
|
|
|
|
mmc->max_blk_count = mmc->max_req_size;
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
|
|
|
|
|
|
writel(0, host->base + MMCIMASK0);
|
|
|
|
|
writel(0, host->base + MMCIMASK1);
|
|
|
|
|
writel(0xfff, host->base + MMCICLEAR);
|
|
|
|
|
|
2009-07-09 22:16:07 +08:00
|
|
|
if (gpio_is_valid(plat->gpio_cd)) {
|
|
|
|
|
ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
|
|
|
|
|
if (ret == 0)
|
|
|
|
|
ret = gpio_direction_input(plat->gpio_cd);
|
|
|
|
|
if (ret == 0)
|
|
|
|
|
host->gpio_cd = plat->gpio_cd;
|
|
|
|
|
else if (ret != -ENOSYS)
|
|
|
|
|
goto err_gpio_cd;
|
2010-08-09 19:55:48 +08:00
|
|
|
|
|
|
|
|
ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
|
|
|
|
|
mmci_cd_irq, 0,
|
|
|
|
|
DRIVER_NAME " (cd)", host);
|
|
|
|
|
if (ret >= 0)
|
|
|
|
|
host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
|
2009-07-09 22:16:07 +08:00
|
|
|
}
|
|
|
|
|
if (gpio_is_valid(plat->gpio_wp)) {
|
|
|
|
|
ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
|
|
|
|
|
if (ret == 0)
|
|
|
|
|
ret = gpio_direction_input(plat->gpio_wp);
|
|
|
|
|
if (ret == 0)
|
|
|
|
|
host->gpio_wp = plat->gpio_wp;
|
|
|
|
|
else if (ret != -ENOSYS)
|
|
|
|
|
goto err_gpio_wp;
|
|
|
|
|
}
|
|
|
|
|
|
2010-08-09 19:56:40 +08:00
|
|
|
if ((host->plat->status || host->gpio_cd != -ENOSYS)
|
|
|
|
|
&& host->gpio_cd_irq < 0)
|
2010-08-09 19:55:48 +08:00
|
|
|
mmc->caps |= MMC_CAP_NEEDS_POLL;
|
|
|
|
|
|
2006-07-02 10:29:38 +08:00
|
|
|
ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (ret)
|
|
|
|
|
goto unmap;
|
|
|
|
|
|
2010-10-19 19:39:48 +08:00
|
|
|
if (dev->irq[1] == NO_IRQ)
|
|
|
|
|
host->singleirq = true;
|
|
|
|
|
else {
|
|
|
|
|
ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
|
|
|
|
|
DRIVER_NAME " (pio)", host);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto irq0_free;
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2011-01-24 22:22:13 +08:00
|
|
|
writel(MCI_IRQENABLE, host->base + MMCIMASK0);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
amba_set_drvdata(dev, mmc);
|
|
|
|
|
|
ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij.
Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface. The changes over Linus' driver are:
- rename txsize_threshold to dmasize_threshold, as this reflects the
purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer. Some DMA controllers
(eg, PL08x) are unable to be configured for scatter DMA and also listen
to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the
final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
its own restrictions on buffer alignment, not the individual DMA engine
users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
causes LBREQ to be asserted for the last seven transfers, rather than
six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
transfer size required to complete the DMA operation.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-12 03:35:53 +08:00
|
|
|
dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
|
|
|
|
|
mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
|
|
|
|
|
amba_rev(dev), (unsigned long long)dev->res.start,
|
|
|
|
|
dev->irq[0], dev->irq[1]);
|
|
|
|
|
|
|
|
|
|
mmci_dma_setup(host);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2010-12-29 03:40:40 +08:00
|
|
|
mmc_add_host(mmc);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
irq0_free:
|
|
|
|
|
free_irq(dev->irq[0], host);
|
|
|
|
|
unmap:
|
2009-07-09 22:16:07 +08:00
|
|
|
if (host->gpio_wp != -ENOSYS)
|
|
|
|
|
gpio_free(host->gpio_wp);
|
|
|
|
|
err_gpio_wp:
|
2010-08-09 19:55:48 +08:00
|
|
|
if (host->gpio_cd_irq >= 0)
|
|
|
|
|
free_irq(host->gpio_cd_irq, host);
|
2009-07-09 22:16:07 +08:00
|
|
|
if (host->gpio_cd != -ENOSYS)
|
|
|
|
|
gpio_free(host->gpio_cd);
|
|
|
|
|
err_gpio_cd:
|
2005-04-17 06:20:36 +08:00
|
|
|
iounmap(host->base);
|
|
|
|
|
clk_disable:
|
|
|
|
|
clk_disable(host->clk);
|
|
|
|
|
clk_free:
|
|
|
|
|
clk_put(host->clk);
|
|
|
|
|
host_free:
|
|
|
|
|
mmc_free_host(mmc);
|
|
|
|
|
rel_regions:
|
|
|
|
|
amba_release_regions(dev);
|
|
|
|
|
out:
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2009-03-07 07:23:52 +08:00
|
|
|
static int __devexit mmci_remove(struct amba_device *dev)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
struct mmc_host *mmc = amba_get_drvdata(dev);
|
|
|
|
|
|
|
|
|
|
amba_set_drvdata(dev, NULL);
|
|
|
|
|
|
|
|
|
|
if (mmc) {
|
|
|
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
|
|
mmc_remove_host(mmc);
|
|
|
|
|
|
|
|
|
|
writel(0, host->base + MMCIMASK0);
|
|
|
|
|
writel(0, host->base + MMCIMASK1);
|
|
|
|
|
|
|
|
|
|
writel(0, host->base + MMCICOMMAND);
|
|
|
|
|
writel(0, host->base + MMCIDATACTRL);
|
|
|
|
|
|
ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij.
Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface. The changes over Linus' driver are:
- rename txsize_threshold to dmasize_threshold, as this reflects the
purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer. Some DMA controllers
(eg, PL08x) are unable to be configured for scatter DMA and also listen
to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the
final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
its own restrictions on buffer alignment, not the individual DMA engine
users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
causes LBREQ to be asserted for the last seven transfers, rather than
six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
transfer size required to complete the DMA operation.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-12 03:35:53 +08:00
|
|
|
mmci_dma_release(host);
|
2005-04-17 06:20:36 +08:00
|
|
|
free_irq(dev->irq[0], host);
|
2010-10-19 19:39:48 +08:00
|
|
|
if (!host->singleirq)
|
|
|
|
|
free_irq(dev->irq[1], host);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2009-07-09 22:16:07 +08:00
|
|
|
if (host->gpio_wp != -ENOSYS)
|
|
|
|
|
gpio_free(host->gpio_wp);
|
2010-08-09 19:55:48 +08:00
|
|
|
if (host->gpio_cd_irq >= 0)
|
|
|
|
|
free_irq(host->gpio_cd_irq, host);
|
2009-07-09 22:16:07 +08:00
|
|
|
if (host->gpio_cd != -ENOSYS)
|
|
|
|
|
gpio_free(host->gpio_cd);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
iounmap(host->base);
|
|
|
|
|
clk_disable(host->clk);
|
|
|
|
|
clk_put(host->clk);
|
|
|
|
|
|
2010-09-29 13:08:27 +08:00
|
|
|
if (host->vcc)
|
|
|
|
|
mmc_regulator_set_ocr(mmc, host->vcc, 0);
|
2009-09-22 21:41:40 +08:00
|
|
|
regulator_put(host->vcc);
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
mmc_free_host(mmc);
|
|
|
|
|
|
|
|
|
|
amba_release_regions(dev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
2005-04-17 06:25:29 +08:00
|
|
|
static int mmci_suspend(struct amba_device *dev, pm_message_t state)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
struct mmc_host *mmc = amba_get_drvdata(dev);
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
if (mmc) {
|
|
|
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
|
|
|
|
2010-05-27 05:42:08 +08:00
|
|
|
ret = mmc_suspend_host(mmc);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (ret == 0)
|
|
|
|
|
writel(0, host->base + MMCIMASK0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mmci_resume(struct amba_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct mmc_host *mmc = amba_get_drvdata(dev);
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
if (mmc) {
|
|
|
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
|
|
writel(MCI_IRQENABLE, host->base + MMCIMASK0);
|
|
|
|
|
|
|
|
|
|
ret = mmc_resume_host(mmc);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
#define mmci_suspend NULL
|
|
|
|
|
#define mmci_resume NULL
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
static struct amba_id mmci_ids[] = {
|
|
|
|
|
{
|
|
|
|
|
.id = 0x00041180,
|
|
|
|
|
.mask = 0x000fffff,
|
2010-07-21 19:54:40 +08:00
|
|
|
.data = &variant_arm,
|
2005-04-17 06:20:36 +08:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.id = 0x00041181,
|
|
|
|
|
.mask = 0x000fffff,
|
2010-07-21 19:54:40 +08:00
|
|
|
.data = &variant_arm,
|
2005-04-17 06:20:36 +08:00
|
|
|
},
|
2009-01-04 22:18:54 +08:00
|
|
|
/* ST Micro variants */
|
|
|
|
|
{
|
|
|
|
|
.id = 0x00180180,
|
|
|
|
|
.mask = 0x00ffffff,
|
2010-07-21 19:54:40 +08:00
|
|
|
.data = &variant_u300,
|
2009-01-04 22:18:54 +08:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.id = 0x00280180,
|
|
|
|
|
.mask = 0x00ffffff,
|
2010-07-21 19:54:40 +08:00
|
|
|
.data = &variant_u300,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.id = 0x00480180,
|
|
|
|
|
.mask = 0x00ffffff,
|
|
|
|
|
.data = &variant_ux500,
|
2009-01-04 22:18:54 +08:00
|
|
|
},
|
2005-04-17 06:20:36 +08:00
|
|
|
{ 0, 0 },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct amba_driver mmci_driver = {
|
|
|
|
|
.drv = {
|
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
|
},
|
|
|
|
|
.probe = mmci_probe,
|
2009-03-07 07:23:52 +08:00
|
|
|
.remove = __devexit_p(mmci_remove),
|
2005-04-17 06:20:36 +08:00
|
|
|
.suspend = mmci_suspend,
|
|
|
|
|
.resume = mmci_resume,
|
|
|
|
|
.id_table = mmci_ids,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init mmci_init(void)
|
|
|
|
|
{
|
|
|
|
|
return amba_driver_register(&mmci_driver);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __exit mmci_exit(void)
|
|
|
|
|
{
|
|
|
|
|
amba_driver_unregister(&mmci_driver);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
module_init(mmci_init);
|
|
|
|
|
module_exit(mmci_exit);
|
|
|
|
|
module_param(fmax, uint, 0444);
|
|
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
|
|
|
|
|
MODULE_LICENSE("GPL");
|