2019-05-29 22:18:05 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2010-01-07 07:07:18 +08:00
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/*******************************************************************************
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DWMAC DMA Header file.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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2012-08-23 05:28:18 +08:00
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#ifndef __DWMAC_DMA_H__
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#define __DWMAC_DMA_H__
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2010-01-07 07:07:18 +08:00
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/* DMA CRS Control and Status Register Mapping */
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#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
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#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
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#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
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#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
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#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
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#define DMA_STATUS 0x00001014 /* Status Register */
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#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
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#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
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#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
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2016-02-29 21:27:27 +08:00
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/* SW Reset */
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#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
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2012-11-26 07:10:43 +08:00
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/* Rx watchdog register */
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#define DMA_RX_WATCHDOG 0x00001024
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2016-02-29 21:27:28 +08:00
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/* AXI Master Bus Mode */
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2012-11-26 07:10:43 +08:00
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#define DMA_AXI_BUS_MODE 0x00001028
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2016-02-29 21:27:28 +08:00
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#define DMA_AXI_EN_LPI BIT(31)
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#define DMA_AXI_LPI_XIT_FRM BIT(30)
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#define DMA_AXI_WR_OSR_LMT GENMASK(23, 20)
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#define DMA_AXI_WR_OSR_LMT_SHIFT 20
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#define DMA_AXI_WR_OSR_LMT_MASK 0xf
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#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
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#define DMA_AXI_RD_OSR_LMT_SHIFT 16
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#define DMA_AXI_RD_OSR_LMT_MASK 0xf
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#define DMA_AXI_OSR_MAX 0xf
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#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
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(DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
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#define DMA_AXI_1KBBE BIT(13)
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#define DMA_AXI_AAL BIT(12)
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#define DMA_AXI_BLEN256 BIT(7)
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#define DMA_AXI_BLEN128 BIT(6)
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#define DMA_AXI_BLEN64 BIT(5)
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#define DMA_AXI_BLEN32 BIT(4)
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#define DMA_AXI_BLEN16 BIT(3)
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#define DMA_AXI_BLEN8 BIT(2)
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#define DMA_AXI_BLEN4 BIT(1)
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#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
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DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
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DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
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DMA_AXI_BLEN4)
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#define DMA_AXI_UNDEF BIT(0)
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#define DMA_AXI_BURST_LEN_MASK 0x000000FE
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2010-01-07 07:07:18 +08:00
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#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
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#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
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2011-09-02 05:51:41 +08:00
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#define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */
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2010-01-07 07:07:18 +08:00
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/* DMA Control register defines */
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#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
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#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
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/* DMA Normal interrupt */
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#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
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#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
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#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
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#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
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#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
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#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
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DMA_INTR_ENA_TIE)
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/* DMA Abnormal interrupt */
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#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
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#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
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#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
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#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
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#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
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#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
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#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
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#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
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#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
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#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
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#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
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DMA_INTR_ENA_UNE)
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/* DMA default interrupt mask */
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#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
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2019-12-18 18:24:44 +08:00
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#define DMA_INTR_DEFAULT_RX (DMA_INTR_ENA_RIE)
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#define DMA_INTR_DEFAULT_TX (DMA_INTR_ENA_TIE)
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2010-01-07 07:07:18 +08:00
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/* DMA Status register defines */
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2012-06-28 05:14:37 +08:00
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#define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */
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2010-01-07 07:07:18 +08:00
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#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
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#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
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#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
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#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
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#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
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#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
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#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
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#define DMA_STATUS_TS_SHIFT 20
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#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
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#define DMA_STATUS_RS_SHIFT 17
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#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
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#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
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#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
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#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
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#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
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#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
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#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
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#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
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#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
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#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
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#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
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#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
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#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
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#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
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#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
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2013-04-08 10:10:01 +08:00
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#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
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2010-01-07 07:07:18 +08:00
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2017-07-22 05:35:09 +08:00
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#define NUM_DWMAC100_DMA_REGS 9
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#define NUM_DWMAC1000_DMA_REGS 23
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2013-09-24 02:37:59 +08:00
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void dwmac_enable_dma_transmission(void __iomem *ioaddr);
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2019-12-18 18:24:44 +08:00
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void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
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void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
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2017-03-15 19:04:47 +08:00
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void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan);
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void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan);
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void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan);
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void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan);
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2017-03-15 19:04:49 +08:00
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int dwmac_dma_interrupt(void __iomem *ioaddr, struct stmmac_extra_stats *x,
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u32 chan);
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2016-02-29 21:27:27 +08:00
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int dwmac_dma_reset(void __iomem *ioaddr);
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2012-08-23 05:28:18 +08:00
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#endif /* __DWMAC_DMA_H__ */
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