2012-09-20 21:04:33 +08:00
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/*
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* Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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2013-04-07 10:49:34 +08:00
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#include "skeleton.dtsi"
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2013-11-06 16:52:16 +08:00
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#include "imx25-pinfunc.h"
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2012-09-20 21:04:33 +08:00
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/ {
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aliases {
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2014-02-28 19:58:41 +08:00
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ethernet0 = &fec;
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2013-06-25 21:51:53 +08:00
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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2014-05-09 14:11:14 +08:00
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mmc0 = &esdhc1;
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mmc1 = &esdhc2;
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2012-09-20 21:04:33 +08:00
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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2013-06-25 21:51:53 +08:00
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spi0 = &spi1;
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spi1 = &spi2;
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spi2 = &spi3;
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2012-09-20 21:04:33 +08:00
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usb0 = &usbotg;
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usb1 = &usbhost1;
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};
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2013-07-07 21:12:30 +08:00
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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};
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};
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2012-09-20 21:04:33 +08:00
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asic: asic-interrupt-controller@68000000 {
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compatible = "fsl,imx25-asic", "fsl,avic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x68000000 0x8000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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2014-04-11 09:56:46 +08:00
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#clock-cells = <0>;
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2012-09-20 21:04:33 +08:00
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clock-frequency = <24000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&asic>;
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ranges;
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aips@43f00000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x43f00000 0x100000>;
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ranges;
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i2c1: i2c@43f80000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
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reg = <0x43f80000 0x4000>;
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clocks = <&clks 48>;
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clock-names = "";
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interrupts = <3>;
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status = "disabled";
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};
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i2c3: i2c@43f84000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
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reg = <0x43f84000 0x4000>;
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clocks = <&clks 48>;
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clock-names = "";
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interrupts = <10>;
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status = "disabled";
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};
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can1: can@43f88000 {
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compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
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reg = <0x43f88000 0x4000>;
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interrupts = <43>;
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clocks = <&clks 75>, <&clks 75>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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can2: can@43f8c000 {
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compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
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reg = <0x43f8c000 0x4000>;
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interrupts = <44>;
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clocks = <&clks 76>, <&clks 76>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart1: serial@43f90000 {
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compatible = "fsl,imx25-uart", "fsl,imx21-uart";
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reg = <0x43f90000 0x4000>;
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interrupts = <45>;
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clocks = <&clks 120>, <&clks 57>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart2: serial@43f94000 {
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compatible = "fsl,imx25-uart", "fsl,imx21-uart";
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reg = <0x43f94000 0x4000>;
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interrupts = <32>;
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clocks = <&clks 121>, <&clks 57>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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i2c2: i2c@43f98000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
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reg = <0x43f98000 0x4000>;
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clocks = <&clks 48>;
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clock-names = "";
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interrupts = <4>;
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status = "disabled";
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};
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owire@43f9c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x43f9c000 0x4000>;
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clocks = <&clks 51>;
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clock-names = "";
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interrupts = <2>;
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status = "disabled";
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};
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spi1: cspi@43fa4000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
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reg = <0x43fa4000 0x4000>;
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2014-12-06 02:16:07 +08:00
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clocks = <&clks 78>, <&clks 78>;
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2013-05-23 19:38:05 +08:00
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clock-names = "ipg", "per";
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2012-09-20 21:04:33 +08:00
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interrupts = <14>;
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status = "disabled";
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};
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2014-03-12 21:19:24 +08:00
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kpp: kpp@43fa8000 {
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2012-09-20 21:04:33 +08:00
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#address-cells = <1>;
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#size-cells = <0>;
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2014-03-12 21:19:24 +08:00
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compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
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2012-09-20 21:04:33 +08:00
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reg = <0x43fa8000 0x4000>;
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clocks = <&clks 102>;
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clock-names = "";
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interrupts = <24>;
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status = "disabled";
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};
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2013-11-06 16:52:17 +08:00
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iomuxc: iomuxc@43fac000 {
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2012-09-20 21:04:33 +08:00
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compatible = "fsl,imx25-iomuxc";
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reg = <0x43fac000 0x4000>;
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};
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2013-10-23 16:29:34 +08:00
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audmux: audmux@43fb0000 {
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2012-09-20 21:04:33 +08:00
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compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
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reg = <0x43fb0000 0x4000>;
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status = "disabled";
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};
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};
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spba@50000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x40000>;
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ranges;
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spi3: cspi@50004000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
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reg = <0x50004000 0x4000>;
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interrupts = <0>;
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2013-05-23 19:38:05 +08:00
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clocks = <&clks 80>, <&clks 80>;
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clock-names = "ipg", "per";
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2012-09-20 21:04:33 +08:00
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status = "disabled";
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};
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uart4: serial@50008000 {
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compatible = "fsl,imx25-uart", "fsl,imx21-uart";
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reg = <0x50008000 0x4000>;
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interrupts = <5>;
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clocks = <&clks 123>, <&clks 57>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart3: serial@5000c000 {
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compatible = "fsl,imx25-uart", "fsl,imx21-uart";
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reg = <0x5000c000 0x4000>;
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interrupts = <18>;
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clocks = <&clks 122>, <&clks 57>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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spi2: cspi@50010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
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reg = <0x50010000 0x4000>;
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2013-05-23 19:38:05 +08:00
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clocks = <&clks 79>, <&clks 79>;
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clock-names = "ipg", "per";
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2012-09-20 21:04:33 +08:00
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interrupts = <13>;
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status = "disabled";
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};
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ssi2: ssi@50014000 {
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2014-08-20 00:00:09 +08:00
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#sound-dai-cells = <0>;
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2012-09-20 21:04:33 +08:00
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compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
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reg = <0x50014000 0x4000>;
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interrupts = <11>;
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2013-10-23 16:29:32 +08:00
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clocks = <&clks 118>;
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clock-names = "ipg";
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dmas = <&sdma 24 1 0>,
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<&sdma 25 1 0>;
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dma-names = "rx", "tx";
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2012-09-20 21:04:33 +08:00
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status = "disabled";
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};
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esai@50018000 {
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reg = <0x50018000 0x4000>;
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interrupts = <7>;
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};
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uart5: serial@5002c000 {
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compatible = "fsl,imx25-uart", "fsl,imx21-uart";
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reg = <0x5002c000 0x4000>;
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interrupts = <40>;
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clocks = <&clks 124>, <&clks 57>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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tsc: tsc@50030000 {
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compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
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reg = <0x50030000 0x4000>;
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interrupts = <46>;
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clocks = <&clks 119>;
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clock-names = "ipg";
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status = "disabled";
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};
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ssi1: ssi@50034000 {
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2014-08-20 00:00:09 +08:00
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#sound-dai-cells = <0>;
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2012-09-20 21:04:33 +08:00
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compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
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reg = <0x50034000 0x4000>;
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interrupts = <12>;
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2013-10-23 16:29:32 +08:00
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clocks = <&clks 117>;
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clock-names = "ipg";
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dmas = <&sdma 28 1 0>,
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<&sdma 29 1 0>;
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dma-names = "rx", "tx";
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2012-09-20 21:04:33 +08:00
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status = "disabled";
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};
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fec: ethernet@50038000 {
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compatible = "fsl,imx25-fec";
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reg = <0x50038000 0x4000>;
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interrupts = <57>;
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clocks = <&clks 88>, <&clks 65>;
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clock-names = "ipg", "ahb";
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status = "disabled";
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};
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};
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aips@53f00000 { /* AIPS2 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x53f00000 0x100000>;
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ranges;
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clks: ccm@53f80000 {
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compatible = "fsl,imx25-ccm";
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reg = <0x53f80000 0x4000>;
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|
interrupts = <31>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpt4: timer@53f84000 {
|
|
|
|
|
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
|
|
|
|
|
reg = <0x53f84000 0x4000>;
|
2014-06-25 20:41:35 +08:00
|
|
|
clocks = <&clks 95>, <&clks 47>;
|
2012-09-20 21:04:33 +08:00
|
|
|
clock-names = "ipg", "per";
|
|
|
|
|
interrupts = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpt3: timer@53f88000 {
|
|
|
|
|
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
|
|
|
|
|
reg = <0x53f88000 0x4000>;
|
2014-06-25 20:41:35 +08:00
|
|
|
clocks = <&clks 94>, <&clks 47>;
|
2012-09-20 21:04:33 +08:00
|
|
|
clock-names = "ipg", "per";
|
|
|
|
|
interrupts = <29>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpt2: timer@53f8c000 {
|
|
|
|
|
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
|
|
|
|
|
reg = <0x53f8c000 0x4000>;
|
2014-06-25 20:41:35 +08:00
|
|
|
clocks = <&clks 93>, <&clks 47>;
|
2012-09-20 21:04:33 +08:00
|
|
|
clock-names = "ipg", "per";
|
|
|
|
|
interrupts = <53>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpt1: timer@53f90000 {
|
|
|
|
|
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
|
|
|
|
|
reg = <0x53f90000 0x4000>;
|
2014-06-25 20:41:35 +08:00
|
|
|
clocks = <&clks 92>, <&clks 47>;
|
2012-09-20 21:04:33 +08:00
|
|
|
clock-names = "ipg", "per";
|
|
|
|
|
interrupts = <54>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epit1: timer@53f94000 {
|
|
|
|
|
compatible = "fsl,imx25-epit";
|
|
|
|
|
reg = <0x53f94000 0x4000>;
|
|
|
|
|
interrupts = <28>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epit2: timer@53f98000 {
|
|
|
|
|
compatible = "fsl,imx25-epit";
|
|
|
|
|
reg = <0x53f98000 0x4000>;
|
|
|
|
|
interrupts = <27>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio4: gpio@53f9c000 {
|
|
|
|
|
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
|
|
|
|
|
reg = <0x53f9c000 0x4000>;
|
|
|
|
|
interrupts = <23>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pwm2: pwm@53fa0000 {
|
|
|
|
|
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
|
|
|
|
|
#pwm-cells = <2>;
|
|
|
|
|
reg = <0x53fa0000 0x4000>;
|
2015-01-14 21:11:03 +08:00
|
|
|
clocks = <&clks 106>, <&clks 52>;
|
2012-09-20 21:04:33 +08:00
|
|
|
clock-names = "ipg", "per";
|
|
|
|
|
interrupts = <36>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio3: gpio@53fa4000 {
|
|
|
|
|
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
|
|
|
|
|
reg = <0x53fa4000 0x4000>;
|
|
|
|
|
interrupts = <16>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pwm3: pwm@53fa8000 {
|
|
|
|
|
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
|
|
|
|
|
#pwm-cells = <2>;
|
|
|
|
|
reg = <0x53fa8000 0x4000>;
|
2015-01-14 21:11:03 +08:00
|
|
|
clocks = <&clks 107>, <&clks 52>;
|
2012-09-20 21:04:33 +08:00
|
|
|
clock-names = "ipg", "per";
|
|
|
|
|
interrupts = <41>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
esdhc1: esdhc@53fb4000 {
|
|
|
|
|
compatible = "fsl,imx25-esdhc";
|
|
|
|
|
reg = <0x53fb4000 0x4000>;
|
|
|
|
|
interrupts = <9>;
|
|
|
|
|
clocks = <&clks 86>, <&clks 63>, <&clks 45>;
|
|
|
|
|
clock-names = "ipg", "ahb", "per";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
esdhc2: esdhc@53fb8000 {
|
|
|
|
|
compatible = "fsl,imx25-esdhc";
|
|
|
|
|
reg = <0x53fb8000 0x4000>;
|
|
|
|
|
interrupts = <8>;
|
|
|
|
|
clocks = <&clks 87>, <&clks 64>, <&clks 46>;
|
|
|
|
|
clock-names = "ipg", "ahb", "per";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-07-12 15:34:54 +08:00
|
|
|
lcdc: lcdc@53fbc000 {
|
|
|
|
|
compatible = "fsl,imx25-fb", "fsl,imx21-fb";
|
2012-09-20 21:04:33 +08:00
|
|
|
reg = <0x53fbc000 0x4000>;
|
|
|
|
|
interrupts = <39>;
|
|
|
|
|
clocks = <&clks 103>, <&clks 66>, <&clks 49>;
|
|
|
|
|
clock-names = "ipg", "ahb", "per";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
slcdc@53fc0000 {
|
|
|
|
|
reg = <0x53fc0000 0x4000>;
|
|
|
|
|
interrupts = <38>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pwm4: pwm@53fc8000 {
|
|
|
|
|
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
|
|
|
|
|
reg = <0x53fc8000 0x4000>;
|
2015-01-14 21:11:03 +08:00
|
|
|
clocks = <&clks 108>, <&clks 52>;
|
2012-09-20 21:04:33 +08:00
|
|
|
clock-names = "ipg", "per";
|
|
|
|
|
interrupts = <42>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio1: gpio@53fcc000 {
|
|
|
|
|
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
|
|
|
|
|
reg = <0x53fcc000 0x4000>;
|
|
|
|
|
interrupts = <52>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio2: gpio@53fd0000 {
|
|
|
|
|
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
|
|
|
|
|
reg = <0x53fd0000 0x4000>;
|
|
|
|
|
interrupts = <51>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-23 16:29:32 +08:00
|
|
|
sdma: sdma@53fd4000 {
|
2014-08-08 03:52:38 +08:00
|
|
|
compatible = "fsl,imx25-sdma";
|
2012-09-20 21:04:33 +08:00
|
|
|
reg = <0x53fd4000 0x4000>;
|
|
|
|
|
clocks = <&clks 112>, <&clks 68>;
|
|
|
|
|
clock-names = "ipg", "ahb";
|
2013-07-02 10:15:29 +08:00
|
|
|
#dma-cells = <3>;
|
2012-09-20 21:04:33 +08:00
|
|
|
interrupts = <34>;
|
2013-10-23 16:29:33 +08:00
|
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
|
2012-09-20 21:04:33 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wdog@53fdc000 {
|
|
|
|
|
compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
|
|
|
|
|
reg = <0x53fdc000 0x4000>;
|
|
|
|
|
clocks = <&clks 126>;
|
|
|
|
|
clock-names = "";
|
|
|
|
|
interrupts = <55>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pwm1: pwm@53fe0000 {
|
|
|
|
|
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
|
|
|
|
|
#pwm-cells = <2>;
|
|
|
|
|
reg = <0x53fe0000 0x4000>;
|
2015-01-14 21:11:03 +08:00
|
|
|
clocks = <&clks 105>, <&clks 52>;
|
2012-09-20 21:04:33 +08:00
|
|
|
clock-names = "ipg", "per";
|
|
|
|
|
interrupts = <26>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-06-25 21:51:50 +08:00
|
|
|
iim: iim@53ff0000 {
|
|
|
|
|
compatible = "fsl,imx25-iim", "fsl,imx27-iim";
|
|
|
|
|
reg = <0x53ff0000 0x4000>;
|
|
|
|
|
interrupts = <19>;
|
|
|
|
|
clocks = <&clks 99>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-20 21:04:33 +08:00
|
|
|
usbotg: usb@53ff4000 {
|
|
|
|
|
compatible = "fsl,imx25-usb", "fsl,imx27-usb";
|
|
|
|
|
reg = <0x53ff4000 0x0200>;
|
|
|
|
|
interrupts = <37>;
|
2014-03-13 17:18:39 +08:00
|
|
|
clocks = <&clks 70>;
|
2012-09-20 21:04:33 +08:00
|
|
|
fsl,usbmisc = <&usbmisc 0>;
|
2014-03-13 17:18:42 +08:00
|
|
|
fsl,usbphy = <&usbphy0>;
|
2012-09-20 21:04:33 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usbhost1: usb@53ff4400 {
|
|
|
|
|
compatible = "fsl,imx25-usb", "fsl,imx27-usb";
|
|
|
|
|
reg = <0x53ff4400 0x0200>;
|
|
|
|
|
interrupts = <35>;
|
2014-03-13 17:18:39 +08:00
|
|
|
clocks = <&clks 70>;
|
2012-09-20 21:04:33 +08:00
|
|
|
fsl,usbmisc = <&usbmisc 1>;
|
2014-03-13 17:18:42 +08:00
|
|
|
fsl,usbphy = <&usbphy1>;
|
2012-09-20 21:04:33 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usbmisc: usbmisc@53ff4600 {
|
|
|
|
|
#index-cells = <1>;
|
|
|
|
|
compatible = "fsl,imx25-usbmisc";
|
|
|
|
|
clocks = <&clks 9>, <&clks 70>, <&clks 8>;
|
|
|
|
|
clock-names = "ipg", "ahb", "per";
|
|
|
|
|
reg = <0x53ff4600 0x00f>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dryice@53ffc000 {
|
|
|
|
|
compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
|
|
|
|
|
reg = <0x53ffc000 0x4000>;
|
|
|
|
|
clocks = <&clks 81>;
|
|
|
|
|
clock-names = "ipg";
|
|
|
|
|
interrupts = <25>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2014-05-09 14:11:16 +08:00
|
|
|
iram: sram@78000000 {
|
|
|
|
|
compatible = "mmio-sram";
|
|
|
|
|
reg = <0x78000000 0x20000>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-20 21:04:33 +08:00
|
|
|
emi@80000000 {
|
|
|
|
|
compatible = "fsl,emi-bus", "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
reg = <0x80000000 0x3b002000>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
2012-12-31 11:32:48 +08:00
|
|
|
nfc: nand@bb000000 {
|
2012-09-20 21:04:33 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
|
|
|
|
|
compatible = "fsl,imx25-nand";
|
|
|
|
|
reg = <0xbb000000 0x2000>;
|
|
|
|
|
clocks = <&clks 50>;
|
|
|
|
|
clock-names = "";
|
|
|
|
|
interrupts = <33>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2014-03-13 17:18:42 +08:00
|
|
|
|
|
|
|
|
usbphy {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
usbphy0: usb-phy@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
compatible = "usb-nop-xceiv";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usbphy1: usb-phy@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
compatible = "usb-nop-xceiv";
|
|
|
|
|
};
|
|
|
|
|
};
|
2012-09-20 21:04:33 +08:00
|
|
|
};
|
