2019-01-22 02:05:50 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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2014-08-28 08:04:47 +08:00
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/*
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* Broadcom UniMAC MDIO bus controller driver
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*
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2017-03-14 08:41:42 +08:00
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* Copyright (C) 2014-2017 Broadcom
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2014-08-28 08:04:47 +08:00
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*/
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#include <linux/kernel.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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2018-09-21 08:05:40 +08:00
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#include <linux/clk.h>
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2014-08-28 08:04:47 +08:00
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_mdio.h>
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2017-08-01 03:04:25 +08:00
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#include <linux/platform_data/mdio-bcm-unimac.h>
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2014-08-28 08:04:47 +08:00
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#define MDIO_CMD 0x00
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#define MDIO_START_BUSY (1 << 29)
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#define MDIO_READ_FAIL (1 << 28)
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#define MDIO_RD (2 << 26)
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#define MDIO_WR (1 << 26)
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#define MDIO_PMD_SHIFT 21
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#define MDIO_PMD_MASK 0x1F
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#define MDIO_REG_SHIFT 16
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#define MDIO_REG_MASK 0x1F
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#define MDIO_CFG 0x04
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#define MDIO_C22 (1 << 0)
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#define MDIO_C45 0
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#define MDIO_CLK_DIV_SHIFT 4
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#define MDIO_CLK_DIV_MASK 0x3F
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#define MDIO_SUPP_PREAMBLE (1 << 12)
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struct unimac_mdio_priv {
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struct mii_bus *mii_bus;
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void __iomem *base;
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2017-08-01 03:04:25 +08:00
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int (*wait_func) (void *wait_func_data);
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void *wait_func_data;
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2018-09-21 08:05:40 +08:00
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struct clk *clk;
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u32 clk_freq;
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2014-08-28 08:04:47 +08:00
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};
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2017-08-30 04:35:18 +08:00
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static inline u32 unimac_mdio_readl(struct unimac_mdio_priv *priv, u32 offset)
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{
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/* MIPS chips strapped for BE will automagically configure the
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* peripheral registers for CPU-native byte order.
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*/
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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return __raw_readl(priv->base + offset);
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else
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return readl_relaxed(priv->base + offset);
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}
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static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val,
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u32 offset)
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{
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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__raw_writel(val, priv->base + offset);
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else
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writel_relaxed(val, priv->base + offset);
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}
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2014-08-28 08:04:47 +08:00
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static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
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{
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u32 reg;
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2017-08-30 04:35:18 +08:00
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reg = unimac_mdio_readl(priv, MDIO_CMD);
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2014-08-28 08:04:47 +08:00
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reg |= MDIO_START_BUSY;
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2017-08-30 04:35:18 +08:00
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unimac_mdio_writel(priv, reg, MDIO_CMD);
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2014-08-28 08:04:47 +08:00
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}
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static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)
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{
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2017-08-30 04:35:18 +08:00
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return unimac_mdio_readl(priv, MDIO_CMD) & MDIO_START_BUSY;
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2014-08-28 08:04:47 +08:00
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}
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2017-08-01 03:04:25 +08:00
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static int unimac_mdio_poll(void *wait_func_data)
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2017-08-01 03:04:22 +08:00
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{
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2017-08-01 03:04:25 +08:00
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struct unimac_mdio_priv *priv = wait_func_data;
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2017-08-01 03:04:22 +08:00
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unsigned int timeout = 1000;
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do {
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if (!unimac_mdio_busy(priv))
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return 0;
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usleep_range(1000, 2000);
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2017-08-08 17:52:32 +08:00
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} while (--timeout);
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2017-08-01 03:04:22 +08:00
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2019-03-28 00:15:20 +08:00
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return -ETIMEDOUT;
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2017-08-01 03:04:22 +08:00
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}
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2014-08-28 08:04:47 +08:00
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static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
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{
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struct unimac_mdio_priv *priv = bus->priv;
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2017-08-01 03:04:25 +08:00
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int ret;
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2014-08-28 08:04:47 +08:00
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u32 cmd;
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/* Prepare the read operation */
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cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
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2017-08-30 04:35:18 +08:00
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unimac_mdio_writel(priv, cmd, MDIO_CMD);
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2014-08-28 08:04:47 +08:00
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/* Start MDIO transaction */
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unimac_mdio_start(priv);
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2017-08-01 03:04:25 +08:00
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ret = priv->wait_func(priv->wait_func_data);
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2017-08-01 03:04:22 +08:00
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if (ret)
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return ret;
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2014-08-28 08:04:47 +08:00
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2017-08-30 04:35:18 +08:00
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cmd = unimac_mdio_readl(priv, MDIO_CMD);
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2015-06-11 03:24:11 +08:00
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/* Some broken devices are known not to release the line during
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* turn-around, e.g: Broadcom BCM53125 external switches, so check for
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* that condition here and ignore the MDIO controller read failure
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* indication.
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*/
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if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL))
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2014-08-28 08:04:47 +08:00
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return -EIO;
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return cmd & 0xffff;
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}
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static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
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int reg, u16 val)
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{
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struct unimac_mdio_priv *priv = bus->priv;
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u32 cmd;
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/* Prepare the write operation */
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cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
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(reg << MDIO_REG_SHIFT) | (0xffff & val);
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2017-08-30 04:35:18 +08:00
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unimac_mdio_writel(priv, cmd, MDIO_CMD);
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2014-08-28 08:04:47 +08:00
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unimac_mdio_start(priv);
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2017-08-01 03:04:25 +08:00
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return priv->wait_func(priv->wait_func_data);
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2014-08-28 08:04:47 +08:00
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}
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2015-06-27 01:39:06 +08:00
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/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
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* their internal MDIO management controller making them fail to successfully
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* be read from or written to for the first transaction. We insert a dummy
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* BMSR read here to make sure that phy_get_device() and get_phy_id() can
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* correctly read the PHY MII_PHYSID1/2 registers and successfully register a
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* PHY device for this peripheral.
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*
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* Once the PHY driver is registered, we can workaround subsequent reads from
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* there (e.g: during system-wide power management).
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*
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* bus->reset is invoked before mdiobus_scan during mdiobus_register and is
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* therefore the right location to stick that workaround. Since we do not want
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* to read from non-existing PHYs, we either use bus->phy_mask or do a manual
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* Device Tree scan to limit the search area.
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*/
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static int unimac_mdio_reset(struct mii_bus *bus)
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{
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struct device_node *np = bus->dev.of_node;
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struct device_node *child;
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u32 read_mask = 0;
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int addr;
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if (!np) {
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read_mask = ~bus->phy_mask;
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} else {
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for_each_available_child_of_node(np, child) {
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addr = of_mdio_parse_addr(&bus->dev, child);
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if (addr < 0)
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continue;
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read_mask |= 1 << addr;
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}
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}
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for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
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2017-08-01 03:04:24 +08:00
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if (read_mask & 1 << addr) {
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dev_dbg(&bus->dev, "Workaround for PHY @ %d\n", addr);
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2015-06-27 01:39:06 +08:00
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mdiobus_read(bus, addr, MII_BMSR);
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2017-08-01 03:04:24 +08:00
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}
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2015-06-27 01:39:06 +08:00
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}
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return 0;
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}
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2018-09-21 08:05:40 +08:00
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static void unimac_mdio_clk_set(struct unimac_mdio_priv *priv)
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{
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unsigned long rate;
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u32 reg, div;
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/* Keep the hardware default values */
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if (!priv->clk_freq)
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return;
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if (!priv->clk)
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rate = 250000000;
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else
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rate = clk_get_rate(priv->clk);
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div = (rate / (2 * priv->clk_freq)) - 1;
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if (div & ~MDIO_CLK_DIV_MASK) {
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pr_warn("Incorrect MDIO clock frequency, ignoring\n");
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return;
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}
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/* The MDIO clock is the reference clock (typicaly 250Mhz) divided by
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* 2 x (MDIO_CLK_DIV + 1)
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*/
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reg = unimac_mdio_readl(priv, MDIO_CFG);
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reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT);
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reg |= div << MDIO_CLK_DIV_SHIFT;
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unimac_mdio_writel(priv, reg, MDIO_CFG);
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}
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2014-08-28 08:04:47 +08:00
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static int unimac_mdio_probe(struct platform_device *pdev)
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{
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2017-08-01 03:04:25 +08:00
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struct unimac_mdio_pdata *pdata = pdev->dev.platform_data;
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2014-08-28 08:04:47 +08:00
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struct unimac_mdio_priv *priv;
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struct device_node *np;
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struct mii_bus *bus;
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struct resource *r;
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int ret;
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np = pdev->dev.of_node;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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net: phy: mdio-bcm-unimac: fix potential NULL dereference in unimac_mdio_probe()
platform_get_resource() may fail and return NULL, so we should
better check it's return value to avoid a NULL pointer dereference
a bit later in the code.
This is detected by Coccinelle semantic patch.
@@
expression pdev, res, n, t, e, e1, e2;
@@
res = platform_get_resource(pdev, t, n);
+ if (!res)
+ return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-01-11 19:21:51 +08:00
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if (!r)
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return -EINVAL;
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2014-08-28 08:04:47 +08:00
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/* Just ioremap, as this MDIO block is usually integrated into an
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* Ethernet MAC controller register range
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*/
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priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
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if (!priv->base) {
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dev_err(&pdev->dev, "failed to remap register\n");
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return -ENOMEM;
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}
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2020-03-25 00:10:10 +08:00
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priv->clk = devm_clk_get_optional(&pdev->dev, NULL);
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if (IS_ERR(priv->clk))
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2018-09-21 08:05:40 +08:00
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return PTR_ERR(priv->clk);
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))
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priv->clk_freq = 0;
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unimac_mdio_clk_set(priv);
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2014-08-28 08:04:47 +08:00
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priv->mii_bus = mdiobus_alloc();
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2018-09-21 08:05:40 +08:00
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if (!priv->mii_bus) {
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ret = -ENOMEM;
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goto out_clk_disable;
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}
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2014-08-28 08:04:47 +08:00
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bus = priv->mii_bus;
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bus->priv = priv;
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2017-08-01 03:04:25 +08:00
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if (pdata) {
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bus->name = pdata->bus_name;
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priv->wait_func = pdata->wait_func;
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priv->wait_func_data = pdata->wait_func_data;
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bus->phy_mask = ~pdata->phy_mask;
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} else {
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bus->name = "unimac MII bus";
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priv->wait_func_data = priv;
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priv->wait_func = unimac_mdio_poll;
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}
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2014-08-28 08:04:47 +08:00
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bus->parent = &pdev->dev;
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bus->read = unimac_mdio_read;
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bus->write = unimac_mdio_write;
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2015-06-27 01:39:06 +08:00
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bus->reset = unimac_mdio_reset;
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2017-08-01 03:04:23 +08:00
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
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2014-08-28 08:04:47 +08:00
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ret = of_mdiobus_register(bus, np);
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if (ret) {
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dev_err(&pdev->dev, "MDIO bus registration failed\n");
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2016-01-07 03:11:15 +08:00
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goto out_mdio_free;
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2014-08-28 08:04:47 +08:00
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}
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platform_set_drvdata(pdev, priv);
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2019-03-21 00:45:15 +08:00
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dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus\n");
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2014-08-28 08:04:47 +08:00
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return 0;
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out_mdio_free:
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mdiobus_free(bus);
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2018-09-21 08:05:40 +08:00
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out_clk_disable:
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clk_disable_unprepare(priv->clk);
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2014-08-28 08:04:47 +08:00
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return ret;
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}
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static int unimac_mdio_remove(struct platform_device *pdev)
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{
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struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
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mdiobus_unregister(priv->mii_bus);
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mdiobus_free(priv->mii_bus);
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2018-09-21 08:05:40 +08:00
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clk_disable_unprepare(priv->clk);
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return 0;
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}
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2018-09-26 21:14:10 +08:00
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static int __maybe_unused unimac_mdio_suspend(struct device *d)
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2018-09-21 08:05:40 +08:00
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{
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struct unimac_mdio_priv *priv = dev_get_drvdata(d);
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clk_disable_unprepare(priv->clk);
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return 0;
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}
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2018-09-26 21:14:10 +08:00
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static int __maybe_unused unimac_mdio_resume(struct device *d)
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2018-09-21 08:05:40 +08:00
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{
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struct unimac_mdio_priv *priv = dev_get_drvdata(d);
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int ret;
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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unimac_mdio_clk_set(priv);
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2014-08-28 08:04:47 +08:00
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return 0;
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}
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2018-09-21 08:05:40 +08:00
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static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops,
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unimac_mdio_suspend, unimac_mdio_resume);
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2015-03-18 02:40:23 +08:00
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static const struct of_device_id unimac_mdio_ids[] = {
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2017-03-14 08:41:42 +08:00
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{ .compatible = "brcm,genet-mdio-v5", },
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2014-08-28 08:04:47 +08:00
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{ .compatible = "brcm,genet-mdio-v4", },
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{ .compatible = "brcm,genet-mdio-v3", },
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{ .compatible = "brcm,genet-mdio-v2", },
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{ .compatible = "brcm,genet-mdio-v1", },
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{ .compatible = "brcm,unimac-mdio", },
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2014-08-30 03:43:56 +08:00
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{ /* sentinel */ },
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2014-08-28 08:04:47 +08:00
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};
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2015-09-19 00:16:12 +08:00
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MODULE_DEVICE_TABLE(of, unimac_mdio_ids);
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2014-08-28 08:04:47 +08:00
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static struct platform_driver unimac_mdio_driver = {
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.driver = {
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2017-08-01 03:04:25 +08:00
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.name = UNIMAC_MDIO_DRV_NAME,
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2014-08-28 08:04:47 +08:00
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.of_match_table = unimac_mdio_ids,
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2018-09-21 08:05:40 +08:00
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.pm = &unimac_mdio_pm_ops,
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2014-08-28 08:04:47 +08:00
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},
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.probe = unimac_mdio_probe,
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.remove = unimac_mdio_remove,
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};
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module_platform_driver(unimac_mdio_driver);
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MODULE_AUTHOR("Broadcom Corporation");
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MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
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MODULE_LICENSE("GPL");
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2017-08-01 03:04:25 +08:00
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MODULE_ALIAS("platform:" UNIMAC_MDIO_DRV_NAME);
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