2009-12-11 17:24:15 +08:00
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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2010-09-01 13:24:34 +08:00
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#include "nouveau_ramht.h"
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2009-12-11 17:24:15 +08:00
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/* returns the size of fifo context */
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static int
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nouveau_fifo_ctx_size(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (dev_priv->chipset >= 0x40)
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return 128;
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else
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if (dev_priv->chipset >= 0x17)
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return 64;
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return 32;
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}
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int nv04_instmem_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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2010-09-01 13:24:34 +08:00
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struct nouveau_gpuobj *ramht = NULL;
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2010-09-01 13:24:35 +08:00
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u32 offset, length;
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2010-06-01 13:32:24 +08:00
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int ret;
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2009-12-11 17:24:15 +08:00
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2010-09-07 02:25:28 +08:00
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/* RAMIN always available */
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dev_priv->ramin_available = true;
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2010-09-01 13:24:34 +08:00
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/* Setup shared RAMHT */
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2010-09-01 13:24:35 +08:00
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ret = nouveau_gpuobj_new_fake(dev, 0x10000, ~0, 4096,
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2010-09-01 13:24:34 +08:00
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NVOBJ_FLAG_ZERO_ALLOC, &ramht);
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if (ret)
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return ret;
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ret = nouveau_ramht_new(dev, ramht, &dev_priv->ramht);
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nouveau_gpuobj_ref(NULL, &ramht);
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if (ret)
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return ret;
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2010-09-01 13:24:35 +08:00
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/* And RAMRO */
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ret = nouveau_gpuobj_new_fake(dev, 0x11200, ~0, 512,
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NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramro);
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if (ret)
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return ret;
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/* And RAMFC */
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length = dev_priv->engine.fifo.channels * nouveau_fifo_ctx_size(dev);
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switch (dev_priv->card_type) {
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case NV_40:
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offset = 0x20000;
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break;
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default:
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offset = 0x11400;
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break;
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}
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ret = nouveau_gpuobj_new_fake(dev, offset, ~0, length,
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NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramfc);
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if (ret)
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return ret;
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/* Only allow space after RAMFC to be used for object allocation */
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offset += length;
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2009-12-11 17:24:15 +08:00
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/* It appears RAMRO (or something?) is controlled by 0x2220/0x2230
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* on certain NV4x chipsets as well as RAMFC. When 0x2230 == 0
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* ("new style" control) the upper 16-bits of 0x2220 points at this
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* other mysterious table that's clobbering important things.
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*
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* We're now pointing this at RAMIN+0x30000 to avoid RAMFC getting
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* smashed to pieces on us, so reserve 0x30000-0x40000 too..
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*/
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if (dev_priv->card_type >= NV_40) {
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if (offset < 0x40000)
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offset = 0x40000;
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}
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2010-06-01 13:32:24 +08:00
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ret = drm_mm_init(&dev_priv->ramin_heap, offset,
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dev_priv->ramin_rsvd_vram - offset);
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2009-12-11 17:24:15 +08:00
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if (ret) {
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2010-06-01 13:32:24 +08:00
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NV_ERROR(dev, "Failed to init RAMIN heap: %d\n", ret);
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return ret;
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2009-12-11 17:24:15 +08:00
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}
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2010-06-01 13:32:24 +08:00
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return 0;
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2009-12-11 17:24:15 +08:00
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}
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void
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nv04_instmem_takedown(struct drm_device *dev)
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{
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2010-09-01 13:24:35 +08:00
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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nouveau_ramht_ref(NULL, &dev_priv->ramht, NULL);
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nouveau_gpuobj_ref(NULL, &dev_priv->ramro);
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nouveau_gpuobj_ref(NULL, &dev_priv->ramfc);
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2009-12-11 17:24:15 +08:00
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}
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int
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2010-09-01 13:24:32 +08:00
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nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
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uint32_t *sz)
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2009-12-11 17:24:15 +08:00
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{
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return 0;
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}
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void
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nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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}
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int
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nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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return 0;
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}
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int
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nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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return 0;
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}
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void
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2010-07-08 09:29:10 +08:00
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nv04_instmem_flush(struct drm_device *dev)
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2009-12-11 17:24:15 +08:00
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{
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}
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int
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nv04_instmem_suspend(struct drm_device *dev)
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{
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return 0;
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}
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void
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nv04_instmem_resume(struct drm_device *dev)
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{
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}
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