2017-12-04 22:07:36 +08:00
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/*
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* Copyright(c) 2017 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* This code is based in part on work published here:
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*
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* https://github.com/IAIK/KAISER
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*
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* The original work was written by and and signed off by for the Linux
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* kernel by:
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*
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* Signed-off-by: Richard Fellner <richard.fellner@student.tugraz.at>
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* Signed-off-by: Moritz Lipp <moritz.lipp@iaik.tugraz.at>
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* Signed-off-by: Daniel Gruss <daniel.gruss@iaik.tugraz.at>
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* Signed-off-by: Michael Schwarz <michael.schwarz@iaik.tugraz.at>
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*
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* Major changes to the original code by: Dave Hansen <dave.hansen@intel.com>
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* Mostly rewritten by Thomas Gleixner <tglx@linutronix.de> and
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* Andy Lutomirsky <luto@amacapital.net>
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/bug.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/uaccess.h>
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#include <asm/cpufeature.h>
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#include <asm/hypervisor.h>
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2017-12-12 23:56:42 +08:00
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#include <asm/vsyscall.h>
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2017-12-04 22:07:36 +08:00
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#include <asm/cmdline.h>
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#include <asm/pti.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/desc.h>
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#undef pr_fmt
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#define pr_fmt(fmt) "Kernel/User page tables isolation: " fmt
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2017-12-04 22:07:42 +08:00
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/* Backporting helper */
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#ifndef __GFP_NOTRACK
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#define __GFP_NOTRACK 0
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#endif
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2017-12-04 22:07:36 +08:00
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static void __init pti_print_if_insecure(const char *reason)
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{
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2018-01-05 22:27:34 +08:00
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if (boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
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2017-12-04 22:07:36 +08:00
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pr_info("%s\n", reason);
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}
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2017-12-12 21:39:52 +08:00
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static void __init pti_print_if_secure(const char *reason)
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{
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2018-01-05 22:27:34 +08:00
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if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
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2017-12-12 21:39:52 +08:00
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pr_info("%s\n", reason);
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}
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2018-04-07 04:55:18 +08:00
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enum pti_mode {
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PTI_AUTO = 0,
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PTI_FORCE_OFF,
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PTI_FORCE_ON
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} pti_mode;
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2017-12-04 22:07:36 +08:00
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void __init pti_check_boottime_disable(void)
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{
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2017-12-12 21:39:52 +08:00
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char arg[5];
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int ret;
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2018-04-07 04:55:18 +08:00
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/* Assume mode is auto unless overridden. */
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pti_mode = PTI_AUTO;
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2017-12-04 22:07:36 +08:00
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if (hypervisor_is_type(X86_HYPER_XEN_PV)) {
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2018-04-07 04:55:18 +08:00
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pti_mode = PTI_FORCE_OFF;
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2017-12-04 22:07:36 +08:00
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pti_print_if_insecure("disabled on XEN PV.");
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return;
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}
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2017-12-12 21:39:52 +08:00
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ret = cmdline_find_option(boot_command_line, "pti", arg, sizeof(arg));
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if (ret > 0) {
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if (ret == 3 && !strncmp(arg, "off", 3)) {
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2018-04-07 04:55:18 +08:00
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pti_mode = PTI_FORCE_OFF;
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2017-12-12 21:39:52 +08:00
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pti_print_if_insecure("disabled on command line.");
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return;
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}
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if (ret == 2 && !strncmp(arg, "on", 2)) {
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2018-04-07 04:55:18 +08:00
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pti_mode = PTI_FORCE_ON;
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2017-12-12 21:39:52 +08:00
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pti_print_if_secure("force enabled on command line.");
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goto enable;
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}
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2018-04-07 04:55:18 +08:00
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if (ret == 4 && !strncmp(arg, "auto", 4)) {
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pti_mode = PTI_AUTO;
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2017-12-12 21:39:52 +08:00
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goto autosel;
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2018-04-07 04:55:18 +08:00
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}
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2017-12-12 21:39:52 +08:00
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}
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2017-12-04 22:07:36 +08:00
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if (cmdline_find_option_bool(boot_command_line, "nopti")) {
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2018-04-07 04:55:18 +08:00
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pti_mode = PTI_FORCE_OFF;
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2017-12-04 22:07:36 +08:00
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pti_print_if_insecure("disabled on command line.");
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return;
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}
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2017-12-12 21:39:52 +08:00
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autosel:
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2018-01-05 22:27:34 +08:00
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if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
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2017-12-04 22:07:36 +08:00
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return;
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2017-12-12 21:39:52 +08:00
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enable:
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2017-12-04 22:07:36 +08:00
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setup_force_cpu_cap(X86_FEATURE_PTI);
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}
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2017-12-04 22:07:37 +08:00
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pgd_t __pti_set_user_pgd(pgd_t *pgdp, pgd_t pgd)
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{
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/*
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* Changes to the high (kernel) portion of the kernelmode page
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* tables are not automatically propagated to the usermode tables.
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*
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* Users should keep in mind that, unlike the kernelmode tables,
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* there is no vmalloc_fault equivalent for the usermode tables.
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* Top-level entries added to init_mm's usermode pgd after boot
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* will not be automatically propagated to other mms.
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*/
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if (!pgdp_maps_userspace(pgdp))
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return pgd;
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/*
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* The user page tables get the full PGD, accessible from
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* userspace:
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*/
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kernel_to_user_pgdp(pgdp)->pgd = pgd.pgd;
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/*
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* If this is normal user memory, make it NX in the kernel
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* pagetables so that, if we somehow screw up and return to
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* usermode with the kernel CR3 loaded, we'll get a page fault
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* instead of allowing user code to execute with the wrong CR3.
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*
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* As exceptions, we don't set NX if:
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* - _PAGE_USER is not set. This could be an executable
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* EFI runtime mapping or something similar, and the kernel
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* may execute from it
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* - we don't have NX support
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* - we're clearing the PGD (i.e. the new pgd is not present).
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*/
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if ((pgd.pgd & (_PAGE_USER|_PAGE_PRESENT)) == (_PAGE_USER|_PAGE_PRESENT) &&
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(__supported_pte_mask & _PAGE_NX))
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pgd.pgd |= _PAGE_NX;
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/* return the copy of the PGD we want the kernel to use: */
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return pgd;
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}
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2017-12-04 22:07:42 +08:00
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/*
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* Walk the user copy of the page tables (optionally) trying to allocate
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* page table pages on the way down.
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*
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* Returns a pointer to a P4D on success, or NULL on failure.
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*/
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2018-04-07 04:55:18 +08:00
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static p4d_t *pti_user_pagetable_walk_p4d(unsigned long address)
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2017-12-04 22:07:42 +08:00
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{
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pgd_t *pgd = kernel_to_user_pgdp(pgd_offset_k(address));
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gfp_t gfp = (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
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if (address < PAGE_OFFSET) {
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WARN_ONCE(1, "attempt to walk user address\n");
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return NULL;
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}
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if (pgd_none(*pgd)) {
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unsigned long new_p4d_page = __get_free_page(gfp);
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if (!new_p4d_page)
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return NULL;
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2018-01-09 00:03:41 +08:00
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set_pgd(pgd, __pgd(_KERNPG_TABLE | __pa(new_p4d_page)));
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2017-12-04 22:07:42 +08:00
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}
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BUILD_BUG_ON(pgd_large(*pgd) != 0);
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return p4d_offset(pgd, address);
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}
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/*
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* Walk the user copy of the page tables (optionally) trying to allocate
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* page table pages on the way down.
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*
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* Returns a pointer to a PMD on success, or NULL on failure.
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*/
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2018-04-07 04:55:18 +08:00
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static pmd_t *pti_user_pagetable_walk_pmd(unsigned long address)
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2017-12-04 22:07:42 +08:00
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{
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gfp_t gfp = (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
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p4d_t *p4d = pti_user_pagetable_walk_p4d(address);
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pud_t *pud;
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BUILD_BUG_ON(p4d_large(*p4d) != 0);
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if (p4d_none(*p4d)) {
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unsigned long new_pud_page = __get_free_page(gfp);
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if (!new_pud_page)
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return NULL;
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2018-01-09 00:03:41 +08:00
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set_p4d(p4d, __p4d(_KERNPG_TABLE | __pa(new_pud_page)));
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2017-12-04 22:07:42 +08:00
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}
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pud = pud_offset(p4d, address);
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/* The user page tables do not use large mappings: */
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if (pud_large(*pud)) {
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WARN_ON(1);
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return NULL;
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}
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if (pud_none(*pud)) {
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unsigned long new_pmd_page = __get_free_page(gfp);
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if (!new_pmd_page)
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return NULL;
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2018-01-09 00:03:41 +08:00
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set_pud(pud, __pud(_KERNPG_TABLE | __pa(new_pmd_page)));
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2017-12-04 22:07:42 +08:00
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}
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return pmd_offset(pud, address);
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}
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2017-12-12 23:56:42 +08:00
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#ifdef CONFIG_X86_VSYSCALL_EMULATION
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/*
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* Walk the shadow copy of the page tables (optionally) trying to allocate
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* page table pages on the way down. Does not support large pages.
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*
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* Note: this is only used when mapping *new* kernel data into the
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* user/shadow page tables. It is never used for userspace data.
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*
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* Returns a pointer to a PTE on success, or NULL on failure.
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*/
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static __init pte_t *pti_user_pagetable_walk_pte(unsigned long address)
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{
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gfp_t gfp = (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
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pmd_t *pmd = pti_user_pagetable_walk_pmd(address);
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pte_t *pte;
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/* We can't do anything sensible if we hit a large mapping. */
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if (pmd_large(*pmd)) {
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WARN_ON(1);
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return NULL;
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}
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if (pmd_none(*pmd)) {
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unsigned long new_pte_page = __get_free_page(gfp);
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if (!new_pte_page)
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return NULL;
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2018-01-09 00:03:41 +08:00
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set_pmd(pmd, __pmd(_KERNPG_TABLE | __pa(new_pte_page)));
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2017-12-12 23:56:42 +08:00
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}
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pte = pte_offset_kernel(pmd, address);
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if (pte_flags(*pte) & _PAGE_USER) {
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WARN_ONCE(1, "attempt to walk to user pte\n");
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return NULL;
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}
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return pte;
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}
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static void __init pti_setup_vsyscall(void)
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{
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pte_t *pte, *target_pte;
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unsigned int level;
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pte = lookup_address(VSYSCALL_ADDR, &level);
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if (!pte || WARN_ON(level != PG_LEVEL_4K) || pte_none(*pte))
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return;
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target_pte = pti_user_pagetable_walk_pte(VSYSCALL_ADDR);
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if (WARN_ON(!target_pte))
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return;
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*target_pte = *pte;
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set_vsyscall_pgtable_user_bits(kernel_to_user_pgdp(swapper_pg_dir));
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}
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#else
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static void __init pti_setup_vsyscall(void) { }
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#endif
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2018-04-07 04:55:18 +08:00
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static void
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2017-12-04 22:07:42 +08:00
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pti_clone_pmds(unsigned long start, unsigned long end, pmdval_t clear)
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{
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unsigned long addr;
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/*
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* Clone the populated PMDs which cover start to end. These PMD areas
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* can have holes.
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*/
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for (addr = start; addr < end; addr += PMD_SIZE) {
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pmd_t *pmd, *target_pmd;
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pgd_t *pgd;
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p4d_t *p4d;
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pud_t *pud;
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pgd = pgd_offset_k(addr);
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if (WARN_ON(pgd_none(*pgd)))
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return;
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p4d = p4d_offset(pgd, addr);
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if (WARN_ON(p4d_none(*p4d)))
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return;
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pud = pud_offset(p4d, addr);
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if (pud_none(*pud))
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continue;
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pmd = pmd_offset(pud, addr);
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if (pmd_none(*pmd))
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continue;
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target_pmd = pti_user_pagetable_walk_pmd(addr);
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if (WARN_ON(!target_pmd))
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return;
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2018-04-07 04:55:15 +08:00
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/*
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* Only clone present PMDs. This ensures only setting
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* _PAGE_GLOBAL on present PMDs. This should only be
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* called on well-known addresses anyway, so a non-
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* present PMD would be a surprise.
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*/
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if (WARN_ON(!(pmd_flags(*pmd) & _PAGE_PRESENT)))
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return;
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/*
|
|
|
|
* Setting 'target_pmd' below creates a mapping in both
|
|
|
|
* the user and kernel page tables. It is effectively
|
|
|
|
* global, so set it as global in both copies. Note:
|
|
|
|
* the X86_FEATURE_PGE check is not _required_ because
|
|
|
|
* the CPU ignores _PAGE_GLOBAL when PGE is not
|
|
|
|
* supported. The check keeps consistentency with
|
|
|
|
* code that only set this bit when supported.
|
|
|
|
*/
|
|
|
|
if (boot_cpu_has(X86_FEATURE_PGE))
|
|
|
|
*pmd = pmd_set_flags(*pmd, _PAGE_GLOBAL);
|
|
|
|
|
2017-12-04 22:07:42 +08:00
|
|
|
/*
|
|
|
|
* Copy the PMD. That is, the kernelmode and usermode
|
|
|
|
* tables will share the last-level page tables of this
|
|
|
|
* address range
|
|
|
|
*/
|
|
|
|
*target_pmd = pmd_clear_flags(*pmd, clear);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-12-04 22:07:45 +08:00
|
|
|
/*
|
|
|
|
* Clone a single p4d (i.e. a top-level entry on 4-level systems and a
|
|
|
|
* next-level entry on 5-level systems.
|
|
|
|
*/
|
|
|
|
static void __init pti_clone_p4d(unsigned long addr)
|
|
|
|
{
|
|
|
|
p4d_t *kernel_p4d, *user_p4d;
|
|
|
|
pgd_t *kernel_pgd;
|
|
|
|
|
|
|
|
user_p4d = pti_user_pagetable_walk_p4d(addr);
|
|
|
|
kernel_pgd = pgd_offset_k(addr);
|
|
|
|
kernel_p4d = p4d_offset(kernel_pgd, addr);
|
|
|
|
*user_p4d = *kernel_p4d;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clone the CPU_ENTRY_AREA into the user space visible page table.
|
|
|
|
*/
|
|
|
|
static void __init pti_clone_user_shared(void)
|
|
|
|
{
|
|
|
|
pti_clone_p4d(CPU_ENTRY_AREA_BASE);
|
|
|
|
}
|
|
|
|
|
2017-12-16 05:08:18 +08:00
|
|
|
/*
|
2018-03-07 12:32:15 +08:00
|
|
|
* Clone the ESPFIX P4D into the user space visible page table
|
2017-12-16 05:08:18 +08:00
|
|
|
*/
|
|
|
|
static void __init pti_setup_espfix64(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_X86_ESPFIX64
|
|
|
|
pti_clone_p4d(ESPFIX_BASE_ADDR);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-12-04 22:07:47 +08:00
|
|
|
/*
|
|
|
|
* Clone the populated PMDs of the entry and irqentry text and force it RO.
|
|
|
|
*/
|
|
|
|
static void __init pti_clone_entry_text(void)
|
|
|
|
{
|
|
|
|
pti_clone_pmds((unsigned long) __entry_text_start,
|
2018-01-03 22:57:59 +08:00
|
|
|
(unsigned long) __irqentry_text_end,
|
2018-04-07 04:55:15 +08:00
|
|
|
_PAGE_RW);
|
2017-12-04 22:07:47 +08:00
|
|
|
}
|
|
|
|
|
2018-04-07 04:55:18 +08:00
|
|
|
/*
|
|
|
|
* Global pages and PCIDs are both ways to make kernel TLB entries
|
|
|
|
* live longer, reduce TLB misses and improve kernel performance.
|
|
|
|
* But, leaving all kernel text Global makes it potentially accessible
|
|
|
|
* to Meltdown-style attacks which make it trivial to find gadgets or
|
|
|
|
* defeat KASLR.
|
|
|
|
*
|
|
|
|
* Only use global pages when it is really worth it.
|
|
|
|
*/
|
|
|
|
static inline bool pti_kernel_image_global_ok(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Systems with PCIDs get litlle benefit from global
|
|
|
|
* kernel text and are not worth the downsides.
|
|
|
|
*/
|
|
|
|
if (cpu_feature_enabled(X86_FEATURE_PCID))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only do global kernel image for pti=auto. Do the most
|
|
|
|
* secure thing (not global) if pti=on specified.
|
|
|
|
*/
|
|
|
|
if (pti_mode != PTI_AUTO)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* K8 may not tolerate the cleared _PAGE_RW on the userspace
|
|
|
|
* global kernel image pages. Do the safe thing (disable
|
|
|
|
* global kernel image). This is unlikely to ever be
|
|
|
|
* noticed because PTI is disabled by default on AMD CPUs.
|
|
|
|
*/
|
|
|
|
if (boot_cpu_has(X86_FEATURE_K8))
|
|
|
|
return false;
|
|
|
|
|
2018-04-21 06:20:26 +08:00
|
|
|
/*
|
|
|
|
* RANDSTRUCT derives its hardening benefits from the
|
|
|
|
* attacker's lack of knowledge about the layout of kernel
|
|
|
|
* data structures. Keep the kernel image non-global in
|
|
|
|
* cases where RANDSTRUCT is in use to help keep the layout a
|
|
|
|
* secret.
|
|
|
|
*/
|
|
|
|
if (IS_ENABLED(CONFIG_GCC_PLUGIN_RANDSTRUCT))
|
|
|
|
return false;
|
|
|
|
|
2018-04-07 04:55:18 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For some configurations, map all of kernel text into the user page
|
|
|
|
* tables. This reduces TLB misses, especially on non-PCID systems.
|
|
|
|
*/
|
|
|
|
void pti_clone_kernel_text(void)
|
|
|
|
{
|
2018-04-21 06:20:23 +08:00
|
|
|
/*
|
|
|
|
* rodata is part of the kernel image and is normally
|
|
|
|
* readable on the filesystem or on the web. But, do not
|
|
|
|
* clone the areas past rodata, they might contain secrets.
|
|
|
|
*/
|
2018-04-07 04:55:18 +08:00
|
|
|
unsigned long start = PFN_ALIGN(_text);
|
2018-04-21 06:20:23 +08:00
|
|
|
unsigned long end = (unsigned long)__end_rodata_hpage_align;
|
2018-04-07 04:55:18 +08:00
|
|
|
|
|
|
|
if (!pti_kernel_image_global_ok())
|
|
|
|
return;
|
|
|
|
|
2018-04-21 06:20:23 +08:00
|
|
|
pr_debug("mapping partial kernel image into user address space\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note that this will undo _some_ of the work that
|
|
|
|
* pti_set_kernel_image_nonglobal() did to clear the
|
|
|
|
* global bit.
|
|
|
|
*/
|
2018-04-07 04:55:18 +08:00
|
|
|
pti_clone_pmds(start, end, _PAGE_RW);
|
|
|
|
}
|
|
|
|
|
x86/pti: Never implicitly clear _PAGE_GLOBAL for kernel image
Summary:
In current kernels, with PTI enabled, no pages are marked Global. This
potentially increases TLB misses. But, the mechanism by which the Global
bit is set and cleared is rather haphazard. This patch makes the process
more explicit. In the end, it leaves us with Global entries in the page
tables for the areas truly shared by userspace and kernel and increases
TLB hit rates.
The place this patch really shines in on systems without PCIDs. In this
case, we are using an lseek microbenchmark[1] to see how a reasonably
non-trivial syscall behaves. Higher is better:
No Global pages (baseline): 6077741 lseeks/sec
88 Global Pages (this set): 7528609 lseeks/sec (+23.9%)
On a modern Skylake desktop with PCIDs, the benefits are tangible, but not
huge for a kernel compile (lower is better):
No Global pages (baseline): 186.951 seconds time elapsed ( +- 0.35% )
28 Global pages (this set): 185.756 seconds time elapsed ( +- 0.09% )
-1.195 seconds (-0.64%)
I also re-checked everything using the lseek1 test[1]:
No Global pages (baseline): 15783951 lseeks/sec
28 Global pages (this set): 16054688 lseeks/sec
+270737 lseeks/sec (+1.71%)
The effect is more visible, but still modest.
Details:
The kernel page tables are inherited from head_64.S which rudely marks
them as _PAGE_GLOBAL. For PTI, we have been relying on the grace of
$DEITY and some insane behavior in pageattr.c to clear _PAGE_GLOBAL.
This patch tries to do better.
First, stop filtering out "unsupported" bits from being cleared in the
pageattr code. It's fine to filter out *setting* these bits but it
is insane to keep us from clearing them.
Then, *explicitly* go clear _PAGE_GLOBAL from the kernel identity map.
Do not rely on pageattr to do it magically.
After this patch, we can see that "GLB" shows up in each copy of the
page tables, that we have the same number of global entries in each
and that they are the *same* entries.
/sys/kernel/debug/page_tables/current_kernel:11
/sys/kernel/debug/page_tables/current_user:11
/sys/kernel/debug/page_tables/kernel:11
9caae8ad6a1fb53aca2407ec037f612d current_kernel.GLB
9caae8ad6a1fb53aca2407ec037f612d current_user.GLB
9caae8ad6a1fb53aca2407ec037f612d kernel.GLB
A quick visual audit also shows that all the entries make sense.
0xfffffe0000000000 is the cpu_entry_area and 0xffffffff81c00000
is the entry/exit text:
0xfffffe0000000000-0xfffffe0000002000 8K ro GLB NX pte
0xfffffe0000002000-0xfffffe0000003000 4K RW GLB NX pte
0xfffffe0000003000-0xfffffe0000006000 12K ro GLB NX pte
0xfffffe0000006000-0xfffffe0000007000 4K ro GLB x pte
0xfffffe0000007000-0xfffffe000000d000 24K RW GLB NX pte
0xfffffe000002d000-0xfffffe000002e000 4K ro GLB NX pte
0xfffffe000002e000-0xfffffe000002f000 4K RW GLB NX pte
0xfffffe000002f000-0xfffffe0000032000 12K ro GLB NX pte
0xfffffe0000032000-0xfffffe0000033000 4K ro GLB x pte
0xfffffe0000033000-0xfffffe0000039000 24K RW GLB NX pte
0xffffffff81c00000-0xffffffff81e00000 2M ro PSE GLB x pmd
[1.] https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hugh Dickins <hughd@google.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Kees Cook <keescook@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Nadav Amit <namit@vmware.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mm@kvack.org
Link: http://lkml.kernel.org/r/20180406205517.C80FBE05@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-04-07 04:55:17 +08:00
|
|
|
/*
|
|
|
|
* This is the only user for it and it is not arch-generic like
|
|
|
|
* the other set_memory.h functions. Just extern it.
|
|
|
|
*/
|
|
|
|
extern int set_memory_nonglobal(unsigned long addr, int numpages);
|
2018-07-16 12:03:38 +08:00
|
|
|
static void pti_set_kernel_image_nonglobal(void)
|
x86/pti: Never implicitly clear _PAGE_GLOBAL for kernel image
Summary:
In current kernels, with PTI enabled, no pages are marked Global. This
potentially increases TLB misses. But, the mechanism by which the Global
bit is set and cleared is rather haphazard. This patch makes the process
more explicit. In the end, it leaves us with Global entries in the page
tables for the areas truly shared by userspace and kernel and increases
TLB hit rates.
The place this patch really shines in on systems without PCIDs. In this
case, we are using an lseek microbenchmark[1] to see how a reasonably
non-trivial syscall behaves. Higher is better:
No Global pages (baseline): 6077741 lseeks/sec
88 Global Pages (this set): 7528609 lseeks/sec (+23.9%)
On a modern Skylake desktop with PCIDs, the benefits are tangible, but not
huge for a kernel compile (lower is better):
No Global pages (baseline): 186.951 seconds time elapsed ( +- 0.35% )
28 Global pages (this set): 185.756 seconds time elapsed ( +- 0.09% )
-1.195 seconds (-0.64%)
I also re-checked everything using the lseek1 test[1]:
No Global pages (baseline): 15783951 lseeks/sec
28 Global pages (this set): 16054688 lseeks/sec
+270737 lseeks/sec (+1.71%)
The effect is more visible, but still modest.
Details:
The kernel page tables are inherited from head_64.S which rudely marks
them as _PAGE_GLOBAL. For PTI, we have been relying on the grace of
$DEITY and some insane behavior in pageattr.c to clear _PAGE_GLOBAL.
This patch tries to do better.
First, stop filtering out "unsupported" bits from being cleared in the
pageattr code. It's fine to filter out *setting* these bits but it
is insane to keep us from clearing them.
Then, *explicitly* go clear _PAGE_GLOBAL from the kernel identity map.
Do not rely on pageattr to do it magically.
After this patch, we can see that "GLB" shows up in each copy of the
page tables, that we have the same number of global entries in each
and that they are the *same* entries.
/sys/kernel/debug/page_tables/current_kernel:11
/sys/kernel/debug/page_tables/current_user:11
/sys/kernel/debug/page_tables/kernel:11
9caae8ad6a1fb53aca2407ec037f612d current_kernel.GLB
9caae8ad6a1fb53aca2407ec037f612d current_user.GLB
9caae8ad6a1fb53aca2407ec037f612d kernel.GLB
A quick visual audit also shows that all the entries make sense.
0xfffffe0000000000 is the cpu_entry_area and 0xffffffff81c00000
is the entry/exit text:
0xfffffe0000000000-0xfffffe0000002000 8K ro GLB NX pte
0xfffffe0000002000-0xfffffe0000003000 4K RW GLB NX pte
0xfffffe0000003000-0xfffffe0000006000 12K ro GLB NX pte
0xfffffe0000006000-0xfffffe0000007000 4K ro GLB x pte
0xfffffe0000007000-0xfffffe000000d000 24K RW GLB NX pte
0xfffffe000002d000-0xfffffe000002e000 4K ro GLB NX pte
0xfffffe000002e000-0xfffffe000002f000 4K RW GLB NX pte
0xfffffe000002f000-0xfffffe0000032000 12K ro GLB NX pte
0xfffffe0000032000-0xfffffe0000033000 4K ro GLB x pte
0xfffffe0000033000-0xfffffe0000039000 24K RW GLB NX pte
0xffffffff81c00000-0xffffffff81e00000 2M ro PSE GLB x pmd
[1.] https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hugh Dickins <hughd@google.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Kees Cook <keescook@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Nadav Amit <namit@vmware.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mm@kvack.org
Link: http://lkml.kernel.org/r/20180406205517.C80FBE05@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-04-07 04:55:17 +08:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* The identity map is created with PMDs, regardless of the
|
|
|
|
* actual length of the kernel. We need to clear
|
|
|
|
* _PAGE_GLOBAL up to a PMD boundary, not just to the end
|
|
|
|
* of the image.
|
|
|
|
*/
|
|
|
|
unsigned long start = PFN_ALIGN(_text);
|
|
|
|
unsigned long end = ALIGN((unsigned long)_end, PMD_PAGE_SIZE);
|
|
|
|
|
2018-04-07 04:55:18 +08:00
|
|
|
if (pti_kernel_image_global_ok())
|
|
|
|
return;
|
|
|
|
|
x86/pti: Never implicitly clear _PAGE_GLOBAL for kernel image
Summary:
In current kernels, with PTI enabled, no pages are marked Global. This
potentially increases TLB misses. But, the mechanism by which the Global
bit is set and cleared is rather haphazard. This patch makes the process
more explicit. In the end, it leaves us with Global entries in the page
tables for the areas truly shared by userspace and kernel and increases
TLB hit rates.
The place this patch really shines in on systems without PCIDs. In this
case, we are using an lseek microbenchmark[1] to see how a reasonably
non-trivial syscall behaves. Higher is better:
No Global pages (baseline): 6077741 lseeks/sec
88 Global Pages (this set): 7528609 lseeks/sec (+23.9%)
On a modern Skylake desktop with PCIDs, the benefits are tangible, but not
huge for a kernel compile (lower is better):
No Global pages (baseline): 186.951 seconds time elapsed ( +- 0.35% )
28 Global pages (this set): 185.756 seconds time elapsed ( +- 0.09% )
-1.195 seconds (-0.64%)
I also re-checked everything using the lseek1 test[1]:
No Global pages (baseline): 15783951 lseeks/sec
28 Global pages (this set): 16054688 lseeks/sec
+270737 lseeks/sec (+1.71%)
The effect is more visible, but still modest.
Details:
The kernel page tables are inherited from head_64.S which rudely marks
them as _PAGE_GLOBAL. For PTI, we have been relying on the grace of
$DEITY and some insane behavior in pageattr.c to clear _PAGE_GLOBAL.
This patch tries to do better.
First, stop filtering out "unsupported" bits from being cleared in the
pageattr code. It's fine to filter out *setting* these bits but it
is insane to keep us from clearing them.
Then, *explicitly* go clear _PAGE_GLOBAL from the kernel identity map.
Do not rely on pageattr to do it magically.
After this patch, we can see that "GLB" shows up in each copy of the
page tables, that we have the same number of global entries in each
and that they are the *same* entries.
/sys/kernel/debug/page_tables/current_kernel:11
/sys/kernel/debug/page_tables/current_user:11
/sys/kernel/debug/page_tables/kernel:11
9caae8ad6a1fb53aca2407ec037f612d current_kernel.GLB
9caae8ad6a1fb53aca2407ec037f612d current_user.GLB
9caae8ad6a1fb53aca2407ec037f612d kernel.GLB
A quick visual audit also shows that all the entries make sense.
0xfffffe0000000000 is the cpu_entry_area and 0xffffffff81c00000
is the entry/exit text:
0xfffffe0000000000-0xfffffe0000002000 8K ro GLB NX pte
0xfffffe0000002000-0xfffffe0000003000 4K RW GLB NX pte
0xfffffe0000003000-0xfffffe0000006000 12K ro GLB NX pte
0xfffffe0000006000-0xfffffe0000007000 4K ro GLB x pte
0xfffffe0000007000-0xfffffe000000d000 24K RW GLB NX pte
0xfffffe000002d000-0xfffffe000002e000 4K ro GLB NX pte
0xfffffe000002e000-0xfffffe000002f000 4K RW GLB NX pte
0xfffffe000002f000-0xfffffe0000032000 12K ro GLB NX pte
0xfffffe0000032000-0xfffffe0000033000 4K ro GLB x pte
0xfffffe0000033000-0xfffffe0000039000 24K RW GLB NX pte
0xffffffff81c00000-0xffffffff81e00000 2M ro PSE GLB x pmd
[1.] https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hugh Dickins <hughd@google.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Kees Cook <keescook@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Nadav Amit <namit@vmware.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mm@kvack.org
Link: http://lkml.kernel.org/r/20180406205517.C80FBE05@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-04-07 04:55:17 +08:00
|
|
|
set_memory_nonglobal(start, (end - start) >> PAGE_SHIFT);
|
|
|
|
}
|
|
|
|
|
2017-12-04 22:07:36 +08:00
|
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/*
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* Initialize kernel page table isolation
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*/
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void __init pti_init(void)
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{
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if (!static_cpu_has(X86_FEATURE_PTI))
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return;
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pr_info("enabled\n");
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2017-12-04 22:07:45 +08:00
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pti_clone_user_shared();
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x86/pti: Never implicitly clear _PAGE_GLOBAL for kernel image
Summary:
In current kernels, with PTI enabled, no pages are marked Global. This
potentially increases TLB misses. But, the mechanism by which the Global
bit is set and cleared is rather haphazard. This patch makes the process
more explicit. In the end, it leaves us with Global entries in the page
tables for the areas truly shared by userspace and kernel and increases
TLB hit rates.
The place this patch really shines in on systems without PCIDs. In this
case, we are using an lseek microbenchmark[1] to see how a reasonably
non-trivial syscall behaves. Higher is better:
No Global pages (baseline): 6077741 lseeks/sec
88 Global Pages (this set): 7528609 lseeks/sec (+23.9%)
On a modern Skylake desktop with PCIDs, the benefits are tangible, but not
huge for a kernel compile (lower is better):
No Global pages (baseline): 186.951 seconds time elapsed ( +- 0.35% )
28 Global pages (this set): 185.756 seconds time elapsed ( +- 0.09% )
-1.195 seconds (-0.64%)
I also re-checked everything using the lseek1 test[1]:
No Global pages (baseline): 15783951 lseeks/sec
28 Global pages (this set): 16054688 lseeks/sec
+270737 lseeks/sec (+1.71%)
The effect is more visible, but still modest.
Details:
The kernel page tables are inherited from head_64.S which rudely marks
them as _PAGE_GLOBAL. For PTI, we have been relying on the grace of
$DEITY and some insane behavior in pageattr.c to clear _PAGE_GLOBAL.
This patch tries to do better.
First, stop filtering out "unsupported" bits from being cleared in the
pageattr code. It's fine to filter out *setting* these bits but it
is insane to keep us from clearing them.
Then, *explicitly* go clear _PAGE_GLOBAL from the kernel identity map.
Do not rely on pageattr to do it magically.
After this patch, we can see that "GLB" shows up in each copy of the
page tables, that we have the same number of global entries in each
and that they are the *same* entries.
/sys/kernel/debug/page_tables/current_kernel:11
/sys/kernel/debug/page_tables/current_user:11
/sys/kernel/debug/page_tables/kernel:11
9caae8ad6a1fb53aca2407ec037f612d current_kernel.GLB
9caae8ad6a1fb53aca2407ec037f612d current_user.GLB
9caae8ad6a1fb53aca2407ec037f612d kernel.GLB
A quick visual audit also shows that all the entries make sense.
0xfffffe0000000000 is the cpu_entry_area and 0xffffffff81c00000
is the entry/exit text:
0xfffffe0000000000-0xfffffe0000002000 8K ro GLB NX pte
0xfffffe0000002000-0xfffffe0000003000 4K RW GLB NX pte
0xfffffe0000003000-0xfffffe0000006000 12K ro GLB NX pte
0xfffffe0000006000-0xfffffe0000007000 4K ro GLB x pte
0xfffffe0000007000-0xfffffe000000d000 24K RW GLB NX pte
0xfffffe000002d000-0xfffffe000002e000 4K ro GLB NX pte
0xfffffe000002e000-0xfffffe000002f000 4K RW GLB NX pte
0xfffffe000002f000-0xfffffe0000032000 12K ro GLB NX pte
0xfffffe0000032000-0xfffffe0000033000 4K ro GLB x pte
0xfffffe0000033000-0xfffffe0000039000 24K RW GLB NX pte
0xffffffff81c00000-0xffffffff81e00000 2M ro PSE GLB x pmd
[1.] https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hugh Dickins <hughd@google.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Kees Cook <keescook@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Nadav Amit <namit@vmware.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mm@kvack.org
Link: http://lkml.kernel.org/r/20180406205517.C80FBE05@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-04-07 04:55:17 +08:00
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/* Undo all global bits from the init pagetables in head_64.S: */
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pti_set_kernel_image_nonglobal();
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/* Replace some of the global bits just for shared entry text: */
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2017-12-04 22:07:47 +08:00
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pti_clone_entry_text();
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2017-12-16 05:08:18 +08:00
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pti_setup_espfix64();
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2017-12-12 23:56:42 +08:00
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pti_setup_vsyscall();
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2017-12-04 22:07:36 +08:00
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}
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