2014-11-04 02:07:35 +08:00
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#
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# Makefile for CoreSight drivers.
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#
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2016-04-06 01:53:49 +08:00
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obj-$(CONFIG_CORESIGHT) += coresight.o coresight-etm-perf.o
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2014-11-04 02:07:35 +08:00
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obj-$(CONFIG_OF) += of_coresight.o
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2016-05-04 01:33:50 +08:00
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obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o \
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coresight-tmc-etf.o \
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coresight-tmc-etr.o
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2014-11-04 02:07:37 +08:00
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obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o
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2014-11-04 02:07:38 +08:00
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obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o
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2014-11-04 02:07:40 +08:00
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obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \
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coresight-replicator.o
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2016-02-18 08:51:49 +08:00
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obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \
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2016-04-06 01:53:49 +08:00
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coresight-etm3x-sysfs.o
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2016-04-06 01:53:42 +08:00
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obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
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coresight-etm4x-sysfs.o
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2015-05-20 00:55:21 +08:00
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obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
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2016-05-04 01:33:40 +08:00
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obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
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coresight: add support for CPU debug module
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".
Chapter H7 "The Sample-based Profiling Extension" introduces several
sampling registers, e.g. we can check program counter value with
combined CPU exception level, secure state, etc. So this is helpful for
analysis CPU lockup scenarios, e.g. if one CPU has run into infinite
loop with IRQ disabled. In this case the CPU cannot switch context and
handle any interrupt (including IPIs), as the result it cannot handle
SMP call for stack dump.
This patch is to enable coresight debug module, so firstly this driver
is to bind apb clock for debug module and this is to ensure the debug
module can be accessed from program or external debugger. And the driver
uses sample-based registers for debug purpose, e.g. when system triggers
panic, the driver will dump program counter and combined context
registers (EDCIDSR, EDVIDSR); by parsing context registers so can
quickly get to know CPU secure state, exception level, etc.
Some of the debug module registers are located in CPU power domain, so
this requires the CPU power domain stays on when access related debug
registers, but the power management for CPU power domain is quite
dependent on SoC integration for power management. For the platforms
which with sane power controller implementations, this driver follows
the method to set EDPRCR to try to pull the CPU out of low power state
and then set 'no power down request' bit so the CPU has no chance to
lose power.
If the SoC has not followed up this design well for power management
controller, the user should use the command line parameter or sysfs
to constrain all or partial idle states to ensure the CPU power
domain is enabled and access coresight CPU debug component safely.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-06 04:15:16 +08:00
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obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
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