linux/arch/arm/include/debug/renesas-scif.S

/*
 * Renesas SCIF(A) debugging macro include header
 *
 * Based on r8a7790.S
 *
 * Copyright (C) 2012-2013 Renesas Electronics Corporation
 * Copyright (C) 1994-1999 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define SCIF_PHYS	CONFIG_DEBUG_UART_PHYS
#define SCIF_VIRT	((SCIF_PHYS & 0x00ffffff) | 0xfd000000)

#if CONFIG_DEBUG_UART_PHYS < 0xe6e00000
/* SCIFA */
#define FTDR		0x20
#define FSR		0x14
#else
/* SCIF */
#define FTDR		0x0c
#define FSR		0x10
#endif

#define TDFE	(1 << 5)
#define TEND	(1 << 6)

	.macro	addruart, rp, rv, tmp
	ldr	\rp, =SCIF_PHYS
	ldr	\rv, =SCIF_VIRT
	.endm

	.macro	waituart, rd, rx
1001:	ldrh	\rd, [\rx, #FSR]
	tst	\rd, #TDFE
	beq	1001b
	.endm

	.macro	senduart, rd, rx
	strb	\rd, [\rx, #FTDR]
	ldrh	\rd, [\rx, #FSR]
	bic	\rd, \rd, #TEND
	strh	\rd, [\rx, #FSR]
	.endm

	.macro	busyuart, rd, rx
1001:	ldrh	\rd, [\rx, #FSR]
	tst	\rd, #TEND
	beq	1001b
	.endm
ARM: shmobile: Add early debugging support using SCIF(A) Add serial port debug macros for the SCIF(A) serial ports. This includes all supported shmobile SoCs, except for EMEV2. The configuration logic (both Kconfig and #ifdef) is more complicated than one would expect, for several reasons: 1. Not all SoCs have the same serial devices, and they're not always at the same addresses. 2. There are two different types: SCIF and SCIFA. Fortunately they can easily be distinguished by physical address. 3. Not all boards use the same serial port for the console. The defaults correspond to the boards that are supported in mainline. If you want to use a different serial port, just change the value of CONFIG_DEBUG_UART_PHYS, and the rest will auto-adapt. 4. debug_ll_io_init() maps the SCIF(A) registers to a fixed virtual address. 0xfdxxxxxx was chosen, as it should lie below VMALLOC_END = 0xff000000, and must not conflict with the 2 MiB reserved region at PCI_IO_VIRT_BASE = 0xfee00000. - On SoCs not using the legacy machine_desc.map_io(), debug_ll_io_init() is called by the ARM core code. - On SoCs using the legacy machine_desc.map_io(), debug_ll_io_init() must be called explicitly. Calls are added for r8a7740, r8a7779, sh7372, and sh73a0. This was derived from the r8a7790 version by Laurent Pinchart. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> 2014-11-14 23:49:47 +08:00			`/*`
			`* Renesas SCIF(A) debugging macro include header`
			`*`
			`* Based on r8a7790.S`
			`*`
			`* Copyright (C) 2012-2013 Renesas Electronics Corporation`
			`* Copyright (C) 1994-1999 Russell King`
			`*`
			`* This program is free software; you can redistribute it and/or modify`
			`* it under the terms of the GNU General Public License version 2 as`
			`* published by the Free Software Foundation.`
			`*/`

			`#define SCIF_PHYS CONFIG_DEBUG_UART_PHYS`
			`#define SCIF_VIRT ((SCIF_PHYS & 0x00ffffff) \| 0xfd000000)`

			`#if CONFIG_DEBUG_UART_PHYS < 0xe6e00000`
			`/* SCIFA */`
			`#define FTDR 0x20`
			`#define FSR 0x14`
			`#else`
			`/* SCIF */`
			`#define FTDR 0x0c`
			`#define FSR 0x10`
			`#endif`

			`#define TDFE (1 << 5)`
			`#define TEND (1 << 6)`

			`.macro addruart, rp, rv, tmp`
			`ldr \rp, =SCIF_PHYS`
			`ldr \rv, =SCIF_VIRT`
			`.endm`

			`.macro waituart, rd, rx`
			`1001: ldrh \rd, [\rx, #FSR]`
			`tst \rd, #TDFE`
			`beq 1001b`
			`.endm`

			`.macro senduart, rd, rx`
			`strb \rd, [\rx, #FTDR]`
			`ldrh \rd, [\rx, #FSR]`
			`bic \rd, \rd, #TEND`
			`strh \rd, [\rx, #FSR]`
			`.endm`

			`.macro busyuart, rd, rx`
			`1001: ldrh \rd, [\rx, #FSR]`
			`tst \rd, #TEND`
			`beq 1001b`
			`.endm`