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linux/arch/powerpc/include/asm/reg_8xx.h

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Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
/*
[PATCH] powerpc: Merge cacheflush.h and cache.h The ppc32 and ppc64 versions of cacheflush.h were almost identical. The two versions of cache.h are fairly similar, except for a bunch of register definitions in the ppc32 version which probably belong better elsewhere. This patch, therefore, merges both headers. Notable points: - there are several functions in cacheflush.h which exist only on ppc32 or only on ppc64. These are handled by #ifdef for now, but these should probably be consolidated, along with the actual code behind them later. - Confusingly, both ppc32 and ppc64 have a flush_dcache_range(), but they're subtly different: it uses dcbf on ppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which uses dcbf. These too should be merged and consolidated later. - Also flush_dcache_range() was defined in cacheflush.h on ppc64, and in cache.h on ppc32. In the merged version it's in cacheflush.h - On ppc32 flush_icache_range() is a normal function from misc.S. On ppc64, it was wrapper, testing a feature bit before calling __flush_icache_range() which does the actual flush. This patch takes the ppc64 approach, which amounts to no change on ppc32, since CPU_FTR_COHERENT_ICACHE will never be set there, but does mean renaming flush_icache_range() to __flush_icache_range() in arch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S - The PReP register info from asm-ppc/cache.h has moved to arch/ppc/platforms/prep_setup.c - The 8xx register info from asm-ppc/cache.h has moved to a new asm-powerpc/reg_8xx.h, included from reg.h - flush_dcache_all() was defined on ppc32 (only), but was never called (although it was exported). Thus this patch removes it from cacheflush.h and from ARCH=powerpc (misc_32.S) entirely. It's left in ARCH=ppc for now, with the prototype moved to ppc_ksyms.c. Built for Walnut (ARCH=ppc), 32-bit multiplatform (pmac, CHRP and PReP ARCH=ppc, pmac and CHRP ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built for 32-bit powermac (ARCH=ppc and ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built and booted on G5 (ARCH=powerpc) Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-10 08:50:16 +08:00
* Contains register definitions common to PowerPC 8xx CPUs. Notice
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
*/
[PATCH] powerpc: Merge cacheflush.h and cache.h The ppc32 and ppc64 versions of cacheflush.h were almost identical. The two versions of cache.h are fairly similar, except for a bunch of register definitions in the ppc32 version which probably belong better elsewhere. This patch, therefore, merges both headers. Notable points: - there are several functions in cacheflush.h which exist only on ppc32 or only on ppc64. These are handled by #ifdef for now, but these should probably be consolidated, along with the actual code behind them later. - Confusingly, both ppc32 and ppc64 have a flush_dcache_range(), but they're subtly different: it uses dcbf on ppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which uses dcbf. These too should be merged and consolidated later. - Also flush_dcache_range() was defined in cacheflush.h on ppc64, and in cache.h on ppc32. In the merged version it's in cacheflush.h - On ppc32 flush_icache_range() is a normal function from misc.S. On ppc64, it was wrapper, testing a feature bit before calling __flush_icache_range() which does the actual flush. This patch takes the ppc64 approach, which amounts to no change on ppc32, since CPU_FTR_COHERENT_ICACHE will never be set there, but does mean renaming flush_icache_range() to __flush_icache_range() in arch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S - The PReP register info from asm-ppc/cache.h has moved to arch/ppc/platforms/prep_setup.c - The 8xx register info from asm-ppc/cache.h has moved to a new asm-powerpc/reg_8xx.h, included from reg.h - flush_dcache_all() was defined on ppc32 (only), but was never called (although it was exported). Thus this patch removes it from cacheflush.h and from ARCH=powerpc (misc_32.S) entirely. It's left in ARCH=ppc for now, with the prototype moved to ppc_ksyms.c. Built for Walnut (ARCH=ppc), 32-bit multiplatform (pmac, CHRP and PReP ARCH=ppc, pmac and CHRP ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built for 32-bit powermac (ARCH=ppc and ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built and booted on G5 (ARCH=powerpc) Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-10 08:50:16 +08:00
#ifndef _ASM_POWERPC_REG_8xx_H
#define _ASM_POWERPC_REG_8xx_H
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
powerpc/8xx: Implement support of hugepages 8xx uses a two level page table with two different linux page size support (4k and 16k). 8xx also support two different hugepage sizes 512k and 8M. In order to support them on linux we define two different page table layout. The size of pages is in the PGD entry, using PS field (bits 28-29): 00 : Small pages (4k or 16k) 01 : 512k pages 10 : reserved 11 : 8M pages For 512K hugepage size a pgd entry have the below format [<hugepte address >0101] . The hugepte table allocated will contain 8 entries pointing to 512K huge pte in 4k pages mode and 64 entries in 16k pages mode. For 8M in 16k mode, a pgd entry have the below format [<hugepte address >1101] . The hugepte table allocated will contain 8 entries pointing to 8M huge pte. For 8M in 4k mode, multiple pgd entries point to the same hugepte address and pgd entry will have the below format [<hugepte address>1101]. The hugepte table allocated will only have one entry. For the time being, we do not support CPU15 ERRATA when HUGETLB is selected Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> (v3, for the generic bits) Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-07 15:47:28 +08:00
#include <asm/mmu.h>
powerpc/8xx: Add missing SPRN defines into reg_8xx.h Add missing SPRN defines into reg_8xx.h Some of them are defined in mmu-8xx.h, so we include mmu-8xx.h in reg_8xx.h, for that we remove references to PAGE_SHIFT in mmu-8xx.h to have it self sufficient, as includers of reg_8xx.h don't all include asm/page.h Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:08:12 +08:00
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
/* Cache control on the MPC8xx is provided through some additional
* special purpose registers.
*/
#define SPRN_IC_CST 560 /* Instruction cache control/status */
#define SPRN_IC_ADR 561 /* Address needed for some commands */
#define SPRN_IC_DAT 562 /* Read-only data register */
#define SPRN_DC_CST 568 /* Data cache control/status */
#define SPRN_DC_ADR 569 /* Address needed for some commands */
#define SPRN_DC_DAT 570 /* Read-only data register */
powerpc/8xx: Add missing SPRN defines into reg_8xx.h Add missing SPRN defines into reg_8xx.h Some of them are defined in mmu-8xx.h, so we include mmu-8xx.h in reg_8xx.h, for that we remove references to PAGE_SHIFT in mmu-8xx.h to have it self sufficient, as includers of reg_8xx.h don't all include asm/page.h Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:08:12 +08:00
/* Misc Debug */
#define SPRN_DPDR 630
#define SPRN_MI_CAM 816
#define SPRN_MI_RAM0 817
#define SPRN_MI_RAM1 818
#define SPRN_MD_CAM 824
#define SPRN_MD_RAM0 825
#define SPRN_MD_RAM1 826
powerpc/8xx: use SPRN_EIE and SPRN_EID to enable/disable interrupts The 8xx has two special registers called EID (External Interrupt Disable) and EIE (External Interrupt Enable) for clearing/setting EE in MSR. It avoids the three instructions set mfmsr/ori/mtmsr or mfmsr/rlwinm/mtmsr and it avoids using a general register. We just have to write something in the special register to change MSR EE bit. So we write r0 into the register, regardless of r0 value. Writing to one of those two special registers also set the MSR RI bit, but this bit is only unset during beginning of exception prolog and end of exception epilog. When executing C-functions MSR RI is always set. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
2016-08-23 21:58:56 +08:00
/* Special MSR manipulation registers */
#define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */
#define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
powerpc/8xx: Implement hw_breakpoint This patch implements HW breakpoint on the 8xx. The 8xx has capability to manage HW breakpoints, which is slightly different than BOOK3S: 1/ The breakpoint match doesn't trigger a DSI exception but a dedicated data breakpoint exception. 2/ The breakpoint happens after the instruction has completed, no need to single step or emulate the instruction, 3/ Matched address is not set in DAR but in BAR, 4/ DABR register doesn't exist, instead we have registers LCTRL1, LCTRL2 and CMPx registers, 5/ The match on one comparator is not on a double word but on a single word. The patch does: 1/ Prepare the dedicated registers in call to __set_dabr(). In order to emulate the double word handling of BOOK3S, comparator E is set to DABR address value and comparator F to address + 4. Then breakpoint 1 is set to match comparator E or F, 2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx, 3/ Implement the exception. In that exception, the matched address is taken from SPRN_BAR and manage as if it was from SPRN_DAR. 4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That tlbie triggers the breakpoint exception when performed on the breakpoint address. For this reason, the routine returns if the match is from one of those two tlbie. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 16:52:15 +08:00
/* Debug registers */
#define SPRN_CMPE 152
#define SPRN_CMPF 153
#define SPRN_LCTRL1 156
#define SPRN_LCTRL2 157
#define SPRN_BAR 159
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
/* Commands. Only the first few are available to the instruction cache.
*/
#define IDC_ENABLE 0x02000000 /* Cache enable */
#define IDC_DISABLE 0x04000000 /* Cache disable */
#define IDC_LDLCK 0x06000000 /* Load and lock */
#define IDC_UNLINE 0x08000000 /* Unlock line */
#define IDC_UNALL 0x0a000000 /* Unlock all */
#define IDC_INVALL 0x0c000000 /* Invalidate all */
#define DC_FLINE 0x0e000000 /* Flush data cache line */
#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
#define DC_SLES 0x05000000 /* Set little endian swap mode */
#define DC_CLES 0x07000000 /* Clear little endian swap mode */
/* Status.
*/
#define IDC_ENABLED 0x80000000 /* Cache is enabled */
#define IDC_CERR1 0x00200000 /* Cache error 1 */
#define IDC_CERR2 0x00100000 /* Cache error 2 */
#define IDC_CERR3 0x00080000 /* Cache error 3 */
#define DC_DFWT 0x40000000 /* Data cache is forced write through */
#define DC_LES 0x20000000 /* Caches are little endian mode */
powerpc/8xx: Handle CPU6 ERRATA directly in mtspr() macro MPC8xx has an ERRATA on the use of mtspr() for some registers This patch includes the ERRATA handling directly into mtspr() macro so that mtspr() users don't need to bother about that errata Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:08:14 +08:00
#ifdef CONFIG_8xx_CPU6
#define do_mtspr_cpu6(rn, rn_addr, v) \
do { \
powerpc/8xx: Fix do_mtspr_cpu6() build on older compilers GCC < 4.9 is unable to build this, saying: arch/powerpc/mm/8xx_mmu.c:139:2: error: memory input 1 is not directly addressable Change the one-element array into a simple variable to avoid this. Fixes: 1458dd951f7c ("powerpc/8xx: Handle CPU6 ERRATA directly in mtspr() macro") Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Cc: Scott Wood <oss@buserror.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-15 21:07:49 +08:00
int _reg_cpu6 = rn_addr, _tmp_cpu6; \
powerpc/8xx: Handle CPU6 ERRATA directly in mtspr() macro MPC8xx has an ERRATA on the use of mtspr() for some registers This patch includes the ERRATA handling directly into mtspr() macro so that mtspr() users don't need to bother about that errata Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:08:14 +08:00
asm volatile("stw %0, %1;" \
"lwz %0, %1;" \
"mtspr " __stringify(rn) ",%2" : \
: "r" (_reg_cpu6), "m"(_tmp_cpu6), \
"r" ((unsigned long)(v)) \
: "memory"); \
} while (0)
#define do_mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
: "r" ((unsigned long)(v)) \
: "memory")
#define mtspr(rn, v) \
do { \
if (rn == SPRN_IMMR) \
do_mtspr_cpu6(rn, 0x3d30, v); \
else if (rn == SPRN_IC_CST) \
do_mtspr_cpu6(rn, 0x2110, v); \
else if (rn == SPRN_IC_ADR) \
do_mtspr_cpu6(rn, 0x2310, v); \
else if (rn == SPRN_IC_DAT) \
do_mtspr_cpu6(rn, 0x2510, v); \
else if (rn == SPRN_DC_CST) \
do_mtspr_cpu6(rn, 0x3110, v); \
else if (rn == SPRN_DC_ADR) \
do_mtspr_cpu6(rn, 0x3310, v); \
else if (rn == SPRN_DC_DAT) \
do_mtspr_cpu6(rn, 0x3510, v); \
else if (rn == SPRN_MI_CTR) \
do_mtspr_cpu6(rn, 0x2180, v); \
else if (rn == SPRN_MI_AP) \
do_mtspr_cpu6(rn, 0x2580, v); \
else if (rn == SPRN_MI_EPN) \
do_mtspr_cpu6(rn, 0x2780, v); \
else if (rn == SPRN_MI_TWC) \
do_mtspr_cpu6(rn, 0x2b80, v); \
else if (rn == SPRN_MI_RPN) \
do_mtspr_cpu6(rn, 0x2d80, v); \
else if (rn == SPRN_MI_CAM) \
do_mtspr_cpu6(rn, 0x2190, v); \
else if (rn == SPRN_MI_RAM0) \
do_mtspr_cpu6(rn, 0x2390, v); \
else if (rn == SPRN_MI_RAM1) \
do_mtspr_cpu6(rn, 0x2590, v); \
else if (rn == SPRN_MD_CTR) \
do_mtspr_cpu6(rn, 0x3180, v); \
else if (rn == SPRN_M_CASID) \
do_mtspr_cpu6(rn, 0x3380, v); \
else if (rn == SPRN_MD_AP) \
do_mtspr_cpu6(rn, 0x3580, v); \
else if (rn == SPRN_MD_EPN) \
do_mtspr_cpu6(rn, 0x3780, v); \
else if (rn == SPRN_M_TWB) \
do_mtspr_cpu6(rn, 0x3980, v); \
else if (rn == SPRN_MD_TWC) \
do_mtspr_cpu6(rn, 0x3b80, v); \
else if (rn == SPRN_MD_RPN) \
do_mtspr_cpu6(rn, 0x3d80, v); \
else if (rn == SPRN_M_TW) \
do_mtspr_cpu6(rn, 0x3f80, v); \
else if (rn == SPRN_MD_CAM) \
do_mtspr_cpu6(rn, 0x3190, v); \
else if (rn == SPRN_MD_RAM0) \
do_mtspr_cpu6(rn, 0x3390, v); \
else if (rn == SPRN_MD_RAM1) \
do_mtspr_cpu6(rn, 0x3590, v); \
else if (rn == SPRN_DEC) \
do_mtspr_cpu6(rn, 0x2c00, v); \
else if (rn == SPRN_TBWL) \
do_mtspr_cpu6(rn, 0x3880, v); \
else if (rn == SPRN_TBWU) \
do_mtspr_cpu6(rn, 0x3a80, v); \
else if (rn == SPRN_DPDR) \
do_mtspr_cpu6(rn, 0x2d30, v); \
else \
do_mtspr(rn, v); \
} while (0)
#endif
[PATCH] powerpc: Merge cacheflush.h and cache.h The ppc32 and ppc64 versions of cacheflush.h were almost identical. The two versions of cache.h are fairly similar, except for a bunch of register definitions in the ppc32 version which probably belong better elsewhere. This patch, therefore, merges both headers. Notable points: - there are several functions in cacheflush.h which exist only on ppc32 or only on ppc64. These are handled by #ifdef for now, but these should probably be consolidated, along with the actual code behind them later. - Confusingly, both ppc32 and ppc64 have a flush_dcache_range(), but they're subtly different: it uses dcbf on ppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which uses dcbf. These too should be merged and consolidated later. - Also flush_dcache_range() was defined in cacheflush.h on ppc64, and in cache.h on ppc32. In the merged version it's in cacheflush.h - On ppc32 flush_icache_range() is a normal function from misc.S. On ppc64, it was wrapper, testing a feature bit before calling __flush_icache_range() which does the actual flush. This patch takes the ppc64 approach, which amounts to no change on ppc32, since CPU_FTR_COHERENT_ICACHE will never be set there, but does mean renaming flush_icache_range() to __flush_icache_range() in arch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S - The PReP register info from asm-ppc/cache.h has moved to arch/ppc/platforms/prep_setup.c - The 8xx register info from asm-ppc/cache.h has moved to a new asm-powerpc/reg_8xx.h, included from reg.h - flush_dcache_all() was defined on ppc32 (only), but was never called (although it was exported). Thus this patch removes it from cacheflush.h and from ARCH=powerpc (misc_32.S) entirely. It's left in ARCH=ppc for now, with the prototype moved to ppc_ksyms.c. Built for Walnut (ARCH=ppc), 32-bit multiplatform (pmac, CHRP and PReP ARCH=ppc, pmac and CHRP ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built for 32-bit powermac (ARCH=ppc and ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built and booted on G5 (ARCH=powerpc) Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-10 08:50:16 +08:00
#endif /* _ASM_POWERPC_REG_8xx_H */