mirror of https://gitee.com/openkylin/linux.git
367 lines
10 KiB
C
367 lines
10 KiB
C
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/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#include "qed_hw.h"
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#include "qed_int.h"
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#include "qed_reg_addr.h"
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#include "qed_sriov.h"
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#include "qed_vf.h"
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bool qed_iov_is_valid_vfid(struct qed_hwfn *p_hwfn,
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int rel_vf_id, bool b_enabled_only)
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{
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if (!p_hwfn->pf_iov_info) {
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DP_NOTICE(p_hwfn->cdev, "No iov info\n");
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return false;
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}
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if ((rel_vf_id >= p_hwfn->cdev->p_iov_info->total_vfs) ||
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(rel_vf_id < 0))
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return false;
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if ((!p_hwfn->pf_iov_info->vfs_array[rel_vf_id].b_init) &&
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b_enabled_only)
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return false;
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return true;
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}
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static int qed_iov_pci_cfg_info(struct qed_dev *cdev)
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{
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struct qed_hw_sriov_info *iov = cdev->p_iov_info;
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int pos = iov->pos;
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DP_VERBOSE(cdev, QED_MSG_IOV, "sriov ext pos %d\n", pos);
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pci_read_config_word(cdev->pdev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
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pci_read_config_word(cdev->pdev,
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pos + PCI_SRIOV_TOTAL_VF, &iov->total_vfs);
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pci_read_config_word(cdev->pdev,
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pos + PCI_SRIOV_INITIAL_VF, &iov->initial_vfs);
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pci_read_config_word(cdev->pdev, pos + PCI_SRIOV_NUM_VF, &iov->num_vfs);
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if (iov->num_vfs) {
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DP_VERBOSE(cdev,
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QED_MSG_IOV,
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"Number of VFs are already set to non-zero value. Ignoring PCI configuration value\n");
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iov->num_vfs = 0;
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}
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pci_read_config_word(cdev->pdev,
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pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
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pci_read_config_word(cdev->pdev,
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pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
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pci_read_config_word(cdev->pdev,
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pos + PCI_SRIOV_VF_DID, &iov->vf_device_id);
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pci_read_config_dword(cdev->pdev,
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pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
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pci_read_config_dword(cdev->pdev, pos + PCI_SRIOV_CAP, &iov->cap);
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pci_read_config_byte(cdev->pdev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
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DP_VERBOSE(cdev,
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QED_MSG_IOV,
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"IOV info: nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n",
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iov->nres,
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iov->cap,
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iov->ctrl,
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iov->total_vfs,
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iov->initial_vfs,
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iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz);
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/* Some sanity checks */
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if (iov->num_vfs > NUM_OF_VFS(cdev) ||
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iov->total_vfs > NUM_OF_VFS(cdev)) {
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/* This can happen only due to a bug. In this case we set
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* num_vfs to zero to avoid memory corruption in the code that
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* assumes max number of vfs
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*/
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DP_NOTICE(cdev,
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"IOV: Unexpected number of vfs set: %d setting num_vf to zero\n",
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iov->num_vfs);
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iov->num_vfs = 0;
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iov->total_vfs = 0;
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}
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return 0;
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}
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static void qed_iov_clear_vf_igu_blocks(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt)
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{
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struct qed_igu_block *p_sb;
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u16 sb_id;
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u32 val;
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if (!p_hwfn->hw_info.p_igu_info) {
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DP_ERR(p_hwfn,
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"qed_iov_clear_vf_igu_blocks IGU Info not initialized\n");
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return;
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}
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for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
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sb_id++) {
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p_sb = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
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if ((p_sb->status & QED_IGU_STATUS_FREE) &&
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!(p_sb->status & QED_IGU_STATUS_PF)) {
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val = qed_rd(p_hwfn, p_ptt,
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IGU_REG_MAPPING_MEMORY + sb_id * 4);
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SET_FIELD(val, IGU_MAPPING_LINE_VALID, 0);
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qed_wr(p_hwfn, p_ptt,
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IGU_REG_MAPPING_MEMORY + 4 * sb_id, val);
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}
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}
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}
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static void qed_iov_setup_vfdb(struct qed_hwfn *p_hwfn)
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{
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struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
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struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
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struct qed_bulletin_content *p_bulletin_virt;
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dma_addr_t req_p, rply_p, bulletin_p;
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union pfvf_tlvs *p_reply_virt_addr;
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union vfpf_tlvs *p_req_virt_addr;
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u8 idx = 0;
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memset(p_iov_info->vfs_array, 0, sizeof(p_iov_info->vfs_array));
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p_req_virt_addr = p_iov_info->mbx_msg_virt_addr;
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req_p = p_iov_info->mbx_msg_phys_addr;
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p_reply_virt_addr = p_iov_info->mbx_reply_virt_addr;
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rply_p = p_iov_info->mbx_reply_phys_addr;
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p_bulletin_virt = p_iov_info->p_bulletins;
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bulletin_p = p_iov_info->bulletins_phys;
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if (!p_req_virt_addr || !p_reply_virt_addr || !p_bulletin_virt) {
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DP_ERR(p_hwfn,
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"qed_iov_setup_vfdb called without allocating mem first\n");
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return;
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}
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for (idx = 0; idx < p_iov->total_vfs; idx++) {
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struct qed_vf_info *vf = &p_iov_info->vfs_array[idx];
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u32 concrete;
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vf->vf_mbx.req_virt = p_req_virt_addr + idx;
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vf->vf_mbx.req_phys = req_p + idx * sizeof(union vfpf_tlvs);
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vf->vf_mbx.reply_virt = p_reply_virt_addr + idx;
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vf->vf_mbx.reply_phys = rply_p + idx * sizeof(union pfvf_tlvs);
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vf->state = VF_STOPPED;
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vf->b_init = false;
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vf->bulletin.phys = idx *
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sizeof(struct qed_bulletin_content) +
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bulletin_p;
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vf->bulletin.p_virt = p_bulletin_virt + idx;
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vf->bulletin.size = sizeof(struct qed_bulletin_content);
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vf->relative_vf_id = idx;
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vf->abs_vf_id = idx + p_iov->first_vf_in_pf;
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concrete = qed_vfid_to_concrete(p_hwfn, vf->abs_vf_id);
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vf->concrete_fid = concrete;
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vf->opaque_fid = (p_hwfn->hw_info.opaque_fid & 0xff) |
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(vf->abs_vf_id << 8);
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vf->vport_id = idx + 1;
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}
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}
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static int qed_iov_allocate_vfdb(struct qed_hwfn *p_hwfn)
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{
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struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
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void **p_v_addr;
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u16 num_vfs = 0;
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num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
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DP_VERBOSE(p_hwfn, QED_MSG_IOV,
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"qed_iov_allocate_vfdb for %d VFs\n", num_vfs);
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/* Allocate PF Mailbox buffer (per-VF) */
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p_iov_info->mbx_msg_size = sizeof(union vfpf_tlvs) * num_vfs;
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p_v_addr = &p_iov_info->mbx_msg_virt_addr;
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*p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
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p_iov_info->mbx_msg_size,
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&p_iov_info->mbx_msg_phys_addr,
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GFP_KERNEL);
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if (!*p_v_addr)
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return -ENOMEM;
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/* Allocate PF Mailbox Reply buffer (per-VF) */
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p_iov_info->mbx_reply_size = sizeof(union pfvf_tlvs) * num_vfs;
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p_v_addr = &p_iov_info->mbx_reply_virt_addr;
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*p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
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p_iov_info->mbx_reply_size,
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&p_iov_info->mbx_reply_phys_addr,
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GFP_KERNEL);
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if (!*p_v_addr)
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return -ENOMEM;
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p_iov_info->bulletins_size = sizeof(struct qed_bulletin_content) *
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num_vfs;
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p_v_addr = &p_iov_info->p_bulletins;
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*p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
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p_iov_info->bulletins_size,
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&p_iov_info->bulletins_phys,
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GFP_KERNEL);
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if (!*p_v_addr)
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return -ENOMEM;
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DP_VERBOSE(p_hwfn,
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QED_MSG_IOV,
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"PF's Requests mailbox [%p virt 0x%llx phys], Response mailbox [%p virt 0x%llx phys] Bulletins [%p virt 0x%llx phys]\n",
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p_iov_info->mbx_msg_virt_addr,
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(u64) p_iov_info->mbx_msg_phys_addr,
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p_iov_info->mbx_reply_virt_addr,
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(u64) p_iov_info->mbx_reply_phys_addr,
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p_iov_info->p_bulletins, (u64) p_iov_info->bulletins_phys);
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return 0;
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}
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static void qed_iov_free_vfdb(struct qed_hwfn *p_hwfn)
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{
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struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
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if (p_hwfn->pf_iov_info->mbx_msg_virt_addr)
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dma_free_coherent(&p_hwfn->cdev->pdev->dev,
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p_iov_info->mbx_msg_size,
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p_iov_info->mbx_msg_virt_addr,
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p_iov_info->mbx_msg_phys_addr);
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if (p_hwfn->pf_iov_info->mbx_reply_virt_addr)
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dma_free_coherent(&p_hwfn->cdev->pdev->dev,
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p_iov_info->mbx_reply_size,
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p_iov_info->mbx_reply_virt_addr,
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p_iov_info->mbx_reply_phys_addr);
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if (p_iov_info->p_bulletins)
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dma_free_coherent(&p_hwfn->cdev->pdev->dev,
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p_iov_info->bulletins_size,
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p_iov_info->p_bulletins,
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p_iov_info->bulletins_phys);
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}
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int qed_iov_alloc(struct qed_hwfn *p_hwfn)
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{
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struct qed_pf_iov *p_sriov;
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if (!IS_PF_SRIOV(p_hwfn)) {
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DP_VERBOSE(p_hwfn, QED_MSG_IOV,
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"No SR-IOV - no need for IOV db\n");
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return 0;
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}
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p_sriov = kzalloc(sizeof(*p_sriov), GFP_KERNEL);
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if (!p_sriov) {
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DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_sriov'\n");
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return -ENOMEM;
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}
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p_hwfn->pf_iov_info = p_sriov;
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return qed_iov_allocate_vfdb(p_hwfn);
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}
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void qed_iov_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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if (!IS_PF_SRIOV(p_hwfn) || !IS_PF_SRIOV_ALLOC(p_hwfn))
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return;
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qed_iov_setup_vfdb(p_hwfn);
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qed_iov_clear_vf_igu_blocks(p_hwfn, p_ptt);
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}
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void qed_iov_free(struct qed_hwfn *p_hwfn)
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{
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if (IS_PF_SRIOV_ALLOC(p_hwfn)) {
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qed_iov_free_vfdb(p_hwfn);
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kfree(p_hwfn->pf_iov_info);
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}
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}
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void qed_iov_free_hw_info(struct qed_dev *cdev)
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{
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kfree(cdev->p_iov_info);
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cdev->p_iov_info = NULL;
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}
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int qed_iov_hw_info(struct qed_hwfn *p_hwfn)
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{
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struct qed_dev *cdev = p_hwfn->cdev;
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int pos;
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int rc;
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/* Learn the PCI configuration */
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pos = pci_find_ext_capability(p_hwfn->cdev->pdev,
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PCI_EXT_CAP_ID_SRIOV);
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if (!pos) {
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DP_VERBOSE(p_hwfn, QED_MSG_IOV, "No PCIe IOV support\n");
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return 0;
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}
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/* Allocate a new struct for IOV information */
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cdev->p_iov_info = kzalloc(sizeof(*cdev->p_iov_info), GFP_KERNEL);
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if (!cdev->p_iov_info) {
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DP_NOTICE(p_hwfn, "Can't support IOV due to lack of memory\n");
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return -ENOMEM;
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}
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cdev->p_iov_info->pos = pos;
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rc = qed_iov_pci_cfg_info(cdev);
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if (rc)
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return rc;
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/* We want PF IOV to be synonemous with the existance of p_iov_info;
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* In case the capability is published but there are no VFs, simply
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* de-allocate the struct.
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*/
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if (!cdev->p_iov_info->total_vfs) {
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DP_VERBOSE(p_hwfn, QED_MSG_IOV,
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"IOV capabilities, but no VFs are published\n");
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kfree(cdev->p_iov_info);
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cdev->p_iov_info = NULL;
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return 0;
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}
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/* Calculate the first VF index - this is a bit tricky; Basically,
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* VFs start at offset 16 relative to PF0, and 2nd engine VFs begin
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* after the first engine's VFs.
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*/
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cdev->p_iov_info->first_vf_in_pf = p_hwfn->cdev->p_iov_info->offset +
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p_hwfn->abs_pf_id - 16;
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if (QED_PATH_ID(p_hwfn))
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cdev->p_iov_info->first_vf_in_pf -= MAX_NUM_VFS_BB;
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DP_VERBOSE(p_hwfn, QED_MSG_IOV,
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"First VF in hwfn 0x%08x\n",
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cdev->p_iov_info->first_vf_in_pf);
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return 0;
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}
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u16 qed_iov_get_next_active_vf(struct qed_hwfn *p_hwfn, u16 rel_vf_id)
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{
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struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
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u16 i;
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if (!p_iov)
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goto out;
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for (i = rel_vf_id; i < p_iov->total_vfs; i++)
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if (qed_iov_is_valid_vfid(p_hwfn, rel_vf_id, true))
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return i;
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out:
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return MAX_NUM_VFS;
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}
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