mirror of https://gitee.com/openkylin/linux.git
50 lines
1.9 KiB
Plaintext
50 lines
1.9 KiB
Plaintext
|
* CoreSight CPU Debug Component:
|
||
|
|
|
||
|
|
CoreSight CPU debug component are compliant with the ARMv8 architecture
|
||
|
|
reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
|
||
|
|
external debug module is mainly used for two modes: self-hosted debug and
|
||
|
|
external debug, and it can be accessed from mmio region from Coresight
|
||
|
|
and eventually the debug module connects with CPU for debugging. And the
|
||
|
|
debug module provides sample-based profiling extension, which can be used
|
||
|
|
to sample CPU program counter, secure state and exception level, etc;
|
||
|
|
usually every CPU has one dedicated debug module to be connected.
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
|
||
|
|
- compatible : should be "arm,coresight-cpu-debug"; supplemented with
|
||
|
|
"arm,primecell" since this driver is using the AMBA bus
|
||
|
|
interface.
|
||
|
|
|
||
|
|
- reg : physical base address and length of the register set.
|
||
|
|
|
||
|
|
- clocks : the clock associated to this component.
|
||
|
|
|
||
|
|
- clock-names : the name of the clock referenced by the code. Since we are
|
||
|
|
using the AMBA framework, the name of the clock providing
|
||
|
|
the interconnect should be "apb_pclk" and the clock is
|
||
|
|
mandatory. The interface between the debug logic and the
|
||
|
|
processor core is clocked by the internal CPU clock, so it
|
||
|
|
is enabled with CPU clock by default.
|
||
|
|
|
||
|
|
- cpu : the CPU phandle the debug module is affined to. When omitted
|
||
|
|
the module is considered to belong to CPU0.
|
||
|
|
|
||
|
|
Optional properties:
|
||
|
|
|
||
|
|
- power-domains: a phandle to the debug power domain. We use "power-domains"
|
||
|
|
binding to turn on the debug logic if it has own dedicated
|
||
|
|
power domain and if necessary to use "cpuidle.off=1" or
|
||
|
|
"nohlt" in the kernel command line or sysfs node to
|
||
|
|
constrain idle states to ensure registers in the CPU power
|
||
|
|
domain are accessible.
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
debug@f6590000 {
|
||
|
|
compatible = "arm,coresight-cpu-debug","arm,primecell";
|
||
|
|
reg = <0 0xf6590000 0 0x1000>;
|
||
|
|
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
cpu = <&cpu0>;
|
||
|
|
};
|