License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2012-06-07 05:28:31 +08:00
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/*
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* m5441xsim.h -- Coldfire 5441x register definitions
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*
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* (C) Copyright 2012, Steven King <sfking@fdwdc.com>
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*/
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#ifndef m5441xsim_h
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#define m5441xsim_h
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#define CPU_NAME "COLDFIRE(m5441x)"
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#define CPU_INSTR_PER_JIFFY 2
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#define MCF_BUSCLK (MCF_CLK / 2)
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2016-08-25 21:10:59 +08:00
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#define MACHINE MACH_M5441X
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2016-08-25 21:12:22 +08:00
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#define FPUTYPE 0
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2016-08-26 13:59:30 +08:00
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#define IOMEMBASE 0xe0000000
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#define IOMEMSIZE 0x20000000
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2012-06-07 05:28:31 +08:00
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#include <asm/m54xxacr.h>
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/*
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* Reset Controller Module.
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*/
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#define MCF_RCR 0xec090000
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#define MCF_RSR 0xec090001
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#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
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#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
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/*
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* Interrupt Controller Modules.
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*/
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/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
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#define MCFINT_VECBASE 64
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#define MCFINT0_VECBASE MCFINT_VECBASE
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#define MCFINT1_VECBASE (MCFINT0_VECBASE + 64)
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#define MCFINT2_VECBASE (MCFINT1_VECBASE + 64)
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/* interrupt controller 0 */
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#define MCFINTC0_SIMR 0xfc04801c
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#define MCFINTC0_CIMR 0xfc04801d
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#define MCFINTC0_ICR0 0xfc048040
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/* interrupt controller 1 */
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#define MCFINTC1_SIMR 0xfc04c01c
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#define MCFINTC1_CIMR 0xfc04c01d
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#define MCFINTC1_ICR0 0xfc04c040
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/* interrupt controller 2 */
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#define MCFINTC2_SIMR 0xfc05001c
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#define MCFINTC2_CIMR 0xfc05001d
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#define MCFINTC2_ICR0 0xfc050040
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/* on interrupt controller 0 */
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#define MCFINT0_EPORT0 1
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#define MCFINT0_UART0 26
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#define MCFINT0_UART1 27
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#define MCFINT0_UART2 28
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#define MCFINT0_UART3 29
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#define MCFINT0_I2C0 30
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#define MCFINT0_DSPI0 31
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#define MCFINT0_TIMER0 32
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#define MCFINT0_TIMER1 33
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#define MCFINT0_TIMER2 34
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#define MCFINT0_TIMER3 35
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#define MCFINT0_FECRX0 36
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#define MCFINT0_FECTX0 40
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#define MCFINT0_FECENTC0 42
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#define MCFINT0_FECRX1 49
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#define MCFINT0_FECTX1 53
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#define MCFINT0_FECENTC1 55
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/* on interrupt controller 1 */
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#define MCFINT1_UART4 48
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#define MCFINT1_UART5 49
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#define MCFINT1_UART6 50
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#define MCFINT1_UART7 51
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#define MCFINT1_UART8 52
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#define MCFINT1_UART9 53
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#define MCFINT1_DSPI1 54
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#define MCFINT1_DSPI2 55
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#define MCFINT1_DSPI3 56
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#define MCFINT1_I2C1 57
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#define MCFINT1_I2C2 58
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#define MCFINT1_I2C3 59
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#define MCFINT1_I2C4 60
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#define MCFINT1_I2C5 61
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/* on interrupt controller 2 */
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#define MCFINT2_PIT0 13
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#define MCFINT2_PIT1 14
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#define MCFINT2_PIT2 15
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#define MCFINT2_PIT3 16
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#define MCFINT2_RTC 26
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/*
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* PIT timer module.
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*/
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#define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */
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#define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
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#define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */
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#define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */
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#define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1)
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/*
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* Power Management
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*/
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#define MCFPM_WCR 0xfc040013
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#define MCFPM_PPMSR0 0xfc04002c
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#define MCFPM_PPMCR0 0xfc04002d
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#define MCFPM_PPMSR1 0xfc04002e
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#define MCFPM_PPMCR1 0xfc04002f
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#define MCFPM_PPMHR0 0xfc040030
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#define MCFPM_PPMLR0 0xfc040034
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#define MCFPM_PPMHR1 0xfc040038
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#define MCFPM_PPMLR1 0xfc04003c
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#define MCFPM_LPCR 0xec090007
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/*
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* UART module.
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*/
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#define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */
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#define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */
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#define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */
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#define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */
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#define MCFUART_BASE4 0xec060000 /* Base address of UART4 */
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#define MCFUART_BASE5 0xec064000 /* Base address of UART5 */
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#define MCFUART_BASE6 0xec068000 /* Base address of UART6 */
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#define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */
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#define MCFUART_BASE8 0xec070000 /* Base address of UART8 */
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#define MCFUART_BASE9 0xec074000 /* Base address of UART9 */
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#define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0)
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#define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1)
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#define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2)
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#define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3)
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#define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4)
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#define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5)
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#define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6)
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#define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7)
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#define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8)
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#define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9)
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/*
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* FEC modules.
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*/
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#define MCFFEC_BASE0 0xfc0d4000
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#define MCFFEC_SIZE0 0x800
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#define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0)
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#define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0)
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#define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0)
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#define MCFFEC_BASE1 0xfc0d8000
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#define MCFFEC_SIZE1 0x800
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#define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1)
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#define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1)
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#define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1)
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/*
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* I2C modules.
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*/
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#define MCFI2C_BASE0 0xfc058000
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#define MCFI2C_SIZE0 0x20
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#define MCFI2C_BASE1 0xfc038000
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#define MCFI2C_SIZE1 0x20
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#define MCFI2C_BASE2 0xec010000
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#define MCFI2C_SIZE2 0x20
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#define MCFI2C_BASE3 0xec014000
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#define MCFI2C_SIZE3 0x20
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#define MCFI2C_BASE4 0xec018000
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#define MCFI2C_SIZE4 0x20
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#define MCFI2C_BASE5 0xec01c000
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#define MCFI2C_SIZE5 0x20
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#define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0)
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#define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1)
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#define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2)
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#define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3)
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#define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4)
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#define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5)
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/*
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* EPORT Module.
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*/
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#define MCFEPORT_EPPAR 0xfc090000
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#define MCFEPORT_EPIER 0xfc090003
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#define MCFEPORT_EPFR 0xfc090006
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2012-06-17 16:03:38 +08:00
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/*
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* RTC Module.
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*/
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#define MCFRTC_BASE 0xfc0a8000
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#define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000)
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#define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC)
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2012-06-07 05:28:31 +08:00
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/*
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* GPIO Module.
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*/
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#define MCFGPIO_PODR_A 0xec094000
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#define MCFGPIO_PODR_B 0xec094001
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#define MCFGPIO_PODR_C 0xec094002
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#define MCFGPIO_PODR_D 0xec094003
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#define MCFGPIO_PODR_E 0xec094004
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#define MCFGPIO_PODR_F 0xec094005
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#define MCFGPIO_PODR_G 0xec094006
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#define MCFGPIO_PODR_H 0xec094007
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#define MCFGPIO_PODR_I 0xec094008
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#define MCFGPIO_PODR_J 0xec094009
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#define MCFGPIO_PODR_K 0xec09400a
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#define MCFGPIO_PDDR_A 0xec09400c
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#define MCFGPIO_PDDR_B 0xec09400d
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#define MCFGPIO_PDDR_C 0xec09400e
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#define MCFGPIO_PDDR_D 0xec09400f
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#define MCFGPIO_PDDR_E 0xec094010
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#define MCFGPIO_PDDR_F 0xec094011
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#define MCFGPIO_PDDR_G 0xec094012
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#define MCFGPIO_PDDR_H 0xec094013
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#define MCFGPIO_PDDR_I 0xec094014
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#define MCFGPIO_PDDR_J 0xec094015
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#define MCFGPIO_PDDR_K 0xec094016
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#define MCFGPIO_PPDSDR_A 0xec094018
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#define MCFGPIO_PPDSDR_B 0xec094019
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#define MCFGPIO_PPDSDR_C 0xec09401a
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#define MCFGPIO_PPDSDR_D 0xec09401b
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#define MCFGPIO_PPDSDR_E 0xec09401c
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#define MCFGPIO_PPDSDR_F 0xec09401d
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#define MCFGPIO_PPDSDR_G 0xec09401e
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#define MCFGPIO_PPDSDR_H 0xec09401f
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#define MCFGPIO_PPDSDR_I 0xec094020
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#define MCFGPIO_PPDSDR_J 0xec094021
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#define MCFGPIO_PPDSDR_K 0xec094022
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#define MCFGPIO_PCLRR_A 0xec094024
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#define MCFGPIO_PCLRR_B 0xec094025
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#define MCFGPIO_PCLRR_C 0xec094026
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#define MCFGPIO_PCLRR_D 0xec094027
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#define MCFGPIO_PCLRR_E 0xec094028
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#define MCFGPIO_PCLRR_F 0xec094029
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#define MCFGPIO_PCLRR_G 0xec09402a
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#define MCFGPIO_PCLRR_H 0xec09402b
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#define MCFGPIO_PCLRR_I 0xec09402c
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#define MCFGPIO_PCLRR_J 0xec09402d
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#define MCFGPIO_PCLRR_K 0xec09402e
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#define MCFGPIO_PAR_FBCTL 0xec094048
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#define MCFGPIO_PAR_BE 0xec094049
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#define MCFGPIO_PAR_CS 0xec09404a
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#define MCFGPIO_PAR_CANI2C 0xec09404b
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#define MCFGPIO_PAR_IRQ0H 0xec09404c
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#define MCFGPIO_PAR_IRQ0L 0xec09404d
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#define MCFGPIO_PAR_DSPIOWH 0xec09404e
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#define MCFGPIO_PAR_DSPIOWL 0xec09404f
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#define MCFGPIO_PAR_TIMER 0xec094050
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#define MCFGPIO_PAR_UART2 0xec094051
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#define MCFGPIO_PAR_UART1 0xec094052
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#define MCFGPIO_PAR_UART0 0xec094053
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#define MCFGPIO_PAR_SDHCH 0xec094054
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#define MCFGPIO_PAR_SDHCL 0xec094055
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#define MCFGPIO_PAR_SIMP0H 0xec094056
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#define MCFGPIO_PAR_SIMP0L 0xec094057
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#define MCFGPIO_PAR_SSI0H 0xec094058
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#define MCFGPIO_PAR_SSI0L 0xec094059
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#define MCFGPIO_PAR_DEBUGH1 0xec09405a
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#define MCFGPIO_PAR_DEBUGH0 0xec09405b
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#define MCFGPIO_PAR_DEBUGl 0xec09405c
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#define MCFGPIO_PAR_FEC 0xec09405e
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/* generalization for generic gpio support */
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#define MCFGPIO_PODR MCFGPIO_PODR_A
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#define MCFGPIO_PDDR MCFGPIO_PDDR_A
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#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A
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#define MCFGPIO_SETR MCFGPIO_PPDSDR_A
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#define MCFGPIO_CLRR MCFGPIO_PCLRR_A
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#define MCFGPIO_IRQ_MIN 17
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#define MCFGPIO_IRQ_MAX 24
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#define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
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#define MCFGPIO_PIN_MAX 87
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#endif /* m5441xsim_h */
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