2013-01-25 19:06:53 +08:00
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synopsys DWC3 CORE
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DWC3- USB3 CONTROLLER
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Required properties:
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2013-07-03 02:20:24 +08:00
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- compatible: must be "snps,dwc3"
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2013-01-25 19:06:53 +08:00
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- reg : Address and length of the register set for the device
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- interrupts: Interrupts used by the dwc3 controller.
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2014-03-03 19:38:11 +08:00
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Optional properties:
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2013-08-09 23:40:32 +08:00
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- usb-phy : array of phandle for the PHY device. The first element
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in the array is expected to be a handle to the USB2/HS PHY and
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the second element is expected to be a handle to the USB3/SS PHY
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2014-03-03 19:38:11 +08:00
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- phys: from the *Generic PHY* bindings
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- phy-names: from the *Generic PHY* bindings
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2013-01-25 19:06:53 +08:00
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- tx-fifo-resize: determines if the FIFO *has* to be reallocated.
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2014-10-28 19:54:25 +08:00
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- snps,disable_scramble_quirk: true when SW should disable data scrambling.
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Only really useful for FPGA builds.
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2013-01-25 19:06:53 +08:00
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This is usually a subnode to DWC3 glue to which it is connected.
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dwc3@4a030000 {
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2013-07-03 02:20:24 +08:00
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compatible = "snps,dwc3";
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2013-01-25 19:06:53 +08:00
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reg = <0x4a030000 0xcfff>;
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interrupts = <0 92 4>
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usb-phy = <&usb2_phy>, <&usb3,phy>;
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tx-fifo-resize;
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};
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