2012-07-19 06:07:18 +08:00
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/*
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2015-06-05 21:24:52 +08:00
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* Copyright (C) 2012-2015 Altera Corporation
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2012-07-19 06:07:18 +08:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2012-11-06 06:18:28 +08:00
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#include <linux/irqchip.h>
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2012-10-26 00:41:39 +08:00
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#include <linux/of_address.h>
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2012-07-19 06:07:18 +08:00
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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2013-07-09 07:01:40 +08:00
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#include <linux/reboot.h>
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2012-07-19 06:07:18 +08:00
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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2012-10-26 00:41:39 +08:00
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#include <asm/mach/map.h>
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2015-02-26 00:24:25 +08:00
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#include <asm/cacheflush.h>
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2012-07-19 06:07:18 +08:00
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2012-10-26 00:41:39 +08:00
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#include "core.h"
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void __iomem *sys_manager_base_addr;
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void __iomem *rst_manager_base_addr;
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2015-06-05 21:24:52 +08:00
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void __iomem *sdr_ctl_base_addr;
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arm: socfpga: fix fetching cpu1start_addr for SMP
When CPU1 is brought out of reset, it's MMU is not turned on yet, so it will
only be able to use physical addresses. For systems with that have the
MMU page configured for 0xC0000000, 0x80000000, or 0x40000000
"BIC 0x40000000" will work just fine, as it was just converting the
virtual address of &cpu1start_addr into a physical address, ie. 0xC0000000
became 0x80000000. So for systems where the SDRAM controller was able to do a
wrap-around access, this was working fine, as it was just dropping the MSB,
but for systems where out of bounds memory access is not allowed, this would
not allow CPU1 to correctly fetch &cpu1start_addr.
This patch fixes the secondary_trampoline code to correctly fetch the
physical address of cpu1start_addr directly. The patch will subtract the
correct PAGE_OFFSET from &cpu1start_addr. And since on this platform, the
physical memory will always start at 0x0, subtracting PAGE_OFFSET from
&cpu1start_addr will allow CPU1 to correctly fetch the value of cpu1start_addr.
While at it, change the name of cpu1start_addr to socfpga_cpu1start_addr
to avoid any future naming collisions for multiplatform image.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v4: Updated commit log to correctly lay out the usage of PAGE_OFFSET and
add comments to the same effect.
v3: Used PAGE_OFFSET to get the physical address
v2: Correctly get the physical address instead of just a BIC hack.
2014-10-01 18:44:48 +08:00
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unsigned long socfpga_cpu1start_addr;
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2012-10-26 00:41:39 +08:00
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void __init socfpga_sysmgr_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
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2013-02-12 07:30:33 +08:00
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if (of_property_read_u32(np, "cpu1-start-addr",
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arm: socfpga: fix fetching cpu1start_addr for SMP
When CPU1 is brought out of reset, it's MMU is not turned on yet, so it will
only be able to use physical addresses. For systems with that have the
MMU page configured for 0xC0000000, 0x80000000, or 0x40000000
"BIC 0x40000000" will work just fine, as it was just converting the
virtual address of &cpu1start_addr into a physical address, ie. 0xC0000000
became 0x80000000. So for systems where the SDRAM controller was able to do a
wrap-around access, this was working fine, as it was just dropping the MSB,
but for systems where out of bounds memory access is not allowed, this would
not allow CPU1 to correctly fetch &cpu1start_addr.
This patch fixes the secondary_trampoline code to correctly fetch the
physical address of cpu1start_addr directly. The patch will subtract the
correct PAGE_OFFSET from &cpu1start_addr. And since on this platform, the
physical memory will always start at 0x0, subtracting PAGE_OFFSET from
&cpu1start_addr will allow CPU1 to correctly fetch the value of cpu1start_addr.
While at it, change the name of cpu1start_addr to socfpga_cpu1start_addr
to avoid any future naming collisions for multiplatform image.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v4: Updated commit log to correctly lay out the usage of PAGE_OFFSET and
add comments to the same effect.
v3: Used PAGE_OFFSET to get the physical address
v2: Correctly get the physical address instead of just a BIC hack.
2014-10-01 18:44:48 +08:00
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(u32 *) &socfpga_cpu1start_addr))
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2013-02-12 07:30:33 +08:00
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pr_err("SMP: Need cpu1-start-addr in device tree.\n");
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2015-02-26 00:24:25 +08:00
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/* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
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smp_wmb();
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sync_cache_w(&socfpga_cpu1start_addr);
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2012-10-26 00:41:39 +08:00
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sys_manager_base_addr = of_iomap(np, 0);
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np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
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rst_manager_base_addr = of_iomap(np, 0);
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2015-06-05 21:24:52 +08:00
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np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
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sdr_ctl_base_addr = of_iomap(np, 0);
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2012-10-26 00:41:39 +08:00
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}
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2012-11-06 06:18:28 +08:00
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static void __init socfpga_init_irq(void)
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2012-07-19 06:07:18 +08:00
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{
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2012-11-06 06:18:28 +08:00
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irqchip_init();
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2012-10-26 00:41:39 +08:00
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socfpga_sysmgr_init();
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2012-07-19 06:07:18 +08:00
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}
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2013-07-09 07:01:40 +08:00
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static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
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2012-07-19 06:07:18 +08:00
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{
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2013-04-11 23:55:24 +08:00
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u32 temp;
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temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
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2013-07-09 07:01:40 +08:00
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if (mode == REBOOT_HARD)
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2013-04-11 23:55:24 +08:00
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temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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else
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temp |= RSTMGR_CTRL_SWWARMRSTREQ;
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writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
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2012-07-19 06:07:18 +08:00
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}
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2015-07-21 00:23:13 +08:00
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static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
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{
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u32 temp;
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temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
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if (mode == REBOOT_HARD)
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temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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else
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temp |= RSTMGR_CTRL_SWWARMRSTREQ;
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writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
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}
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2012-07-19 06:07:18 +08:00
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static const char *altera_dt_match[] = {
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"altr,socfpga",
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NULL
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};
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DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
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2014-04-28 22:55:59 +08:00
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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2012-11-06 06:18:28 +08:00
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.init_irq = socfpga_init_irq,
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2012-07-19 06:07:18 +08:00
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.restart = socfpga_cyclone5_restart,
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.dt_compat = altera_dt_match,
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MACHINE_END
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2015-07-21 00:23:13 +08:00
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static const char *altera_a10_dt_match[] = {
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"altr,socfpga-arria10",
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NULL
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};
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DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = socfpga_init_irq,
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.restart = socfpga_arria10_restart,
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.dt_compat = altera_a10_dt_match,
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MACHINE_END
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