mirror of https://gitee.com/openkylin/linux.git
504 lines
13 KiB
ArmAsm
504 lines
13 KiB
ArmAsm
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#define __ARM_ARCH__ __LINUX_ARM_ARCH__
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@ ====================================================================
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@ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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@ project. The module is, however, dual licensed under OpenSSL and
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@ CRYPTOGAMS licenses depending on where you obtain it. For further
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@ details see http://www.openssl.org/~appro/cryptogams/.
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@ ====================================================================
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@ sha1_block procedure for ARMv4.
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@
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@ January 2007.
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@ Size/performance trade-off
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@ ====================================================================
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@ impl size in bytes comp cycles[*] measured performance
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@ ====================================================================
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@ thumb 304 3212 4420
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@ armv4-small 392/+29% 1958/+64% 2250/+96%
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@ armv4-compact 740/+89% 1552/+26% 1840/+22%
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@ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
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@ full unroll ~5100/+260% ~1260/+4% ~1300/+5%
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@ ====================================================================
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@ thumb = same as 'small' but in Thumb instructions[**] and
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@ with recurring code in two private functions;
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@ small = detached Xload/update, loops are folded;
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@ compact = detached Xload/update, 5x unroll;
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@ large = interleaved Xload/update, 5x unroll;
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@ full unroll = interleaved Xload/update, full unroll, estimated[!];
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@
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@ [*] Manually counted instructions in "grand" loop body. Measured
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@ performance is affected by prologue and epilogue overhead,
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@ i-cache availability, branch penalties, etc.
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@ [**] While each Thumb instruction is twice smaller, they are not as
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@ diverse as ARM ones: e.g., there are only two arithmetic
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@ instructions with 3 arguments, no [fixed] rotate, addressing
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@ modes are limited. As result it takes more instructions to do
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@ the same job in Thumb, therefore the code is never twice as
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@ small and always slower.
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@ [***] which is also ~35% better than compiler generated code. Dual-
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@ issue Cortex A8 core was measured to process input block in
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@ ~990 cycles.
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@ August 2010.
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@
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@ Rescheduling for dual-issue pipeline resulted in 13% improvement on
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@ Cortex A8 core and in absolute terms ~870 cycles per input block
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@ [or 13.6 cycles per byte].
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@ February 2011.
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@
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@ Profiler-assisted and platform-specific optimization resulted in 10%
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@ improvement on Cortex A8 core and 12.2 cycles per byte.
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.text
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.global sha1_block_data_order
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.type sha1_block_data_order,%function
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.align 2
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sha1_block_data_order:
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stmdb sp!,{r4-r12,lr}
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add r2,r1,r2,lsl#6 @ r2 to point at the end of r1
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ldmia r0,{r3,r4,r5,r6,r7}
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.Lloop:
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ldr r8,.LK_00_19
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mov r14,sp
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sub sp,sp,#15*4
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mov r5,r5,ror#30
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mov r6,r6,ror#30
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mov r7,r7,ror#30 @ [6]
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.L_00_15:
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#if __ARM_ARCH__<7
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ldrb r10,[r1,#2]
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ldrb r9,[r1,#3]
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ldrb r11,[r1,#1]
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add r7,r8,r7,ror#2 @ E+=K_00_19
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ldrb r12,[r1],#4
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orr r9,r9,r10,lsl#8
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eor r10,r5,r6 @ F_xx_xx
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orr r9,r9,r11,lsl#16
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add r7,r7,r3,ror#27 @ E+=ROR(A,27)
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orr r9,r9,r12,lsl#24
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#else
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ldr r9,[r1],#4 @ handles unaligned
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add r7,r8,r7,ror#2 @ E+=K_00_19
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eor r10,r5,r6 @ F_xx_xx
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add r7,r7,r3,ror#27 @ E+=ROR(A,27)
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#ifdef __ARMEL__
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rev r9,r9 @ byte swap
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#endif
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#endif
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and r10,r4,r10,ror#2
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add r7,r7,r9 @ E+=X[i]
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eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
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str r9,[r14,#-4]!
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add r7,r7,r10 @ E+=F_00_19(B,C,D)
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#if __ARM_ARCH__<7
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ldrb r10,[r1,#2]
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ldrb r9,[r1,#3]
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ldrb r11,[r1,#1]
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add r6,r8,r6,ror#2 @ E+=K_00_19
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ldrb r12,[r1],#4
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orr r9,r9,r10,lsl#8
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eor r10,r4,r5 @ F_xx_xx
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orr r9,r9,r11,lsl#16
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add r6,r6,r7,ror#27 @ E+=ROR(A,27)
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orr r9,r9,r12,lsl#24
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#else
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ldr r9,[r1],#4 @ handles unaligned
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add r6,r8,r6,ror#2 @ E+=K_00_19
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eor r10,r4,r5 @ F_xx_xx
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add r6,r6,r7,ror#27 @ E+=ROR(A,27)
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#ifdef __ARMEL__
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rev r9,r9 @ byte swap
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#endif
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#endif
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and r10,r3,r10,ror#2
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add r6,r6,r9 @ E+=X[i]
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eor r10,r10,r5,ror#2 @ F_00_19(B,C,D)
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str r9,[r14,#-4]!
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add r6,r6,r10 @ E+=F_00_19(B,C,D)
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#if __ARM_ARCH__<7
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ldrb r10,[r1,#2]
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ldrb r9,[r1,#3]
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ldrb r11,[r1,#1]
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add r5,r8,r5,ror#2 @ E+=K_00_19
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ldrb r12,[r1],#4
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orr r9,r9,r10,lsl#8
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eor r10,r3,r4 @ F_xx_xx
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orr r9,r9,r11,lsl#16
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add r5,r5,r6,ror#27 @ E+=ROR(A,27)
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orr r9,r9,r12,lsl#24
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#else
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ldr r9,[r1],#4 @ handles unaligned
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add r5,r8,r5,ror#2 @ E+=K_00_19
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eor r10,r3,r4 @ F_xx_xx
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add r5,r5,r6,ror#27 @ E+=ROR(A,27)
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#ifdef __ARMEL__
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rev r9,r9 @ byte swap
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#endif
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#endif
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and r10,r7,r10,ror#2
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add r5,r5,r9 @ E+=X[i]
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eor r10,r10,r4,ror#2 @ F_00_19(B,C,D)
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str r9,[r14,#-4]!
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add r5,r5,r10 @ E+=F_00_19(B,C,D)
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#if __ARM_ARCH__<7
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ldrb r10,[r1,#2]
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ldrb r9,[r1,#3]
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ldrb r11,[r1,#1]
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add r4,r8,r4,ror#2 @ E+=K_00_19
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ldrb r12,[r1],#4
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orr r9,r9,r10,lsl#8
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eor r10,r7,r3 @ F_xx_xx
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orr r9,r9,r11,lsl#16
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add r4,r4,r5,ror#27 @ E+=ROR(A,27)
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orr r9,r9,r12,lsl#24
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#else
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ldr r9,[r1],#4 @ handles unaligned
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add r4,r8,r4,ror#2 @ E+=K_00_19
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eor r10,r7,r3 @ F_xx_xx
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add r4,r4,r5,ror#27 @ E+=ROR(A,27)
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#ifdef __ARMEL__
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rev r9,r9 @ byte swap
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#endif
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#endif
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and r10,r6,r10,ror#2
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add r4,r4,r9 @ E+=X[i]
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eor r10,r10,r3,ror#2 @ F_00_19(B,C,D)
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str r9,[r14,#-4]!
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add r4,r4,r10 @ E+=F_00_19(B,C,D)
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#if __ARM_ARCH__<7
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ldrb r10,[r1,#2]
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ldrb r9,[r1,#3]
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ldrb r11,[r1,#1]
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add r3,r8,r3,ror#2 @ E+=K_00_19
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ldrb r12,[r1],#4
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orr r9,r9,r10,lsl#8
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eor r10,r6,r7 @ F_xx_xx
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orr r9,r9,r11,lsl#16
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add r3,r3,r4,ror#27 @ E+=ROR(A,27)
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orr r9,r9,r12,lsl#24
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#else
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ldr r9,[r1],#4 @ handles unaligned
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add r3,r8,r3,ror#2 @ E+=K_00_19
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eor r10,r6,r7 @ F_xx_xx
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add r3,r3,r4,ror#27 @ E+=ROR(A,27)
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#ifdef __ARMEL__
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rev r9,r9 @ byte swap
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#endif
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#endif
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and r10,r5,r10,ror#2
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add r3,r3,r9 @ E+=X[i]
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eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
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str r9,[r14,#-4]!
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add r3,r3,r10 @ E+=F_00_19(B,C,D)
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teq r14,sp
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bne .L_00_15 @ [((11+4)*5+2)*3]
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#if __ARM_ARCH__<7
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ldrb r10,[r1,#2]
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ldrb r9,[r1,#3]
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ldrb r11,[r1,#1]
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add r7,r8,r7,ror#2 @ E+=K_00_19
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ldrb r12,[r1],#4
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orr r9,r9,r10,lsl#8
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eor r10,r5,r6 @ F_xx_xx
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orr r9,r9,r11,lsl#16
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add r7,r7,r3,ror#27 @ E+=ROR(A,27)
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orr r9,r9,r12,lsl#24
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#else
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ldr r9,[r1],#4 @ handles unaligned
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add r7,r8,r7,ror#2 @ E+=K_00_19
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eor r10,r5,r6 @ F_xx_xx
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add r7,r7,r3,ror#27 @ E+=ROR(A,27)
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#ifdef __ARMEL__
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rev r9,r9 @ byte swap
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#endif
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#endif
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and r10,r4,r10,ror#2
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add r7,r7,r9 @ E+=X[i]
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eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
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str r9,[r14,#-4]!
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add r7,r7,r10 @ E+=F_00_19(B,C,D)
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ldr r9,[r14,#15*4]
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ldr r10,[r14,#13*4]
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ldr r11,[r14,#7*4]
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add r6,r8,r6,ror#2 @ E+=K_xx_xx
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ldr r12,[r14,#2*4]
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eor r9,r9,r10
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eor r11,r11,r12 @ 1 cycle stall
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eor r10,r4,r5 @ F_xx_xx
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mov r9,r9,ror#31
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add r6,r6,r7,ror#27 @ E+=ROR(A,27)
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eor r9,r9,r11,ror#31
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str r9,[r14,#-4]!
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and r10,r3,r10,ror#2 @ F_xx_xx
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@ F_xx_xx
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add r6,r6,r9 @ E+=X[i]
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eor r10,r10,r5,ror#2 @ F_00_19(B,C,D)
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add r6,r6,r10 @ E+=F_00_19(B,C,D)
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ldr r9,[r14,#15*4]
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ldr r10,[r14,#13*4]
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ldr r11,[r14,#7*4]
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add r5,r8,r5,ror#2 @ E+=K_xx_xx
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ldr r12,[r14,#2*4]
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eor r9,r9,r10
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eor r11,r11,r12 @ 1 cycle stall
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eor r10,r3,r4 @ F_xx_xx
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mov r9,r9,ror#31
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add r5,r5,r6,ror#27 @ E+=ROR(A,27)
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eor r9,r9,r11,ror#31
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str r9,[r14,#-4]!
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and r10,r7,r10,ror#2 @ F_xx_xx
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@ F_xx_xx
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add r5,r5,r9 @ E+=X[i]
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eor r10,r10,r4,ror#2 @ F_00_19(B,C,D)
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add r5,r5,r10 @ E+=F_00_19(B,C,D)
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ldr r9,[r14,#15*4]
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ldr r10,[r14,#13*4]
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ldr r11,[r14,#7*4]
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add r4,r8,r4,ror#2 @ E+=K_xx_xx
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ldr r12,[r14,#2*4]
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eor r9,r9,r10
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eor r11,r11,r12 @ 1 cycle stall
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eor r10,r7,r3 @ F_xx_xx
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mov r9,r9,ror#31
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add r4,r4,r5,ror#27 @ E+=ROR(A,27)
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eor r9,r9,r11,ror#31
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str r9,[r14,#-4]!
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and r10,r6,r10,ror#2 @ F_xx_xx
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@ F_xx_xx
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add r4,r4,r9 @ E+=X[i]
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eor r10,r10,r3,ror#2 @ F_00_19(B,C,D)
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add r4,r4,r10 @ E+=F_00_19(B,C,D)
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ldr r9,[r14,#15*4]
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ldr r10,[r14,#13*4]
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ldr r11,[r14,#7*4]
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add r3,r8,r3,ror#2 @ E+=K_xx_xx
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ldr r12,[r14,#2*4]
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eor r9,r9,r10
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eor r11,r11,r12 @ 1 cycle stall
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eor r10,r6,r7 @ F_xx_xx
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mov r9,r9,ror#31
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add r3,r3,r4,ror#27 @ E+=ROR(A,27)
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eor r9,r9,r11,ror#31
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str r9,[r14,#-4]!
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and r10,r5,r10,ror#2 @ F_xx_xx
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@ F_xx_xx
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add r3,r3,r9 @ E+=X[i]
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eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
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add r3,r3,r10 @ E+=F_00_19(B,C,D)
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ldr r8,.LK_20_39 @ [+15+16*4]
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sub sp,sp,#25*4
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cmn sp,#0 @ [+3], clear carry to denote 20_39
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.L_20_39_or_60_79:
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ldr r9,[r14,#15*4]
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ldr r10,[r14,#13*4]
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ldr r11,[r14,#7*4]
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add r7,r8,r7,ror#2 @ E+=K_xx_xx
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ldr r12,[r14,#2*4]
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eor r9,r9,r10
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eor r11,r11,r12 @ 1 cycle stall
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eor r10,r5,r6 @ F_xx_xx
|
||
|
|
mov r9,r9,ror#31
|
||
|
|
add r7,r7,r3,ror#27 @ E+=ROR(A,27)
|
||
|
|
eor r9,r9,r11,ror#31
|
||
|
|
str r9,[r14,#-4]!
|
||
|
|
eor r10,r4,r10,ror#2 @ F_xx_xx
|
||
|
|
@ F_xx_xx
|
||
|
|
add r7,r7,r9 @ E+=X[i]
|
||
|
|
add r7,r7,r10 @ E+=F_20_39(B,C,D)
|
||
|
|
ldr r9,[r14,#15*4]
|
||
|
|
ldr r10,[r14,#13*4]
|
||
|
|
ldr r11,[r14,#7*4]
|
||
|
|
add r6,r8,r6,ror#2 @ E+=K_xx_xx
|
||
|
|
ldr r12,[r14,#2*4]
|
||
|
|
eor r9,r9,r10
|
||
|
|
eor r11,r11,r12 @ 1 cycle stall
|
||
|
|
eor r10,r4,r5 @ F_xx_xx
|
||
|
|
mov r9,r9,ror#31
|
||
|
|
add r6,r6,r7,ror#27 @ E+=ROR(A,27)
|
||
|
|
eor r9,r9,r11,ror#31
|
||
|
|
str r9,[r14,#-4]!
|
||
|
|
eor r10,r3,r10,ror#2 @ F_xx_xx
|
||
|
|
@ F_xx_xx
|
||
|
|
add r6,r6,r9 @ E+=X[i]
|
||
|
|
add r6,r6,r10 @ E+=F_20_39(B,C,D)
|
||
|
|
ldr r9,[r14,#15*4]
|
||
|
|
ldr r10,[r14,#13*4]
|
||
|
|
ldr r11,[r14,#7*4]
|
||
|
|
add r5,r8,r5,ror#2 @ E+=K_xx_xx
|
||
|
|
ldr r12,[r14,#2*4]
|
||
|
|
eor r9,r9,r10
|
||
|
|
eor r11,r11,r12 @ 1 cycle stall
|
||
|
|
eor r10,r3,r4 @ F_xx_xx
|
||
|
|
mov r9,r9,ror#31
|
||
|
|
add r5,r5,r6,ror#27 @ E+=ROR(A,27)
|
||
|
|
eor r9,r9,r11,ror#31
|
||
|
|
str r9,[r14,#-4]!
|
||
|
|
eor r10,r7,r10,ror#2 @ F_xx_xx
|
||
|
|
@ F_xx_xx
|
||
|
|
add r5,r5,r9 @ E+=X[i]
|
||
|
|
add r5,r5,r10 @ E+=F_20_39(B,C,D)
|
||
|
|
ldr r9,[r14,#15*4]
|
||
|
|
ldr r10,[r14,#13*4]
|
||
|
|
ldr r11,[r14,#7*4]
|
||
|
|
add r4,r8,r4,ror#2 @ E+=K_xx_xx
|
||
|
|
ldr r12,[r14,#2*4]
|
||
|
|
eor r9,r9,r10
|
||
|
|
eor r11,r11,r12 @ 1 cycle stall
|
||
|
|
eor r10,r7,r3 @ F_xx_xx
|
||
|
|
mov r9,r9,ror#31
|
||
|
|
add r4,r4,r5,ror#27 @ E+=ROR(A,27)
|
||
|
|
eor r9,r9,r11,ror#31
|
||
|
|
str r9,[r14,#-4]!
|
||
|
|
eor r10,r6,r10,ror#2 @ F_xx_xx
|
||
|
|
@ F_xx_xx
|
||
|
|
add r4,r4,r9 @ E+=X[i]
|
||
|
|
add r4,r4,r10 @ E+=F_20_39(B,C,D)
|
||
|
|
ldr r9,[r14,#15*4]
|
||
|
|
ldr r10,[r14,#13*4]
|
||
|
|
ldr r11,[r14,#7*4]
|
||
|
|
add r3,r8,r3,ror#2 @ E+=K_xx_xx
|
||
|
|
ldr r12,[r14,#2*4]
|
||
|
|
eor r9,r9,r10
|
||
|
|
eor r11,r11,r12 @ 1 cycle stall
|
||
|
|
eor r10,r6,r7 @ F_xx_xx
|
||
|
|
mov r9,r9,ror#31
|
||
|
|
add r3,r3,r4,ror#27 @ E+=ROR(A,27)
|
||
|
|
eor r9,r9,r11,ror#31
|
||
|
|
str r9,[r14,#-4]!
|
||
|
|
eor r10,r5,r10,ror#2 @ F_xx_xx
|
||
|
|
@ F_xx_xx
|
||
|
|
add r3,r3,r9 @ E+=X[i]
|
||
|
|
add r3,r3,r10 @ E+=F_20_39(B,C,D)
|
||
|
|
teq r14,sp @ preserve carry
|
||
|
|
bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
|
||
|
|
bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
|
||
|
|
|
||
|
|
ldr r8,.LK_40_59
|
||
|
|
sub sp,sp,#20*4 @ [+2]
|
||
|
|
.L_40_59:
|
||
|
|
ldr r9,[r14,#15*4]
|
||
|
|
ldr r10,[r14,#13*4]
|
||
|
|
ldr r11,[r14,#7*4]
|
||
|
|
add r7,r8,r7,ror#2 @ E+=K_xx_xx
|
||
|
|
ldr r12,[r14,#2*4]
|
||
|
|
eor r9,r9,r10
|
||
|
|
eor r11,r11,r12 @ 1 cycle stall
|
||
|
|
eor r10,r5,r6 @ F_xx_xx
|
||
|
|
mov r9,r9,ror#31
|
||
|
|
add r7,r7,r3,ror#27 @ E+=ROR(A,27)
|
||
|
|
eor r9,r9,r11,ror#31
|
||
|
|
str r9,[r14,#-4]!
|
||
|
|
and r10,r4,r10,ror#2 @ F_xx_xx
|
||
|
|
and r11,r5,r6 @ F_xx_xx
|
||
|
|
add r7,r7,r9 @ E+=X[i]
|
||
|
|
add r7,r7,r10 @ E+=F_40_59(B,C,D)
|
||
|
|
add r7,r7,r11,ror#2
|
||
|
|
ldr r9,[r14,#15*4]
|
||
|
|
ldr r10,[r14,#13*4]
|
||
|
|
ldr r11,[r14,#7*4]
|
||
|
|
add r6,r8,r6,ror#2 @ E+=K_xx_xx
|
||
|
|
ldr r12,[r14,#2*4]
|
||
|
|
eor r9,r9,r10
|
||
|
|
eor r11,r11,r12 @ 1 cycle stall
|
||
|
|
eor r10,r4,r5 @ F_xx_xx
|
||
|
|
mov r9,r9,ror#31
|
||
|
|
add r6,r6,r7,ror#27 @ E+=ROR(A,27)
|
||
|
|
eor r9,r9,r11,ror#31
|
||
|
|
str r9,[r14,#-4]!
|
||
|
|
and r10,r3,r10,ror#2 @ F_xx_xx
|
||
|
|
and r11,r4,r5 @ F_xx_xx
|
||
|
|
add r6,r6,r9 @ E+=X[i]
|
||
|
|
add r6,r6,r10 @ E+=F_40_59(B,C,D)
|
||
|
|
add r6,r6,r11,ror#2
|
||
|
|
ldr r9,[r14,#15*4]
|
||
|
|
ldr r10,[r14,#13*4]
|
||
|
|
ldr r11,[r14,#7*4]
|
||
|
|
add r5,r8,r5,ror#2 @ E+=K_xx_xx
|
||
|
|
ldr r12,[r14,#2*4]
|
||
|
|
eor r9,r9,r10
|
||
|
|
eor r11,r11,r12 @ 1 cycle stall
|
||
|
|
eor r10,r3,r4 @ F_xx_xx
|
||
|
|
mov r9,r9,ror#31
|
||
|
|
add r5,r5,r6,ror#27 @ E+=ROR(A,27)
|
||
|
|
eor r9,r9,r11,ror#31
|
||
|
|
str r9,[r14,#-4]!
|
||
|
|
and r10,r7,r10,ror#2 @ F_xx_xx
|
||
|
|
and r11,r3,r4 @ F_xx_xx
|
||
|
|
add r5,r5,r9 @ E+=X[i]
|
||
|
|
add r5,r5,r10 @ E+=F_40_59(B,C,D)
|
||
|
|
add r5,r5,r11,ror#2
|
||
|
|
ldr r9,[r14,#15*4]
|
||
|
|
ldr r10,[r14,#13*4]
|
||
|
|
ldr r11,[r14,#7*4]
|
||
|
|
add r4,r8,r4,ror#2 @ E+=K_xx_xx
|
||
|
|
ldr r12,[r14,#2*4]
|
||
|
|
eor r9,r9,r10
|
||
|
|
eor r11,r11,r12 @ 1 cycle stall
|
||
|
|
eor r10,r7,r3 @ F_xx_xx
|
||
|
|
mov r9,r9,ror#31
|
||
|
|
add r4,r4,r5,ror#27 @ E+=ROR(A,27)
|
||
|
|
eor r9,r9,r11,ror#31
|
||
|
|
str r9,[r14,#-4]!
|
||
|
|
and r10,r6,r10,ror#2 @ F_xx_xx
|
||
|
|
and r11,r7,r3 @ F_xx_xx
|
||
|
|
add r4,r4,r9 @ E+=X[i]
|
||
|
|
add r4,r4,r10 @ E+=F_40_59(B,C,D)
|
||
|
|
add r4,r4,r11,ror#2
|
||
|
|
ldr r9,[r14,#15*4]
|
||
|
|
ldr r10,[r14,#13*4]
|
||
|
|
ldr r11,[r14,#7*4]
|
||
|
|
add r3,r8,r3,ror#2 @ E+=K_xx_xx
|
||
|
|
ldr r12,[r14,#2*4]
|
||
|
|
eor r9,r9,r10
|
||
|
|
eor r11,r11,r12 @ 1 cycle stall
|
||
|
|
eor r10,r6,r7 @ F_xx_xx
|
||
|
|
mov r9,r9,ror#31
|
||
|
|
add r3,r3,r4,ror#27 @ E+=ROR(A,27)
|
||
|
|
eor r9,r9,r11,ror#31
|
||
|
|
str r9,[r14,#-4]!
|
||
|
|
and r10,r5,r10,ror#2 @ F_xx_xx
|
||
|
|
and r11,r6,r7 @ F_xx_xx
|
||
|
|
add r3,r3,r9 @ E+=X[i]
|
||
|
|
add r3,r3,r10 @ E+=F_40_59(B,C,D)
|
||
|
|
add r3,r3,r11,ror#2
|
||
|
|
teq r14,sp
|
||
|
|
bne .L_40_59 @ [+((12+5)*5+2)*4]
|
||
|
|
|
||
|
|
ldr r8,.LK_60_79
|
||
|
|
sub sp,sp,#20*4
|
||
|
|
cmp sp,#0 @ set carry to denote 60_79
|
||
|
|
b .L_20_39_or_60_79 @ [+4], spare 300 bytes
|
||
|
|
.L_done:
|
||
|
|
add sp,sp,#80*4 @ "deallocate" stack frame
|
||
|
|
ldmia r0,{r8,r9,r10,r11,r12}
|
||
|
|
add r3,r8,r3
|
||
|
|
add r4,r9,r4
|
||
|
|
add r5,r10,r5,ror#2
|
||
|
|
add r6,r11,r6,ror#2
|
||
|
|
add r7,r12,r7,ror#2
|
||
|
|
stmia r0,{r3,r4,r5,r6,r7}
|
||
|
|
teq r1,r2
|
||
|
|
bne .Lloop @ [+18], total 1307
|
||
|
|
|
||
|
|
#if __ARM_ARCH__>=5
|
||
|
|
ldmia sp!,{r4-r12,pc}
|
||
|
|
#else
|
||
|
|
ldmia sp!,{r4-r12,lr}
|
||
|
|
tst lr,#1
|
||
|
|
moveq pc,lr @ be binary compatible with V4, yet
|
||
|
|
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||
|
|
#endif
|
||
|
|
.align 2
|
||
|
|
.LK_00_19: .word 0x5a827999
|
||
|
|
.LK_20_39: .word 0x6ed9eba1
|
||
|
|
.LK_40_59: .word 0x8f1bbcdc
|
||
|
|
.LK_60_79: .word 0xca62c1d6
|
||
|
|
.size sha1_block_data_order,.-sha1_block_data_order
|
||
|
|
.asciz "SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
|
||
|
|
.align 2
|