mirror of https://gitee.com/openkylin/linux.git
71 lines
2.4 KiB
C
71 lines
2.4 KiB
C
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/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* Authors: Christian König <christian.koenig@amd.com>
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "cikd.h"
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int vce_v2_0_resume(struct radeon_device *rdev)
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{
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uint64_t addr = rdev->vce.gpu_addr;
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uint32_t size;
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WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
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WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
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WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
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WREG32(VCE_CLOCK_GATING_B, 0xf7);
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WREG32(VCE_LMI_CTRL, 0x00398000);
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WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
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WREG32(VCE_LMI_SWAP_CNTL, 0);
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WREG32(VCE_LMI_SWAP_CNTL1, 0);
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WREG32(VCE_LMI_VM_CTRL, 0);
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size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
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WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = RADEON_VCE_STACK_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = RADEON_VCE_HEAP_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE2, size);
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WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
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WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,
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~VCE_SYS_INT_TRAP_INTERRUPT_EN);
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return 0;
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}
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