mirror of https://gitee.com/openkylin/linux.git
488 lines
11 KiB
C
488 lines
11 KiB
C
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/*
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* s5m-irq.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/mfd/s5m87xx/s5m-core.h>
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struct s5m_irq_data {
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int reg;
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int mask;
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};
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static struct s5m_irq_data s5m8767_irqs[] = {
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[S5M8767_IRQ_PWRR] = {
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.reg = 1,
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.mask = S5M8767_IRQ_PWRR_MASK,
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},
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[S5M8767_IRQ_PWRF] = {
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.reg = 1,
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.mask = S5M8767_IRQ_PWRF_MASK,
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},
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[S5M8767_IRQ_PWR1S] = {
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.reg = 1,
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.mask = S5M8767_IRQ_PWR1S_MASK,
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},
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[S5M8767_IRQ_JIGR] = {
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.reg = 1,
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.mask = S5M8767_IRQ_JIGR_MASK,
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},
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[S5M8767_IRQ_JIGF] = {
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.reg = 1,
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.mask = S5M8767_IRQ_JIGF_MASK,
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},
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[S5M8767_IRQ_LOWBAT2] = {
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.reg = 1,
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.mask = S5M8767_IRQ_LOWBAT2_MASK,
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},
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[S5M8767_IRQ_LOWBAT1] = {
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.reg = 1,
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.mask = S5M8767_IRQ_LOWBAT1_MASK,
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},
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[S5M8767_IRQ_MRB] = {
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.reg = 2,
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.mask = S5M8767_IRQ_MRB_MASK,
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},
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[S5M8767_IRQ_DVSOK2] = {
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.reg = 2,
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.mask = S5M8767_IRQ_DVSOK2_MASK,
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},
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[S5M8767_IRQ_DVSOK3] = {
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.reg = 2,
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.mask = S5M8767_IRQ_DVSOK3_MASK,
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},
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[S5M8767_IRQ_DVSOK4] = {
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.reg = 2,
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.mask = S5M8767_IRQ_DVSOK4_MASK,
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},
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[S5M8767_IRQ_RTC60S] = {
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.reg = 3,
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.mask = S5M8767_IRQ_RTC60S_MASK,
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},
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[S5M8767_IRQ_RTCA1] = {
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.reg = 3,
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.mask = S5M8767_IRQ_RTCA1_MASK,
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},
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[S5M8767_IRQ_RTCA2] = {
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.reg = 3,
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.mask = S5M8767_IRQ_RTCA2_MASK,
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},
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[S5M8767_IRQ_SMPL] = {
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.reg = 3,
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.mask = S5M8767_IRQ_SMPL_MASK,
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},
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[S5M8767_IRQ_RTC1S] = {
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.reg = 3,
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.mask = S5M8767_IRQ_RTC1S_MASK,
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},
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[S5M8767_IRQ_WTSR] = {
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.reg = 3,
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.mask = S5M8767_IRQ_WTSR_MASK,
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},
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};
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static struct s5m_irq_data s5m8763_irqs[] = {
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[S5M8763_IRQ_DCINF] = {
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.reg = 1,
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.mask = S5M8763_IRQ_DCINF_MASK,
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},
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[S5M8763_IRQ_DCINR] = {
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.reg = 1,
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.mask = S5M8763_IRQ_DCINR_MASK,
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},
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[S5M8763_IRQ_JIGF] = {
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.reg = 1,
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.mask = S5M8763_IRQ_JIGF_MASK,
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},
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[S5M8763_IRQ_JIGR] = {
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.reg = 1,
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.mask = S5M8763_IRQ_JIGR_MASK,
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},
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[S5M8763_IRQ_PWRONF] = {
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.reg = 1,
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.mask = S5M8763_IRQ_PWRONF_MASK,
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},
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[S5M8763_IRQ_PWRONR] = {
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.reg = 1,
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.mask = S5M8763_IRQ_PWRONR_MASK,
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},
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[S5M8763_IRQ_WTSREVNT] = {
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.reg = 2,
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.mask = S5M8763_IRQ_WTSREVNT_MASK,
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},
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[S5M8763_IRQ_SMPLEVNT] = {
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.reg = 2,
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.mask = S5M8763_IRQ_SMPLEVNT_MASK,
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},
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[S5M8763_IRQ_ALARM1] = {
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.reg = 2,
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.mask = S5M8763_IRQ_ALARM1_MASK,
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},
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[S5M8763_IRQ_ALARM0] = {
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.reg = 2,
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.mask = S5M8763_IRQ_ALARM0_MASK,
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},
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[S5M8763_IRQ_ONKEY1S] = {
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.reg = 3,
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.mask = S5M8763_IRQ_ONKEY1S_MASK,
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},
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[S5M8763_IRQ_TOPOFFR] = {
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.reg = 3,
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.mask = S5M8763_IRQ_TOPOFFR_MASK,
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},
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[S5M8763_IRQ_DCINOVPR] = {
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.reg = 3,
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.mask = S5M8763_IRQ_DCINOVPR_MASK,
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},
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[S5M8763_IRQ_CHGRSTF] = {
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.reg = 3,
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.mask = S5M8763_IRQ_CHGRSTF_MASK,
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},
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[S5M8763_IRQ_DONER] = {
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.reg = 3,
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.mask = S5M8763_IRQ_DONER_MASK,
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},
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[S5M8763_IRQ_CHGFAULT] = {
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.reg = 3,
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.mask = S5M8763_IRQ_CHGFAULT_MASK,
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},
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[S5M8763_IRQ_LOBAT1] = {
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.reg = 4,
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.mask = S5M8763_IRQ_LOBAT1_MASK,
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},
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[S5M8763_IRQ_LOBAT2] = {
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.reg = 4,
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.mask = S5M8763_IRQ_LOBAT2_MASK,
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},
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};
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static inline struct s5m_irq_data *
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irq_to_s5m8767_irq(struct s5m87xx_dev *s5m87xx, int irq)
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{
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return &s5m8767_irqs[irq - s5m87xx->irq_base];
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}
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static void s5m8767_irq_lock(struct irq_data *data)
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{
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struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
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mutex_lock(&s5m87xx->irqlock);
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}
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static void s5m8767_irq_sync_unlock(struct irq_data *data)
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{
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struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
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int i;
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for (i = 0; i < ARRAY_SIZE(s5m87xx->irq_masks_cur); i++) {
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if (s5m87xx->irq_masks_cur[i] != s5m87xx->irq_masks_cache[i]) {
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s5m87xx->irq_masks_cache[i] = s5m87xx->irq_masks_cur[i];
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s5m_reg_write(s5m87xx, S5M8767_REG_INT1M + i,
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s5m87xx->irq_masks_cur[i]);
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}
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}
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mutex_unlock(&s5m87xx->irqlock);
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}
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static void s5m8767_irq_unmask(struct irq_data *data)
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{
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struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
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struct s5m_irq_data *irq_data = irq_to_s5m8767_irq(s5m87xx,
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data->irq);
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s5m87xx->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
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}
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static void s5m8767_irq_mask(struct irq_data *data)
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{
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struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
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struct s5m_irq_data *irq_data = irq_to_s5m8767_irq(s5m87xx,
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data->irq);
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s5m87xx->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
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}
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static struct irq_chip s5m8767_irq_chip = {
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.name = "s5m8767",
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.irq_bus_lock = s5m8767_irq_lock,
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.irq_bus_sync_unlock = s5m8767_irq_sync_unlock,
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.irq_mask = s5m8767_irq_mask,
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.irq_unmask = s5m8767_irq_unmask,
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};
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static inline struct s5m_irq_data *
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irq_to_s5m8763_irq(struct s5m87xx_dev *s5m87xx, int irq)
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{
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return &s5m8763_irqs[irq - s5m87xx->irq_base];
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}
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static void s5m8763_irq_lock(struct irq_data *data)
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{
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struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
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mutex_lock(&s5m87xx->irqlock);
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}
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static void s5m8763_irq_sync_unlock(struct irq_data *data)
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{
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struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
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int i;
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for (i = 0; i < ARRAY_SIZE(s5m87xx->irq_masks_cur); i++) {
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if (s5m87xx->irq_masks_cur[i] != s5m87xx->irq_masks_cache[i]) {
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s5m87xx->irq_masks_cache[i] = s5m87xx->irq_masks_cur[i];
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s5m_reg_write(s5m87xx, S5M8763_REG_IRQM1 + i,
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s5m87xx->irq_masks_cur[i]);
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}
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}
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mutex_unlock(&s5m87xx->irqlock);
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}
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static void s5m8763_irq_unmask(struct irq_data *data)
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{
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struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
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struct s5m_irq_data *irq_data = irq_to_s5m8763_irq(s5m87xx,
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data->irq);
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s5m87xx->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
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}
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static void s5m8763_irq_mask(struct irq_data *data)
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{
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struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
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struct s5m_irq_data *irq_data = irq_to_s5m8763_irq(s5m87xx,
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data->irq);
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s5m87xx->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
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}
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static struct irq_chip s5m8763_irq_chip = {
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.name = "s5m8763",
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.irq_bus_lock = s5m8763_irq_lock,
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.irq_bus_sync_unlock = s5m8763_irq_sync_unlock,
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.irq_mask = s5m8763_irq_mask,
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.irq_unmask = s5m8763_irq_unmask,
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};
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static irqreturn_t s5m8767_irq_thread(int irq, void *data)
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{
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struct s5m87xx_dev *s5m87xx = data;
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u8 irq_reg[NUM_IRQ_REGS-1];
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int ret;
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int i;
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ret = s5m_bulk_read(s5m87xx, S5M8767_REG_INT1,
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NUM_IRQ_REGS - 1, irq_reg);
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if (ret < 0) {
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dev_err(s5m87xx->dev, "Failed to read interrupt register: %d\n",
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ret);
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return IRQ_NONE;
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}
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for (i = 0; i < NUM_IRQ_REGS - 1; i++)
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irq_reg[i] &= ~s5m87xx->irq_masks_cur[i];
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for (i = 0; i < S5M8767_IRQ_NR; i++) {
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if (irq_reg[s5m8767_irqs[i].reg - 1] & s5m8767_irqs[i].mask)
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handle_nested_irq(s5m87xx->irq_base + i);
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t s5m8763_irq_thread(int irq, void *data)
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{
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struct s5m87xx_dev *s5m87xx = data;
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u8 irq_reg[NUM_IRQ_REGS];
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int ret;
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int i;
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ret = s5m_bulk_read(s5m87xx, S5M8763_REG_IRQ1,
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NUM_IRQ_REGS, irq_reg);
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if (ret < 0) {
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dev_err(s5m87xx->dev, "Failed to read interrupt register: %d\n",
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ret);
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return IRQ_NONE;
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}
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for (i = 0; i < NUM_IRQ_REGS; i++)
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irq_reg[i] &= ~s5m87xx->irq_masks_cur[i];
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for (i = 0; i < S5M8763_IRQ_NR; i++) {
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if (irq_reg[s5m8763_irqs[i].reg - 1] & s5m8763_irqs[i].mask)
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handle_nested_irq(s5m87xx->irq_base + i);
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}
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return IRQ_HANDLED;
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}
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int s5m_irq_resume(struct s5m87xx_dev *s5m87xx)
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{
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if (s5m87xx->irq && s5m87xx->irq_base){
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switch (s5m87xx->device_type) {
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case S5M8763X:
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||
|
|
s5m8763_irq_thread(s5m87xx->irq_base, s5m87xx);
|
||
|
|
break;
|
||
|
|
case S5M8767X:
|
||
|
|
s5m8767_irq_thread(s5m87xx->irq_base, s5m87xx);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int s5m_irq_init(struct s5m87xx_dev *s5m87xx)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
int cur_irq;
|
||
|
|
int ret = 0;
|
||
|
|
int type = s5m87xx->device_type;
|
||
|
|
|
||
|
|
if (!s5m87xx->irq) {
|
||
|
|
dev_warn(s5m87xx->dev,
|
||
|
|
"No interrupt specified, no interrupts\n");
|
||
|
|
s5m87xx->irq_base = 0;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!s5m87xx->irq_base) {
|
||
|
|
dev_err(s5m87xx->dev,
|
||
|
|
"No interrupt base specified, no interrupts\n");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
mutex_init(&s5m87xx->irqlock);
|
||
|
|
|
||
|
|
switch (type) {
|
||
|
|
case S5M8763X:
|
||
|
|
for (i = 0; i < NUM_IRQ_REGS; i++) {
|
||
|
|
s5m87xx->irq_masks_cur[i] = 0xff;
|
||
|
|
s5m87xx->irq_masks_cache[i] = 0xff;
|
||
|
|
s5m_reg_write(s5m87xx, S5M8763_REG_IRQM1 + i,
|
||
|
|
0xff);
|
||
|
|
}
|
||
|
|
|
||
|
|
s5m_reg_write(s5m87xx, S5M8763_REG_STATUSM1, 0xff);
|
||
|
|
s5m_reg_write(s5m87xx, S5M8763_REG_STATUSM2, 0xff);
|
||
|
|
|
||
|
|
for (i = 0; i < S5M8763_IRQ_NR; i++) {
|
||
|
|
cur_irq = i + s5m87xx->irq_base;
|
||
|
|
irq_set_chip_data(cur_irq, s5m87xx);
|
||
|
|
irq_set_chip_and_handler(cur_irq, &s5m8763_irq_chip,
|
||
|
|
handle_edge_irq);
|
||
|
|
irq_set_nested_thread(cur_irq, 1);
|
||
|
|
#ifdef CONFIG_ARM
|
||
|
|
set_irq_flags(cur_irq, IRQF_VALID);
|
||
|
|
#else
|
||
|
|
irq_set_noprobe(cur_irq);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = request_threaded_irq(s5m87xx->irq, NULL,
|
||
|
|
s5m8763_irq_thread,
|
||
|
|
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
|
||
|
|
"s5m87xx-irq", s5m87xx);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(s5m87xx->dev, "Failed to request IRQ %d: %d\n",
|
||
|
|
s5m87xx->irq, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case S5M8767X:
|
||
|
|
for (i = 0; i < NUM_IRQ_REGS - 1; i++) {
|
||
|
|
s5m87xx->irq_masks_cur[i] = 0xff;
|
||
|
|
s5m87xx->irq_masks_cache[i] = 0xff;
|
||
|
|
s5m_reg_write(s5m87xx, S5M8767_REG_INT1M + i,
|
||
|
|
0xff);
|
||
|
|
}
|
||
|
|
for (i = 0; i < S5M8767_IRQ_NR; i++) {
|
||
|
|
cur_irq = i + s5m87xx->irq_base;
|
||
|
|
irq_set_chip_data(cur_irq, s5m87xx);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(s5m87xx->dev,
|
||
|
|
"Failed to irq_set_chip_data %d: %d\n",
|
||
|
|
s5m87xx->irq, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
irq_set_chip_and_handler(cur_irq, &s5m8767_irq_chip,
|
||
|
|
handle_edge_irq);
|
||
|
|
irq_set_nested_thread(cur_irq, 1);
|
||
|
|
#ifdef CONFIG_ARM
|
||
|
|
set_irq_flags(cur_irq, IRQF_VALID);
|
||
|
|
#else
|
||
|
|
irq_set_noprobe(cur_irq);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = request_threaded_irq(s5m87xx->irq, NULL,
|
||
|
|
s5m8767_irq_thread,
|
||
|
|
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
|
||
|
|
"s5m87xx-irq", s5m87xx);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(s5m87xx->dev, "Failed to request IRQ %d: %d\n",
|
||
|
|
s5m87xx->irq, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!s5m87xx->ono)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
switch (type) {
|
||
|
|
case S5M8763X:
|
||
|
|
ret = request_threaded_irq(s5m87xx->ono, NULL,
|
||
|
|
s5m8763_irq_thread,
|
||
|
|
IRQF_TRIGGER_FALLING |
|
||
|
|
IRQF_TRIGGER_RISING |
|
||
|
|
IRQF_ONESHOT, "s5m87xx-ono",
|
||
|
|
s5m87xx);
|
||
|
|
break;
|
||
|
|
case S5M8767X:
|
||
|
|
ret = request_threaded_irq(s5m87xx->ono, NULL,
|
||
|
|
s5m8767_irq_thread,
|
||
|
|
IRQF_TRIGGER_FALLING |
|
||
|
|
IRQF_TRIGGER_RISING |
|
||
|
|
IRQF_ONESHOT, "s5m87xx-ono", s5m87xx);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
dev_err(s5m87xx->dev, "Failed to request IRQ %d: %d\n",
|
||
|
|
s5m87xx->ono, ret);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void s5m_irq_exit(struct s5m87xx_dev *s5m87xx)
|
||
|
|
{
|
||
|
|
if (s5m87xx->ono)
|
||
|
|
free_irq(s5m87xx->ono, s5m87xx);
|
||
|
|
|
||
|
|
if (s5m87xx->irq)
|
||
|
|
free_irq(s5m87xx->irq, s5m87xx);
|
||
|
|
}
|