2012-06-01 07:26:39 +08:00
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/*
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* DMA Engine support for Tsi721 PCIExpress-to-SRIO bridge
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*
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* Copyright 2011 Integrated Device Technology, Inc.
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* Alexandre Bounine <alexandre.bounine@idt.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/rio.h>
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#include <linux/rio_drv.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/kfifo.h>
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#include <linux/delay.h>
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#include "tsi721.h"
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static inline struct tsi721_bdma_chan *to_tsi721_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct tsi721_bdma_chan, dchan);
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}
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static inline struct tsi721_device *to_tsi721(struct dma_device *ddev)
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{
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return container_of(ddev, struct rio_mport, dma)->priv;
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}
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static inline
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struct tsi721_tx_desc *to_tsi721_desc(struct dma_async_tx_descriptor *txd)
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{
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return container_of(txd, struct tsi721_tx_desc, txd);
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}
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static inline
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struct tsi721_tx_desc *tsi721_dma_first_active(
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struct tsi721_bdma_chan *bdma_chan)
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{
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return list_first_entry(&bdma_chan->active_list,
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struct tsi721_tx_desc, desc_node);
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}
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static int tsi721_bdma_ch_init(struct tsi721_bdma_chan *bdma_chan)
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{
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struct tsi721_dma_desc *bd_ptr;
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struct device *dev = bdma_chan->dchan.device->dev;
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u64 *sts_ptr;
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dma_addr_t bd_phys;
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dma_addr_t sts_phys;
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int sts_size;
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int bd_num = bdma_chan->bd_num;
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dev_dbg(dev, "Init Block DMA Engine, CH%d\n", bdma_chan->id);
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/* Allocate space for DMA descriptors */
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bd_ptr = dma_zalloc_coherent(dev,
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bd_num * sizeof(struct tsi721_dma_desc),
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&bd_phys, GFP_KERNEL);
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if (!bd_ptr)
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return -ENOMEM;
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bdma_chan->bd_phys = bd_phys;
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bdma_chan->bd_base = bd_ptr;
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dev_dbg(dev, "DMA descriptors @ %p (phys = %llx)\n",
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bd_ptr, (unsigned long long)bd_phys);
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/* Allocate space for descriptor status FIFO */
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sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ?
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bd_num : TSI721_DMA_MINSTSSZ;
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sts_size = roundup_pow_of_two(sts_size);
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sts_ptr = dma_zalloc_coherent(dev,
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sts_size * sizeof(struct tsi721_dma_sts),
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&sts_phys, GFP_KERNEL);
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if (!sts_ptr) {
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/* Free space allocated for DMA descriptors */
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dma_free_coherent(dev,
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bd_num * sizeof(struct tsi721_dma_desc),
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bd_ptr, bd_phys);
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bdma_chan->bd_base = NULL;
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return -ENOMEM;
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}
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bdma_chan->sts_phys = sts_phys;
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bdma_chan->sts_base = sts_ptr;
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bdma_chan->sts_size = sts_size;
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dev_dbg(dev,
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"desc status FIFO @ %p (phys = %llx) size=0x%x\n",
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sts_ptr, (unsigned long long)sts_phys, sts_size);
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/* Initialize DMA descriptors ring */
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bd_ptr[bd_num - 1].type_id = cpu_to_le32(DTYPE3 << 29);
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bd_ptr[bd_num - 1].next_lo = cpu_to_le32((u64)bd_phys &
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TSI721_DMAC_DPTRL_MASK);
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bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32);
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/* Setup DMA descriptor pointers */
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iowrite32(((u64)bd_phys >> 32),
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bdma_chan->regs + TSI721_DMAC_DPTRH);
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iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
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bdma_chan->regs + TSI721_DMAC_DPTRL);
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/* Setup descriptor status FIFO */
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iowrite32(((u64)sts_phys >> 32),
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bdma_chan->regs + TSI721_DMAC_DSBH);
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iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
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bdma_chan->regs + TSI721_DMAC_DSBL);
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iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
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bdma_chan->regs + TSI721_DMAC_DSSZ);
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/* Clear interrupt bits */
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iowrite32(TSI721_DMAC_INT_ALL,
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bdma_chan->regs + TSI721_DMAC_INT);
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ioread32(bdma_chan->regs + TSI721_DMAC_INT);
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/* Toggle DMA channel initialization */
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iowrite32(TSI721_DMAC_CTL_INIT, bdma_chan->regs + TSI721_DMAC_CTL);
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ioread32(bdma_chan->regs + TSI721_DMAC_CTL);
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bdma_chan->wr_count = bdma_chan->wr_count_next = 0;
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bdma_chan->sts_rdptr = 0;
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udelay(10);
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return 0;
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}
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static int tsi721_bdma_ch_free(struct tsi721_bdma_chan *bdma_chan)
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{
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u32 ch_stat;
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if (bdma_chan->bd_base == NULL)
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return 0;
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/* Check if DMA channel still running */
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ch_stat = ioread32(bdma_chan->regs + TSI721_DMAC_STS);
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if (ch_stat & TSI721_DMAC_STS_RUN)
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return -EFAULT;
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/* Put DMA channel into init state */
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iowrite32(TSI721_DMAC_CTL_INIT, bdma_chan->regs + TSI721_DMAC_CTL);
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/* Free space allocated for DMA descriptors */
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dma_free_coherent(bdma_chan->dchan.device->dev,
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bdma_chan->bd_num * sizeof(struct tsi721_dma_desc),
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bdma_chan->bd_base, bdma_chan->bd_phys);
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bdma_chan->bd_base = NULL;
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/* Free space allocated for status FIFO */
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dma_free_coherent(bdma_chan->dchan.device->dev,
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bdma_chan->sts_size * sizeof(struct tsi721_dma_sts),
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bdma_chan->sts_base, bdma_chan->sts_phys);
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bdma_chan->sts_base = NULL;
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return 0;
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}
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static void
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tsi721_bdma_interrupt_enable(struct tsi721_bdma_chan *bdma_chan, int enable)
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{
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if (enable) {
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/* Clear pending BDMA channel interrupts */
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iowrite32(TSI721_DMAC_INT_ALL,
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bdma_chan->regs + TSI721_DMAC_INT);
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ioread32(bdma_chan->regs + TSI721_DMAC_INT);
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/* Enable BDMA channel interrupts */
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iowrite32(TSI721_DMAC_INT_ALL,
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bdma_chan->regs + TSI721_DMAC_INTE);
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} else {
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/* Disable BDMA channel interrupts */
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iowrite32(0, bdma_chan->regs + TSI721_DMAC_INTE);
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/* Clear pending BDMA channel interrupts */
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iowrite32(TSI721_DMAC_INT_ALL,
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bdma_chan->regs + TSI721_DMAC_INT);
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}
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}
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static bool tsi721_dma_is_idle(struct tsi721_bdma_chan *bdma_chan)
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{
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u32 sts;
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sts = ioread32(bdma_chan->regs + TSI721_DMAC_STS);
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return ((sts & TSI721_DMAC_STS_RUN) == 0);
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}
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void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan)
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{
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/* Disable BDMA channel interrupts */
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iowrite32(0, bdma_chan->regs + TSI721_DMAC_INTE);
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tasklet_schedule(&bdma_chan->tasklet);
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}
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#ifdef CONFIG_PCI_MSI
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/**
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* tsi721_omsg_msix - MSI-X interrupt handler for BDMA channels
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* @irq: Linux interrupt number
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* @ptr: Pointer to interrupt-specific data (BDMA channel structure)
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*
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* Handles BDMA channel interrupts signaled using MSI-X.
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*/
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static irqreturn_t tsi721_bdma_msix(int irq, void *ptr)
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{
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struct tsi721_bdma_chan *bdma_chan = ptr;
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tsi721_bdma_handler(bdma_chan);
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return IRQ_HANDLED;
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}
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#endif /* CONFIG_PCI_MSI */
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/* Must be called with the spinlock held */
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static void tsi721_start_dma(struct tsi721_bdma_chan *bdma_chan)
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{
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if (!tsi721_dma_is_idle(bdma_chan)) {
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dev_err(bdma_chan->dchan.device->dev,
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"BUG: Attempt to start non-idle channel\n");
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return;
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}
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if (bdma_chan->wr_count == bdma_chan->wr_count_next) {
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dev_err(bdma_chan->dchan.device->dev,
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"BUG: Attempt to start DMA with no BDs ready\n");
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return;
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}
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dev_dbg(bdma_chan->dchan.device->dev,
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"tx_chan: %p, chan: %d, regs: %p\n",
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bdma_chan, bdma_chan->dchan.chan_id, bdma_chan->regs);
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iowrite32(bdma_chan->wr_count_next,
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bdma_chan->regs + TSI721_DMAC_DWRCNT);
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ioread32(bdma_chan->regs + TSI721_DMAC_DWRCNT);
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bdma_chan->wr_count = bdma_chan->wr_count_next;
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}
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static void tsi721_desc_put(struct tsi721_bdma_chan *bdma_chan,
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struct tsi721_tx_desc *desc)
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{
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dev_dbg(bdma_chan->dchan.device->dev,
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"Put desc: %p into free list\n", desc);
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if (desc) {
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spin_lock_bh(&bdma_chan->lock);
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list_splice_init(&desc->tx_list, &bdma_chan->free_list);
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list_add(&desc->desc_node, &bdma_chan->free_list);
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bdma_chan->wr_count_next = bdma_chan->wr_count;
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spin_unlock_bh(&bdma_chan->lock);
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}
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}
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static
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struct tsi721_tx_desc *tsi721_desc_get(struct tsi721_bdma_chan *bdma_chan)
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{
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struct tsi721_tx_desc *tx_desc, *_tx_desc;
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struct tsi721_tx_desc *ret = NULL;
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int i;
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spin_lock_bh(&bdma_chan->lock);
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list_for_each_entry_safe(tx_desc, _tx_desc,
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&bdma_chan->free_list, desc_node) {
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if (async_tx_test_ack(&tx_desc->txd)) {
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list_del(&tx_desc->desc_node);
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ret = tx_desc;
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break;
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}
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dev_dbg(bdma_chan->dchan.device->dev,
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"desc %p not ACKed\n", tx_desc);
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}
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i = bdma_chan->wr_count_next % bdma_chan->bd_num;
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if (i == bdma_chan->bd_num - 1) {
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i = 0;
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bdma_chan->wr_count_next++; /* skip link descriptor */
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}
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bdma_chan->wr_count_next++;
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tx_desc->txd.phys = bdma_chan->bd_phys +
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i * sizeof(struct tsi721_dma_desc);
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tx_desc->hw_desc = &((struct tsi721_dma_desc *)bdma_chan->bd_base)[i];
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spin_unlock_bh(&bdma_chan->lock);
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return ret;
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}
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static int
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tsi721_fill_desc(struct tsi721_bdma_chan *bdma_chan,
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struct tsi721_tx_desc *desc, struct scatterlist *sg,
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enum dma_rtype rtype, u32 sys_size)
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{
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struct tsi721_dma_desc *bd_ptr = desc->hw_desc;
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u64 rio_addr;
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if (sg_dma_len(sg) > TSI721_DMAD_BCOUNT1 + 1) {
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dev_err(bdma_chan->dchan.device->dev,
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"SG element is too large\n");
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return -EINVAL;
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}
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dev_dbg(bdma_chan->dchan.device->dev,
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"desc: 0x%llx, addr: 0x%llx len: 0x%x\n",
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(u64)desc->txd.phys, (unsigned long long)sg_dma_address(sg),
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sg_dma_len(sg));
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dev_dbg(bdma_chan->dchan.device->dev,
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"bd_ptr = %p did=%d raddr=0x%llx\n",
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bd_ptr, desc->destid, desc->rio_addr);
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/* Initialize DMA descriptor */
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bd_ptr->type_id = cpu_to_le32((DTYPE1 << 29) |
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(rtype << 19) | desc->destid);
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if (desc->interrupt)
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bd_ptr->type_id |= cpu_to_le32(TSI721_DMAD_IOF);
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bd_ptr->bcount = cpu_to_le32(((desc->rio_addr & 0x3) << 30) |
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(sys_size << 26) | sg_dma_len(sg));
|
|
|
|
rio_addr = (desc->rio_addr >> 2) |
|
|
|
|
((u64)(desc->rio_addr_u & 0x3) << 62);
|
|
|
|
bd_ptr->raddr_lo = cpu_to_le32(rio_addr & 0xffffffff);
|
|
|
|
bd_ptr->raddr_hi = cpu_to_le32(rio_addr >> 32);
|
|
|
|
bd_ptr->t1.bufptr_lo = cpu_to_le32(
|
|
|
|
(u64)sg_dma_address(sg) & 0xffffffff);
|
|
|
|
bd_ptr->t1.bufptr_hi = cpu_to_le32((u64)sg_dma_address(sg) >> 32);
|
|
|
|
bd_ptr->t1.s_dist = 0;
|
|
|
|
bd_ptr->t1.s_size = 0;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tsi721_dma_chain_complete(struct tsi721_bdma_chan *bdma_chan,
|
|
|
|
struct tsi721_tx_desc *desc)
|
|
|
|
{
|
|
|
|
struct dma_async_tx_descriptor *txd = &desc->txd;
|
|
|
|
dma_async_tx_callback callback = txd->callback;
|
|
|
|
void *param = txd->callback_param;
|
|
|
|
|
|
|
|
list_splice_init(&desc->tx_list, &bdma_chan->free_list);
|
|
|
|
list_move(&desc->desc_node, &bdma_chan->free_list);
|
|
|
|
bdma_chan->completed_cookie = txd->cookie;
|
|
|
|
|
|
|
|
if (callback)
|
|
|
|
callback(param);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tsi721_dma_complete_all(struct tsi721_bdma_chan *bdma_chan)
|
|
|
|
{
|
|
|
|
struct tsi721_tx_desc *desc, *_d;
|
|
|
|
LIST_HEAD(list);
|
|
|
|
|
|
|
|
BUG_ON(!tsi721_dma_is_idle(bdma_chan));
|
|
|
|
|
|
|
|
if (!list_empty(&bdma_chan->queue))
|
|
|
|
tsi721_start_dma(bdma_chan);
|
|
|
|
|
|
|
|
list_splice_init(&bdma_chan->active_list, &list);
|
|
|
|
list_splice_init(&bdma_chan->queue, &bdma_chan->active_list);
|
|
|
|
|
|
|
|
list_for_each_entry_safe(desc, _d, &list, desc_node)
|
|
|
|
tsi721_dma_chain_complete(bdma_chan, desc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tsi721_clr_stat(struct tsi721_bdma_chan *bdma_chan)
|
|
|
|
{
|
|
|
|
u32 srd_ptr;
|
|
|
|
u64 *sts_ptr;
|
|
|
|
int i, j;
|
|
|
|
|
|
|
|
/* Check and clear descriptor status FIFO entries */
|
|
|
|
srd_ptr = bdma_chan->sts_rdptr;
|
|
|
|
sts_ptr = bdma_chan->sts_base;
|
|
|
|
j = srd_ptr * 8;
|
|
|
|
while (sts_ptr[j]) {
|
|
|
|
for (i = 0; i < 8 && sts_ptr[j]; i++, j++)
|
|
|
|
sts_ptr[j] = 0;
|
|
|
|
|
|
|
|
++srd_ptr;
|
|
|
|
srd_ptr %= bdma_chan->sts_size;
|
|
|
|
j = srd_ptr * 8;
|
|
|
|
}
|
|
|
|
|
|
|
|
iowrite32(srd_ptr, bdma_chan->regs + TSI721_DMAC_DSRP);
|
|
|
|
bdma_chan->sts_rdptr = srd_ptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tsi721_advance_work(struct tsi721_bdma_chan *bdma_chan)
|
|
|
|
{
|
|
|
|
if (list_empty(&bdma_chan->active_list) ||
|
|
|
|
list_is_singular(&bdma_chan->active_list)) {
|
|
|
|
dev_dbg(bdma_chan->dchan.device->dev,
|
|
|
|
"%s: Active_list empty\n", __func__);
|
|
|
|
tsi721_dma_complete_all(bdma_chan);
|
|
|
|
} else {
|
|
|
|
dev_dbg(bdma_chan->dchan.device->dev,
|
|
|
|
"%s: Active_list NOT empty\n", __func__);
|
|
|
|
tsi721_dma_chain_complete(bdma_chan,
|
|
|
|
tsi721_dma_first_active(bdma_chan));
|
|
|
|
tsi721_start_dma(bdma_chan);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tsi721_dma_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct tsi721_bdma_chan *bdma_chan = (struct tsi721_bdma_chan *)data;
|
|
|
|
u32 dmac_int, dmac_sts;
|
|
|
|
|
|
|
|
dmac_int = ioread32(bdma_chan->regs + TSI721_DMAC_INT);
|
|
|
|
dev_dbg(bdma_chan->dchan.device->dev, "%s: DMAC%d_INT = 0x%x\n",
|
|
|
|
__func__, bdma_chan->id, dmac_int);
|
|
|
|
/* Clear channel interrupts */
|
|
|
|
iowrite32(dmac_int, bdma_chan->regs + TSI721_DMAC_INT);
|
|
|
|
|
|
|
|
if (dmac_int & TSI721_DMAC_INT_ERR) {
|
|
|
|
dmac_sts = ioread32(bdma_chan->regs + TSI721_DMAC_STS);
|
|
|
|
dev_err(bdma_chan->dchan.device->dev,
|
|
|
|
"%s: DMA ERROR - DMAC%d_STS = 0x%x\n",
|
|
|
|
__func__, bdma_chan->id, dmac_sts);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dmac_int & TSI721_DMAC_INT_STFULL) {
|
|
|
|
dev_err(bdma_chan->dchan.device->dev,
|
|
|
|
"%s: DMAC%d descriptor status FIFO is full\n",
|
|
|
|
__func__, bdma_chan->id);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dmac_int & (TSI721_DMAC_INT_DONE | TSI721_DMAC_INT_IOFDONE)) {
|
|
|
|
tsi721_clr_stat(bdma_chan);
|
|
|
|
spin_lock(&bdma_chan->lock);
|
|
|
|
tsi721_advance_work(bdma_chan);
|
|
|
|
spin_unlock(&bdma_chan->lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Re-Enable BDMA channel interrupts */
|
|
|
|
iowrite32(TSI721_DMAC_INT_ALL, bdma_chan->regs + TSI721_DMAC_INTE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static dma_cookie_t tsi721_tx_submit(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
struct tsi721_tx_desc *desc = to_tsi721_desc(txd);
|
|
|
|
struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(txd->chan);
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
|
|
|
|
spin_lock_bh(&bdma_chan->lock);
|
|
|
|
|
|
|
|
cookie = txd->chan->cookie;
|
|
|
|
if (++cookie < 0)
|
|
|
|
cookie = 1;
|
|
|
|
txd->chan->cookie = cookie;
|
|
|
|
txd->cookie = cookie;
|
|
|
|
|
|
|
|
if (list_empty(&bdma_chan->active_list)) {
|
|
|
|
list_add_tail(&desc->desc_node, &bdma_chan->active_list);
|
|
|
|
tsi721_start_dma(bdma_chan);
|
|
|
|
} else {
|
|
|
|
list_add_tail(&desc->desc_node, &bdma_chan->queue);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_bh(&bdma_chan->lock);
|
|
|
|
return cookie;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tsi721_alloc_chan_resources(struct dma_chan *dchan)
|
|
|
|
{
|
|
|
|
struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
struct tsi721_device *priv = to_tsi721(dchan->device);
|
|
|
|
#endif
|
|
|
|
struct tsi721_tx_desc *desc = NULL;
|
|
|
|
LIST_HEAD(tmp_list);
|
|
|
|
int i;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (bdma_chan->bd_base)
|
|
|
|
return bdma_chan->bd_num - 1;
|
|
|
|
|
|
|
|
/* Initialize BDMA channel */
|
|
|
|
if (tsi721_bdma_ch_init(bdma_chan)) {
|
|
|
|
dev_err(dchan->device->dev, "Unable to initialize data DMA"
|
|
|
|
" channel %d, aborting\n", bdma_chan->id);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Alocate matching number of logical descriptors */
|
|
|
|
desc = kcalloc((bdma_chan->bd_num - 1), sizeof(struct tsi721_tx_desc),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!desc) {
|
|
|
|
dev_err(dchan->device->dev,
|
|
|
|
"Failed to allocate logical descriptors\n");
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
bdma_chan->tx_desc = desc;
|
|
|
|
|
|
|
|
for (i = 0; i < bdma_chan->bd_num - 1; i++) {
|
|
|
|
dma_async_tx_descriptor_init(&desc[i].txd, dchan);
|
|
|
|
desc[i].txd.tx_submit = tsi721_tx_submit;
|
|
|
|
desc[i].txd.flags = DMA_CTRL_ACK;
|
|
|
|
INIT_LIST_HEAD(&desc[i].tx_list);
|
|
|
|
list_add_tail(&desc[i].desc_node, &tmp_list);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_bh(&bdma_chan->lock);
|
|
|
|
list_splice(&tmp_list, &bdma_chan->free_list);
|
|
|
|
bdma_chan->completed_cookie = dchan->cookie = 1;
|
|
|
|
spin_unlock_bh(&bdma_chan->lock);
|
|
|
|
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
if (priv->flags & TSI721_USING_MSIX) {
|
|
|
|
/* Request interrupt service if we are in MSI-X mode */
|
|
|
|
rc = request_irq(
|
|
|
|
priv->msix[TSI721_VECT_DMA0_DONE +
|
|
|
|
bdma_chan->id].vector,
|
|
|
|
tsi721_bdma_msix, 0,
|
|
|
|
priv->msix[TSI721_VECT_DMA0_DONE +
|
|
|
|
bdma_chan->id].irq_name,
|
|
|
|
(void *)bdma_chan);
|
|
|
|
|
|
|
|
if (rc) {
|
|
|
|
dev_dbg(dchan->device->dev,
|
|
|
|
"Unable to allocate MSI-X interrupt for "
|
|
|
|
"BDMA%d-DONE\n", bdma_chan->id);
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = request_irq(priv->msix[TSI721_VECT_DMA0_INT +
|
|
|
|
bdma_chan->id].vector,
|
|
|
|
tsi721_bdma_msix, 0,
|
|
|
|
priv->msix[TSI721_VECT_DMA0_INT +
|
|
|
|
bdma_chan->id].irq_name,
|
|
|
|
(void *)bdma_chan);
|
|
|
|
|
|
|
|
if (rc) {
|
|
|
|
dev_dbg(dchan->device->dev,
|
|
|
|
"Unable to allocate MSI-X interrupt for "
|
|
|
|
"BDMA%d-INT\n", bdma_chan->id);
|
|
|
|
free_irq(
|
|
|
|
priv->msix[TSI721_VECT_DMA0_DONE +
|
|
|
|
bdma_chan->id].vector,
|
|
|
|
(void *)bdma_chan);
|
|
|
|
rc = -EIO;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PCI_MSI */
|
|
|
|
|
|
|
|
tasklet_enable(&bdma_chan->tasklet);
|
|
|
|
tsi721_bdma_interrupt_enable(bdma_chan, 1);
|
|
|
|
|
|
|
|
return bdma_chan->bd_num - 1;
|
|
|
|
|
|
|
|
err_out:
|
|
|
|
kfree(desc);
|
|
|
|
tsi721_bdma_ch_free(bdma_chan);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tsi721_free_chan_resources(struct dma_chan *dchan)
|
|
|
|
{
|
|
|
|
struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
struct tsi721_device *priv = to_tsi721(dchan->device);
|
|
|
|
#endif
|
|
|
|
LIST_HEAD(list);
|
|
|
|
|
|
|
|
dev_dbg(dchan->device->dev, "%s: Entry\n", __func__);
|
|
|
|
|
|
|
|
if (bdma_chan->bd_base == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
BUG_ON(!list_empty(&bdma_chan->active_list));
|
|
|
|
BUG_ON(!list_empty(&bdma_chan->queue));
|
|
|
|
|
|
|
|
tasklet_disable(&bdma_chan->tasklet);
|
|
|
|
|
|
|
|
spin_lock_bh(&bdma_chan->lock);
|
|
|
|
list_splice_init(&bdma_chan->free_list, &list);
|
|
|
|
spin_unlock_bh(&bdma_chan->lock);
|
|
|
|
|
|
|
|
tsi721_bdma_interrupt_enable(bdma_chan, 0);
|
|
|
|
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
if (priv->flags & TSI721_USING_MSIX) {
|
|
|
|
free_irq(priv->msix[TSI721_VECT_DMA0_DONE +
|
|
|
|
bdma_chan->id].vector, (void *)bdma_chan);
|
|
|
|
free_irq(priv->msix[TSI721_VECT_DMA0_INT +
|
|
|
|
bdma_chan->id].vector, (void *)bdma_chan);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PCI_MSI */
|
|
|
|
|
|
|
|
tsi721_bdma_ch_free(bdma_chan);
|
|
|
|
kfree(bdma_chan->tx_desc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
enum dma_status tsi721_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
|
|
|
|
struct dma_tx_state *txstate)
|
|
|
|
{
|
|
|
|
struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
|
|
|
|
dma_cookie_t last_used;
|
|
|
|
dma_cookie_t last_completed;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
spin_lock_bh(&bdma_chan->lock);
|
|
|
|
last_completed = bdma_chan->completed_cookie;
|
|
|
|
last_used = dchan->cookie;
|
|
|
|
spin_unlock_bh(&bdma_chan->lock);
|
|
|
|
|
|
|
|
ret = dma_async_is_complete(cookie, last_completed, last_used);
|
|
|
|
|
|
|
|
dma_set_tx_state(txstate, last_completed, last_used, 0);
|
|
|
|
|
|
|
|
dev_dbg(dchan->device->dev,
|
|
|
|
"%s: exit, ret: %d, last_completed: %d, last_used: %d\n",
|
|
|
|
__func__, ret, last_completed, last_used);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tsi721_issue_pending(struct dma_chan *dchan)
|
|
|
|
{
|
|
|
|
struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
|
|
|
|
|
|
|
|
dev_dbg(dchan->device->dev, "%s: Entry\n", __func__);
|
|
|
|
|
|
|
|
if (tsi721_dma_is_idle(bdma_chan)) {
|
|
|
|
spin_lock_bh(&bdma_chan->lock);
|
|
|
|
tsi721_advance_work(bdma_chan);
|
|
|
|
spin_unlock_bh(&bdma_chan->lock);
|
|
|
|
} else
|
|
|
|
dev_dbg(dchan->device->dev,
|
|
|
|
"%s: DMA channel still busy\n", __func__);
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
struct dma_async_tx_descriptor *tsi721_prep_rio_sg(struct dma_chan *dchan,
|
|
|
|
struct scatterlist *sgl, unsigned int sg_len,
|
|
|
|
enum dma_transfer_direction dir, unsigned long flags,
|
|
|
|
void *tinfo)
|
|
|
|
{
|
|
|
|
struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
|
|
|
|
struct tsi721_tx_desc *desc = NULL;
|
|
|
|
struct tsi721_tx_desc *first = NULL;
|
|
|
|
struct scatterlist *sg;
|
|
|
|
struct rio_dma_ext *rext = tinfo;
|
|
|
|
u64 rio_addr = rext->rio_addr; /* limited to 64-bit rio_addr for now */
|
|
|
|
unsigned int i;
|
|
|
|
u32 sys_size = dma_to_mport(dchan->device)->sys_size;
|
|
|
|
enum dma_rtype rtype;
|
|
|
|
|
|
|
|
if (!sgl || !sg_len) {
|
|
|
|
dev_err(dchan->device->dev, "%s: No SG list\n", __func__);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dir == DMA_DEV_TO_MEM)
|
|
|
|
rtype = NREAD;
|
|
|
|
else if (dir == DMA_MEM_TO_DEV) {
|
|
|
|
switch (rext->wr_type) {
|
|
|
|
case RDW_ALL_NWRITE:
|
|
|
|
rtype = ALL_NWRITE;
|
|
|
|
break;
|
|
|
|
case RDW_ALL_NWRITE_R:
|
|
|
|
rtype = ALL_NWRITE_R;
|
|
|
|
break;
|
|
|
|
case RDW_LAST_NWRITE_R:
|
|
|
|
default:
|
|
|
|
rtype = LAST_NWRITE_R;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
dev_err(dchan->device->dev,
|
|
|
|
"%s: Unsupported DMA direction option\n", __func__);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
|
|
int err;
|
|
|
|
|
|
|
|
dev_dbg(dchan->device->dev, "%s: sg #%d\n", __func__, i);
|
|
|
|
desc = tsi721_desc_get(bdma_chan);
|
|
|
|
if (!desc) {
|
|
|
|
dev_err(dchan->device->dev,
|
|
|
|
"Not enough descriptors available\n");
|
|
|
|
goto err_desc_get;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sg_is_last(sg))
|
|
|
|
desc->interrupt = (flags & DMA_PREP_INTERRUPT) != 0;
|
|
|
|
else
|
|
|
|
desc->interrupt = false;
|
|
|
|
|
|
|
|
desc->destid = rext->destid;
|
|
|
|
desc->rio_addr = rio_addr;
|
|
|
|
desc->rio_addr_u = 0;
|
|
|
|
|
|
|
|
err = tsi721_fill_desc(bdma_chan, desc, sg, rtype, sys_size);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dchan->device->dev,
|
|
|
|
"Failed to build desc: %d\n", err);
|
|
|
|
goto err_desc_get;
|
|
|
|
}
|
|
|
|
|
|
|
|
rio_addr += sg_dma_len(sg);
|
|
|
|
|
|
|
|
if (!first)
|
|
|
|
first = desc;
|
|
|
|
else
|
|
|
|
list_add_tail(&desc->desc_node, &first->tx_list);
|
|
|
|
}
|
|
|
|
|
|
|
|
first->txd.cookie = -EBUSY;
|
|
|
|
desc->txd.flags = flags;
|
|
|
|
|
|
|
|
return &first->txd;
|
|
|
|
|
|
|
|
err_desc_get:
|
|
|
|
tsi721_desc_put(bdma_chan, first);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tsi721_device_control(struct dma_chan *dchan, enum dma_ctrl_cmd cmd,
|
|
|
|
unsigned long arg)
|
|
|
|
{
|
|
|
|
struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
|
|
|
|
struct tsi721_tx_desc *desc, *_d;
|
|
|
|
LIST_HEAD(list);
|
|
|
|
|
|
|
|
dev_dbg(dchan->device->dev, "%s: Entry\n", __func__);
|
|
|
|
|
|
|
|
if (cmd != DMA_TERMINATE_ALL)
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
spin_lock_bh(&bdma_chan->lock);
|
|
|
|
|
|
|
|
/* make sure to stop the transfer */
|
|
|
|
iowrite32(TSI721_DMAC_CTL_SUSP, bdma_chan->regs + TSI721_DMAC_CTL);
|
|
|
|
|
|
|
|
list_splice_init(&bdma_chan->active_list, &list);
|
|
|
|
list_splice_init(&bdma_chan->queue, &list);
|
|
|
|
|
|
|
|
list_for_each_entry_safe(desc, _d, &list, desc_node)
|
|
|
|
tsi721_dma_chain_complete(bdma_chan, desc);
|
|
|
|
|
|
|
|
spin_unlock_bh(&bdma_chan->lock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-20 02:23:25 +08:00
|
|
|
int tsi721_register_dma(struct tsi721_device *priv)
|
2012-06-01 07:26:39 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int nr_channels = TSI721_DMA_MAXCH;
|
|
|
|
int err;
|
|
|
|
struct rio_mport *mport = priv->mport;
|
|
|
|
|
|
|
|
mport->dma.dev = &priv->pdev->dev;
|
|
|
|
mport->dma.chancnt = nr_channels;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&mport->dma.channels);
|
|
|
|
|
|
|
|
for (i = 0; i < nr_channels; i++) {
|
|
|
|
struct tsi721_bdma_chan *bdma_chan = &priv->bdma[i];
|
|
|
|
|
|
|
|
if (i == TSI721_DMACH_MAINT)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
bdma_chan->bd_num = 64;
|
|
|
|
bdma_chan->regs = priv->regs + TSI721_DMAC_BASE(i);
|
|
|
|
|
|
|
|
bdma_chan->dchan.device = &mport->dma;
|
|
|
|
bdma_chan->dchan.cookie = 1;
|
|
|
|
bdma_chan->dchan.chan_id = i;
|
|
|
|
bdma_chan->id = i;
|
|
|
|
|
|
|
|
spin_lock_init(&bdma_chan->lock);
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&bdma_chan->active_list);
|
|
|
|
INIT_LIST_HEAD(&bdma_chan->queue);
|
|
|
|
INIT_LIST_HEAD(&bdma_chan->free_list);
|
|
|
|
|
|
|
|
tasklet_init(&bdma_chan->tasklet, tsi721_dma_tasklet,
|
|
|
|
(unsigned long)bdma_chan);
|
|
|
|
tasklet_disable(&bdma_chan->tasklet);
|
|
|
|
list_add_tail(&bdma_chan->dchan.device_node,
|
|
|
|
&mport->dma.channels);
|
|
|
|
}
|
|
|
|
|
|
|
|
dma_cap_zero(mport->dma.cap_mask);
|
|
|
|
dma_cap_set(DMA_PRIVATE, mport->dma.cap_mask);
|
|
|
|
dma_cap_set(DMA_SLAVE, mport->dma.cap_mask);
|
|
|
|
|
|
|
|
mport->dma.device_alloc_chan_resources = tsi721_alloc_chan_resources;
|
|
|
|
mport->dma.device_free_chan_resources = tsi721_free_chan_resources;
|
|
|
|
mport->dma.device_tx_status = tsi721_tx_status;
|
|
|
|
mport->dma.device_issue_pending = tsi721_issue_pending;
|
|
|
|
mport->dma.device_prep_slave_sg = tsi721_prep_rio_sg;
|
|
|
|
mport->dma.device_control = tsi721_device_control;
|
|
|
|
|
|
|
|
err = dma_async_device_register(&mport->dma);
|
|
|
|
if (err)
|
|
|
|
dev_err(&priv->pdev->dev, "Failed to register DMA device\n");
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|