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linux/include/dt-bindings/clock/exynos4.h

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ARM: exynos4: create a DT header defining CLK IDs The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:29 +08:00
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
clk: samsung: trivial: Correct typo in author's name This patch corrects mistyped author's name in four header files. While at it, a copy/paste error in author's e-mail in one of the headers is also fixed. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-26 08:57:20 +08:00
* Author: Andrzej Hajda <a.hajda@samsung.com>
ARM: exynos4: create a DT header defining CLK IDs The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:29 +08:00
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Exynos4 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
/* core clocks */
#define CLK_XXTI 1
#define CLK_XUSBXTI 2
#define CLK_FIN_PLL 3
#define CLK_FOUT_APLL 4
#define CLK_FOUT_MPLL 5
#define CLK_FOUT_EPLL 6
#define CLK_FOUT_VPLL 7
#define CLK_SCLK_APLL 8
#define CLK_SCLK_MPLL 9
#define CLK_SCLK_EPLL 10
#define CLK_SCLK_VPLL 11
#define CLK_ARM_CLK 12
#define CLK_ACLK200 13
#define CLK_ACLK100 14
#define CLK_ACLK160 15
#define CLK_ACLK133 16
#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
#define CLK_MOUT_CORE 19
#define CLK_MOUT_APLL 20
clk: samsung: exynos4: export sclk_hdmiphy clock Export sclk_hdmiphy clock to be usable from DT. Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-04-04 22:53:19 +08:00
#define CLK_SCLK_HDMIPHY 22
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
#define CLK_OUT_DMC 23
#define CLK_OUT_TOP 24
#define CLK_OUT_LEFTBUS 25
#define CLK_OUT_RIGHTBUS 26
#define CLK_OUT_CPU 27
ARM: exynos4: create a DT header defining CLK IDs The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:29 +08:00
/* gate for special clocks (sclk) */
#define CLK_SCLK_FIMC0 128
#define CLK_SCLK_FIMC1 129
#define CLK_SCLK_FIMC2 130
#define CLK_SCLK_FIMC3 131
#define CLK_SCLK_CAM0 132
#define CLK_SCLK_CAM1 133
#define CLK_SCLK_CSIS0 134
#define CLK_SCLK_CSIS1 135
#define CLK_SCLK_HDMI 136
#define CLK_SCLK_MIXER 137
#define CLK_SCLK_DAC 138
#define CLK_SCLK_PIXEL 139
#define CLK_SCLK_FIMD0 140
#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
#define CLK_SCLK_MDNIE_PWM0 142
#define CLK_SCLK_MIPI0 143
#define CLK_SCLK_AUDIO0 144
#define CLK_SCLK_MMC0 145
#define CLK_SCLK_MMC1 146
#define CLK_SCLK_MMC2 147
#define CLK_SCLK_MMC3 148
#define CLK_SCLK_MMC4 149
#define CLK_SCLK_SATA 150 /* Exynos4210 only */
#define CLK_SCLK_UART0 151
#define CLK_SCLK_UART1 152
#define CLK_SCLK_UART2 153
#define CLK_SCLK_UART3 154
#define CLK_SCLK_UART4 155
#define CLK_SCLK_AUDIO1 156
#define CLK_SCLK_AUDIO2 157
#define CLK_SCLK_SPDIF 158
#define CLK_SCLK_SPI0 159
#define CLK_SCLK_SPI1 160
#define CLK_SCLK_SPI2 161
#define CLK_SCLK_SLIMBUS 162
#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
#define CLK_SCLK_PCM1 165
#define CLK_SCLK_PCM2 166
#define CLK_SCLK_I2S1 167
#define CLK_SCLK_I2S2 168
#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
#define CLK_SCLK_MFC 170
#define CLK_SCLK_PCM0 171
#define CLK_SCLK_G3D 172
#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
#define CLK_SCLK_FIMG2D 177
/* gate clocks */
clk: samsung: exynos4: Add SSS gate clock Add a gate clock for controlling all clocks of Security Sub System (SSS). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-19 13:00:32 +08:00
#define CLK_SSS 255
ARM: exynos4: create a DT header defining CLK IDs The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:29 +08:00
#define CLK_FIMC0 256
#define CLK_FIMC1 257
#define CLK_FIMC2 258
#define CLK_FIMC3 259
#define CLK_CSIS0 260
#define CLK_CSIS1 261
#define CLK_JPEG 262
#define CLK_SMMU_FIMC0 263
#define CLK_SMMU_FIMC1 264
#define CLK_SMMU_FIMC2 265
#define CLK_SMMU_FIMC3 266
#define CLK_SMMU_JPEG 267
#define CLK_VP 268
#define CLK_MIXER 269
#define CLK_TVENC 270 /* Exynos4210 only */
#define CLK_HDMI 271
#define CLK_SMMU_TV 272
#define CLK_MFC 273
#define CLK_SMMU_MFCL 274
#define CLK_SMMU_MFCR 275
#define CLK_G3D 276
#define CLK_G2D 277
clk: samsung: exynos4: add missing smmu_g2d clock and update comments This patch adds missing smmu_g2d clock implementation and updates comment about Exynos4 clocks from 278-282 range. Those clocks are available on all Exynos4 SoC series, so the misleading comment has been removed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-16 19:54:31 +08:00
#define CLK_ROTATOR 278
#define CLK_MDMA 279
#define CLK_SMMU_G2D 280
#define CLK_SMMU_ROTATOR 281
#define CLK_SMMU_MDMA 282
ARM: exynos4: create a DT header defining CLK IDs The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:29 +08:00
#define CLK_FIMD0 283
#define CLK_MIE0 284
#define CLK_MDNIE0 285 /* Exynos4412 only */
#define CLK_DSIM0 286
#define CLK_SMMU_FIMD0 287
#define CLK_FIMD1 288 /* Exynos4210 only */
#define CLK_MIE1 289 /* Exynos4210 only */
#define CLK_DSIM1 290 /* Exynos4210 only */
#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
#define CLK_PDMA0 292
#define CLK_PDMA1 293
#define CLK_PCIE_PHY 294
#define CLK_SATA_PHY 295 /* Exynos4210 only */
#define CLK_TSI 296
#define CLK_SDMMC0 297
#define CLK_SDMMC1 298
#define CLK_SDMMC2 299
#define CLK_SDMMC3 300
#define CLK_SDMMC4 301
#define CLK_SATA 302 /* Exynos4210 only */
#define CLK_SROMC 303
#define CLK_USB_HOST 304
#define CLK_USB_DEVICE 305
#define CLK_PCIE 306
#define CLK_ONENAND 307
#define CLK_NFCON 308
#define CLK_SMMU_PCIE 309
#define CLK_GPS 310
#define CLK_SMMU_GPS 311
#define CLK_UART0 312
#define CLK_UART1 313
#define CLK_UART2 314
#define CLK_UART3 315
#define CLK_UART4 316
#define CLK_I2C0 317
#define CLK_I2C1 318
#define CLK_I2C2 319
#define CLK_I2C3 320
#define CLK_I2C4 321
#define CLK_I2C5 322
#define CLK_I2C6 323
#define CLK_I2C7 324
#define CLK_I2C_HDMI 325
#define CLK_TSADC 326
#define CLK_SPI0 327
#define CLK_SPI1 328
#define CLK_SPI2 329
#define CLK_I2S1 330
#define CLK_I2S2 331
#define CLK_PCM0 332
#define CLK_I2S0 333
#define CLK_PCM1 334
#define CLK_PCM2 335
#define CLK_PWM 336
#define CLK_SLIMBUS 337
#define CLK_SPDIF 338
#define CLK_AC97 339
#define CLK_MODEMIF 340
#define CLK_CHIPID 341
#define CLK_SYSREG 342
#define CLK_HDMI_CEC 343
#define CLK_MCT 344
#define CLK_WDT 345
#define CLK_RTC 346
#define CLK_KEYIF 347
#define CLK_AUDSS 348
#define CLK_MIPI_HSI 349 /* Exynos4210 only */
#define CLK_PIXELASYNCM0 351
#define CLK_PIXELASYNCM1 352
#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
#define CLK_PPMUISPX 355 /* Exynos4x12 only */
#define CLK_PPMUISPMX 356 /* Exynos4x12 only */
#define CLK_FIMC_ISP 357 /* Exynos4x12 only */
#define CLK_FIMC_DRC 358 /* Exynos4x12 only */
#define CLK_FIMC_FD 359 /* Exynos4x12 only */
#define CLK_MCUISP 360 /* Exynos4x12 only */
#define CLK_GICISP 361 /* Exynos4x12 only */
#define CLK_SMMU_ISP 362 /* Exynos4x12 only */
#define CLK_SMMU_DRC 363 /* Exynos4x12 only */
#define CLK_SMMU_FD 364 /* Exynos4x12 only */
#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
#define CLK_MPWM_ISP 368 /* Exynos4x12 only */
#define CLK_I2C0_ISP 369 /* Exynos4x12 only */
#define CLK_I2C1_ISP 370 /* Exynos4x12 only */
#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
#define CLK_PWM_ISP 372 /* Exynos4x12 only */
#define CLK_WDT_ISP 373 /* Exynos4x12 only */
#define CLK_UART_ISP 374 /* Exynos4x12 only */
#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
#define CLK_SPI0_ISP 377 /* Exynos4x12 only */
#define CLK_SPI1_ISP 378 /* Exynos4x12 only */
#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
#define CLK_TMU_APBIF 383
/* mux clocks */
#define CLK_MOUT_FIMC0 384
#define CLK_MOUT_FIMC1 385
#define CLK_MOUT_FIMC2 386
#define CLK_MOUT_FIMC3 387
#define CLK_MOUT_CAM0 388
#define CLK_MOUT_CAM1 389
#define CLK_MOUT_CSIS0 390
#define CLK_MOUT_CSIS1 391
#define CLK_MOUT_G3D0 392
#define CLK_MOUT_G3D1 393
#define CLK_MOUT_G3D 394
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks This patch adds support for exporting mout_hdmi and mout_mixer to device tree. Access to those clocks is required to correctly setup HDMI module on Exynos 4210 and 4x12 SoCs. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> CC: Mike Turquette <mturquette@linaro.org> CC: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-07-01 16:10:05 +08:00
#define CLK_MOUT_HDMI 396
#define CLK_MOUT_MIXER 397
ARM: exynos4: create a DT header defining CLK IDs The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:29 +08:00
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
/* gate clocks - ppmu */
#define CLK_PPMULEFT 400
#define CLK_PPMURIGHT 401
#define CLK_PPMUCAMIF 402
#define CLK_PPMUTV 403
#define CLK_PPMUMFC_L 404
#define CLK_PPMUMFC_R 405
#define CLK_PPMUG3D 406
#define CLK_PPMUIMAGE 407
#define CLK_PPMULCD0 408
#define CLK_PPMULCD1 409 /* Exynos4210 only */
#define CLK_PPMUFILE 410
#define CLK_PPMUGPS 411
#define CLK_PPMUDMC0 412
#define CLK_PPMUDMC1 413
#define CLK_PPMUCPU 414
#define CLK_PPMUACP 415
ARM: exynos4: create a DT header defining CLK IDs The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:29 +08:00
/* div clocks */
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
clk: samsung: exynos4: Add divider clock id for memory bus frequency This patch adds the divider clock id for Exynos4 memory bus frequency. The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling) feature of the exynos memory bus. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15 09:50:52 +08:00
#define CLK_DIV_ACP 456
#define CLK_DIV_DMC 457
#define CLK_DIV_C2C 458 /* Exynos4x12 only */
#define CLK_DIV_GDL 459
#define CLK_DIV_GDR 460
ARM: exynos4: create a DT header defining CLK IDs The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:29 +08:00
/* must be greater than maximal clock id */
clk: samsung: exynos4: Add divider clock id for memory bus frequency This patch adds the divider clock id for Exynos4 memory bus frequency. The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling) feature of the exynos memory bus. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15 09:50:52 +08:00
#define CLK_NR_CLKS 461
ARM: exynos4: create a DT header defining CLK IDs The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:29 +08:00
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */