2019-05-29 22:17:58 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2015-01-15 22:32:38 +08:00
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*/
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#include "phy-qcom-ufs-qmp-14nm.h"
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#define UFS_PHY_NAME "ufs_phy_qmp_14nm"
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#define UFS_PHY_VDDA_PHY_UV (925000)
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static
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int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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bool is_rate_B)
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{
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int tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
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int tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
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int err;
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err = ufs_qcom_phy_calibrate(ufs_qcom_phy, phy_cal_table_rate_A,
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tbl_size_A, phy_cal_table_rate_B, tbl_size_B, is_rate_B);
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if (err)
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dev_err(ufs_qcom_phy->dev,
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"%s: ufs_qcom_phy_calibrate() failed %d\n",
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__func__, err);
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return err;
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}
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static
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void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
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{
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phy_common->quirks =
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UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
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}
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2017-10-12 14:19:34 +08:00
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static
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2018-11-20 09:24:20 +08:00
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int ufs_qcom_phy_qmp_14nm_set_mode(struct phy *generic_phy,
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enum phy_mode mode, int submode)
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2017-10-12 14:19:34 +08:00
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{
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struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
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phy_common->mode = PHY_MODE_INVALID;
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if (mode > 0)
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phy_common->mode = mode;
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return 0;
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}
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2015-01-15 22:32:38 +08:00
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static
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void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, bool val)
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{
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writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Before any transactions involving PHY, ensure PHY knows
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* that it's analog rail is powered ON (or OFF).
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*/
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mb();
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}
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static inline
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void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
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{
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/*
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* 14nm PHY does not have TX_LANE_ENABLE register.
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* Implement this function so as not to propagate error to caller.
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*/
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}
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static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 tmp;
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tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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tmp &= ~MASK_SERDES_START;
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tmp |= (1 << OFFSET_SERDES_START);
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writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
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/* Ensure register value is committed */
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mb();
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}
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static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
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val, (val & MASK_PCS_READY), 10, 1000000);
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if (err)
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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return err;
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}
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2015-07-15 15:33:51 +08:00
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static const struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {
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2015-01-15 22:32:38 +08:00
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.power_on = ufs_qcom_phy_power_on,
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.power_off = ufs_qcom_phy_power_off,
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2017-10-12 14:19:34 +08:00
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.set_mode = ufs_qcom_phy_qmp_14nm_set_mode,
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2015-01-15 22:32:38 +08:00
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.owner = THIS_MODULE,
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};
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static struct ufs_qcom_phy_specific_ops phy_14nm_ops = {
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phy: ufs-qcom: Refactor all init steps into phy_poweron
The phy code was using implicit sequencing between the PHY driver
and the UFS driver to implement certain hardware requirements.
Specifically, the PHY reset register in the UFS controller needs
to be deasserted before serdes start occurs in the PHY.
Before this change, the code was doing this by utilizing the two
phy callbacks, phy_init() and phy_poweron(), as "init step 1" and
"init step 2", where the UFS driver would deassert reset between
these two steps.
This makes it challenging to power off the regulators in suspend,
as regulators are initialized in init, not in poweron(), but only
poweroff() is called during suspend, not exit().
For UFS, move the actual firing up of the PHY to phy_poweron() and
phy_poweroff() callbacks, rather than init()/exit(). UFS calls
phy_poweroff() during suspend, so now all clocks and regulators for
the phy can be powered down during suspend.
QMP is a little tricky because the PHY is also shared with PCIe and
USB3, which have their own definitions for init() and poweron(). Rename
the meaty functions to _enable() and _disable() to disentangle from the
PHY core names, and then create two different ops structures: one for
UFS and one for the other PHY types.
In phy-qcom-ufs, remove the 'is_powered_on' and 'is_started' guards,
as the generic PHY code does the reference counting. The
14/20nm-specific init functions get collapsed into the generic power_on()
function, with the addition of a calibrate() callback specific to 14/20nm.
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-03-22 01:18:00 +08:00
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.calibrate = ufs_qcom_phy_qmp_14nm_phy_calibrate,
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2015-01-15 22:32:38 +08:00
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.start_serdes = ufs_qcom_phy_qmp_14nm_start_serdes,
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.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready,
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.set_tx_lane_enable = ufs_qcom_phy_qmp_14nm_set_tx_lane_enable,
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.power_control = ufs_qcom_phy_qmp_14nm_power_control,
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};
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static int ufs_qcom_phy_qmp_14nm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
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struct ufs_qcom_phy_qmp_14nm *phy;
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2016-11-08 18:07:47 +08:00
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struct ufs_qcom_phy *phy_common;
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2015-01-15 22:32:38 +08:00
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int err = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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err = -ENOMEM;
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goto out;
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}
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2016-11-08 18:07:47 +08:00
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phy_common = &phy->common_cfg;
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2015-01-15 22:32:38 +08:00
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2016-11-08 18:07:47 +08:00
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generic_phy = ufs_qcom_phy_generic_probe(pdev, phy_common,
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2015-01-15 22:32:38 +08:00
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&ufs_qcom_phy_qmp_14nm_phy_ops, &phy_14nm_ops);
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if (!generic_phy) {
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err = -EIO;
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goto out;
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}
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2016-11-08 18:07:47 +08:00
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err = ufs_qcom_phy_init_clks(phy_common);
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2017-01-23 05:17:49 +08:00
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if (err)
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2016-11-08 18:07:47 +08:00
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goto out;
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err = ufs_qcom_phy_init_vregulators(phy_common);
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2017-01-23 05:17:49 +08:00
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if (err)
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2016-11-08 18:07:47 +08:00
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goto out;
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2017-01-23 05:17:49 +08:00
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2016-11-08 18:07:47 +08:00
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phy_common->vdda_phy.max_uV = UFS_PHY_VDDA_PHY_UV;
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phy_common->vdda_phy.min_uV = UFS_PHY_VDDA_PHY_UV;
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ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common);
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2015-01-15 22:32:38 +08:00
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phy_set_drvdata(generic_phy, phy);
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2016-11-08 18:07:47 +08:00
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strlcpy(phy_common->name, UFS_PHY_NAME, sizeof(phy_common->name));
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2015-01-15 22:32:38 +08:00
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out:
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return err;
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}
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static const struct of_device_id ufs_qcom_phy_qmp_14nm_of_match[] = {
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{.compatible = "qcom,ufs-phy-qmp-14nm"},
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2016-11-08 18:07:43 +08:00
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{.compatible = "qcom,msm8996-ufs-phy-qmp-14nm"},
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2015-01-15 22:32:38 +08:00
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_14nm_of_match);
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static struct platform_driver ufs_qcom_phy_qmp_14nm_driver = {
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.probe = ufs_qcom_phy_qmp_14nm_probe,
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.driver = {
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.of_match_table = ufs_qcom_phy_qmp_14nm_of_match,
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.name = "ufs_qcom_phy_qmp_14nm",
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},
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};
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module_platform_driver(ufs_qcom_phy_qmp_14nm_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 14nm");
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MODULE_LICENSE("GPL v2");
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