2011-04-04 20:44:19 +08:00
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/*
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* Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
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*
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2012-02-15 00:23:46 +08:00
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* Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd.
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* Sylwester Nawrocki, <s.nawrocki@samsung.com>
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2011-04-04 20:44:19 +08:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/memory.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/videodev2.h>
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#include <media/v4l2-subdev.h>
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#include <plat/mipi_csis.h>
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#include "mipi-csis.h"
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static int debug;
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "Debug level (0-1)");
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/* Register map definition */
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/* CSIS global control */
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#define S5PCSIS_CTRL 0x00
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#define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31)
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#define S5PCSIS_CTRL_DPDN_SWAP (1 << 31)
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#define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20)
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#define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16)
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#define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8)
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#define S5PCSIS_CTRL_RESET (1 << 4)
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#define S5PCSIS_CTRL_ENABLE (1 << 0)
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/* D-PHY control */
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#define S5PCSIS_DPHYCTRL 0x04
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#define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27)
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#define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0)
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#define S5PCSIS_CONFIG 0x08
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#define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2)
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#define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2)
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#define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2)
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#define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2)
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/* User defined formats, x = 1...4 */
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#define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2)
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#define S5PCSIS_CFG_FMT_MASK (0x3f << 2)
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#define S5PCSIS_CFG_NR_LANE_MASK 3
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/* Interrupt mask. */
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#define S5PCSIS_INTMSK 0x10
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#define S5PCSIS_INTMSK_EN_ALL 0xf000003f
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#define S5PCSIS_INTSRC 0x14
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/* Pixel resolution */
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#define S5PCSIS_RESOL 0x2c
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#define CSIS_MAX_PIX_WIDTH 0xffff
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#define CSIS_MAX_PIX_HEIGHT 0xffff
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enum {
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CSIS_CLK_MUX,
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CSIS_CLK_GATE,
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};
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static char *csi_clock_name[] = {
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[CSIS_CLK_MUX] = "sclk_csis",
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[CSIS_CLK_GATE] = "csis",
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};
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#define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
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2011-06-30 00:08:49 +08:00
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static const char * const csis_supply_name[] = {
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"vdd11", /* 1.1V or 1.2V (s5pc100) MIPI CSI suppply */
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"vdd18", /* VDD 1.8V and MIPI CSI PLL supply */
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};
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#define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name)
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2011-04-04 20:44:19 +08:00
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enum {
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ST_POWERED = 1,
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ST_STREAMING = 2,
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ST_SUSPENDED = 4,
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};
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/**
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* struct csis_state - the driver's internal state data structure
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* @lock: mutex serializing the subdev and power management operations,
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* protecting @format and @flags members
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* @pads: CSIS pads array
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* @sd: v4l2_subdev associated with CSIS device instance
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* @pdev: CSIS platform device
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* @regs: mmaped I/O registers memory
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* @clock: CSIS clocks
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* @irq: requested s5p-mipi-csis irq number
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* @flags: the state variable for power and streaming control
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* @csis_fmt: current CSIS pixel format
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* @format: common media bus format for the source and sink pad
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*/
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struct csis_state {
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struct mutex lock;
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struct media_pad pads[CSIS_PADS_NUM];
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struct v4l2_subdev sd;
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struct platform_device *pdev;
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void __iomem *regs;
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2011-06-30 00:08:49 +08:00
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struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES];
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2011-04-04 20:44:19 +08:00
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struct clk *clock[NUM_CSIS_CLOCKS];
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int irq;
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u32 flags;
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const struct csis_pix_format *csis_fmt;
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struct v4l2_mbus_framefmt format;
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};
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/**
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* struct csis_pix_format - CSIS pixel format description
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* @pix_width_alignment: horizontal pixel alignment, width will be
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* multiple of 2^pix_width_alignment
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* @code: corresponding media bus code
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* @fmt_reg: S5PCSIS_CONFIG register value
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2012-03-21 17:21:30 +08:00
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* @data_alignment: MIPI-CSI data alignment in bits
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2011-04-04 20:44:19 +08:00
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*/
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struct csis_pix_format {
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unsigned int pix_width_alignment;
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enum v4l2_mbus_pixelcode code;
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u32 fmt_reg;
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2012-03-21 17:21:30 +08:00
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u8 data_alignment;
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2011-04-04 20:44:19 +08:00
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};
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static const struct csis_pix_format s5pcsis_formats[] = {
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{
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.code = V4L2_MBUS_FMT_VYUY8_2X8,
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.fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
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2012-03-21 17:21:30 +08:00
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.data_alignment = 32,
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2011-04-04 20:44:19 +08:00
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}, {
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.code = V4L2_MBUS_FMT_JPEG_1X8,
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.fmt_reg = S5PCSIS_CFG_FMT_USER(1),
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2012-03-21 17:21:30 +08:00
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.data_alignment = 32,
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2011-04-04 20:44:19 +08:00
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},
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};
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#define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
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#define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
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static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
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{
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return container_of(sdev, struct csis_state, sd);
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}
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static const struct csis_pix_format *find_csis_format(
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struct v4l2_mbus_framefmt *mf)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
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if (mf->code == s5pcsis_formats[i].code)
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return &s5pcsis_formats[i];
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return NULL;
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}
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static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
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{
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u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
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val = on ? val | S5PCSIS_INTMSK_EN_ALL :
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val & ~S5PCSIS_INTMSK_EN_ALL;
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s5pcsis_write(state, S5PCSIS_INTMSK, val);
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}
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static void s5pcsis_reset(struct csis_state *state)
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{
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u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
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s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
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udelay(10);
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}
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static void s5pcsis_system_enable(struct csis_state *state, int on)
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{
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u32 val;
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val = s5pcsis_read(state, S5PCSIS_CTRL);
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if (on)
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val |= S5PCSIS_CTRL_ENABLE;
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else
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val &= ~S5PCSIS_CTRL_ENABLE;
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s5pcsis_write(state, S5PCSIS_CTRL, val);
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val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
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if (on)
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val |= S5PCSIS_DPHYCTRL_ENABLE;
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else
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val &= ~S5PCSIS_DPHYCTRL_ENABLE;
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s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
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}
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/* Called with the state.lock mutex held */
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static void __s5pcsis_set_format(struct csis_state *state)
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{
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struct v4l2_mbus_framefmt *mf = &state->format;
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u32 val;
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v4l2_dbg(1, debug, &state->sd, "fmt: %d, %d x %d\n",
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mf->code, mf->width, mf->height);
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/* Color format */
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val = s5pcsis_read(state, S5PCSIS_CONFIG);
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val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
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s5pcsis_write(state, S5PCSIS_CONFIG, val);
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/* Pixel resolution */
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val = (mf->width << 16) | mf->height;
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s5pcsis_write(state, S5PCSIS_RESOL, val);
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}
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static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
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{
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u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
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val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
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s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
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}
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static void s5pcsis_set_params(struct csis_state *state)
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{
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struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data;
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u32 val;
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val = s5pcsis_read(state, S5PCSIS_CONFIG);
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val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1);
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s5pcsis_write(state, S5PCSIS_CONFIG, val);
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__s5pcsis_set_format(state);
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s5pcsis_set_hsync_settle(state, pdata->hs_settle);
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val = s5pcsis_read(state, S5PCSIS_CTRL);
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2012-03-21 17:21:30 +08:00
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if (state->csis_fmt->data_alignment == 32)
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2011-04-04 20:44:19 +08:00
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val |= S5PCSIS_CTRL_ALIGN_32BIT;
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else /* 24-bits */
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val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
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/* Not using external clock. */
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val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
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s5pcsis_write(state, S5PCSIS_CTRL, val);
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/* Update the shadow register. */
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val = s5pcsis_read(state, S5PCSIS_CTRL);
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s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
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}
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static void s5pcsis_clk_put(struct csis_state *state)
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{
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int i;
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2012-01-30 22:39:30 +08:00
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for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
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if (IS_ERR_OR_NULL(state->clock[i]))
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continue;
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clk_unprepare(state->clock[i]);
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clk_put(state->clock[i]);
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state->clock[i] = NULL;
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}
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2011-04-04 20:44:19 +08:00
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}
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static int s5pcsis_clk_get(struct csis_state *state)
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{
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struct device *dev = &state->pdev->dev;
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2012-01-30 22:39:30 +08:00
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int i, ret;
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2011-04-04 20:44:19 +08:00
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for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
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state->clock[i] = clk_get(dev, csi_clock_name[i]);
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2012-01-30 22:39:30 +08:00
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if (IS_ERR(state->clock[i]))
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goto err;
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ret = clk_prepare(state->clock[i]);
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if (ret < 0) {
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clk_put(state->clock[i]);
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state->clock[i] = NULL;
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goto err;
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2011-04-04 20:44:19 +08:00
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}
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}
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return 0;
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2012-01-30 22:39:30 +08:00
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err:
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s5pcsis_clk_put(state);
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dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]);
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return -ENXIO;
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2011-04-04 20:44:19 +08:00
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}
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static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
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{
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struct csis_state *state = sd_to_csis_state(sd);
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struct device *dev = &state->pdev->dev;
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if (on)
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return pm_runtime_get_sync(dev);
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return pm_runtime_put_sync(dev);
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}
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static void s5pcsis_start_stream(struct csis_state *state)
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{
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s5pcsis_reset(state);
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s5pcsis_set_params(state);
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s5pcsis_system_enable(state, true);
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s5pcsis_enable_interrupts(state, true);
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}
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static void s5pcsis_stop_stream(struct csis_state *state)
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{
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s5pcsis_enable_interrupts(state, false);
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s5pcsis_system_enable(state, false);
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}
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/* v4l2_subdev operations */
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static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
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{
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struct csis_state *state = sd_to_csis_state(sd);
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int ret = 0;
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v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
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|
|
__func__, enable, state->flags);
|
|
|
|
|
|
|
|
if (enable) {
|
|
|
|
ret = pm_runtime_get_sync(&state->pdev->dev);
|
|
|
|
if (ret && ret != 1)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
mutex_lock(&state->lock);
|
|
|
|
if (enable) {
|
|
|
|
if (state->flags & ST_SUSPENDED) {
|
|
|
|
ret = -EBUSY;
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
s5pcsis_start_stream(state);
|
|
|
|
state->flags |= ST_STREAMING;
|
|
|
|
} else {
|
|
|
|
s5pcsis_stop_stream(state);
|
|
|
|
state->flags &= ~ST_STREAMING;
|
|
|
|
}
|
|
|
|
unlock:
|
|
|
|
mutex_unlock(&state->lock);
|
|
|
|
if (!enable)
|
|
|
|
pm_runtime_put(&state->pdev->dev);
|
|
|
|
|
|
|
|
return ret == 1 ? 0 : ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
|
|
|
|
struct v4l2_subdev_fh *fh,
|
|
|
|
struct v4l2_subdev_mbus_code_enum *code)
|
|
|
|
{
|
|
|
|
if (code->index >= ARRAY_SIZE(s5pcsis_formats))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
code->code = s5pcsis_formats[code->index].code;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct csis_pix_format const *s5pcsis_try_format(
|
|
|
|
struct v4l2_mbus_framefmt *mf)
|
|
|
|
{
|
|
|
|
struct csis_pix_format const *csis_fmt;
|
|
|
|
|
|
|
|
csis_fmt = find_csis_format(mf);
|
|
|
|
if (csis_fmt == NULL)
|
|
|
|
csis_fmt = &s5pcsis_formats[0];
|
|
|
|
|
|
|
|
mf->code = csis_fmt->code;
|
|
|
|
v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
|
|
|
|
csis_fmt->pix_width_alignment,
|
|
|
|
&mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
|
|
|
|
0);
|
|
|
|
return csis_fmt;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
|
|
|
|
struct csis_state *state, struct v4l2_subdev_fh *fh,
|
|
|
|
u32 pad, enum v4l2_subdev_format_whence which)
|
|
|
|
{
|
|
|
|
if (which == V4L2_SUBDEV_FORMAT_TRY)
|
|
|
|
return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL;
|
|
|
|
|
|
|
|
return &state->format;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
|
|
|
|
struct v4l2_subdev_format *fmt)
|
|
|
|
{
|
|
|
|
struct csis_state *state = sd_to_csis_state(sd);
|
|
|
|
struct csis_pix_format const *csis_fmt;
|
|
|
|
struct v4l2_mbus_framefmt *mf;
|
|
|
|
|
|
|
|
if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
|
|
|
|
|
|
|
|
if (fmt->pad == CSIS_PAD_SOURCE) {
|
|
|
|
if (mf) {
|
|
|
|
mutex_lock(&state->lock);
|
|
|
|
fmt->format = *mf;
|
|
|
|
mutex_unlock(&state->lock);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
csis_fmt = s5pcsis_try_format(&fmt->format);
|
|
|
|
if (mf) {
|
|
|
|
mutex_lock(&state->lock);
|
|
|
|
*mf = fmt->format;
|
|
|
|
if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
|
|
|
|
state->csis_fmt = csis_fmt;
|
|
|
|
mutex_unlock(&state->lock);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
|
|
|
|
struct v4l2_subdev_format *fmt)
|
|
|
|
{
|
|
|
|
struct csis_state *state = sd_to_csis_state(sd);
|
|
|
|
struct v4l2_mbus_framefmt *mf;
|
|
|
|
|
|
|
|
if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
|
|
|
|
if (!mf)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mutex_lock(&state->lock);
|
|
|
|
fmt->format = *mf;
|
|
|
|
mutex_unlock(&state->lock);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-11-16 02:34:06 +08:00
|
|
|
static int s5pcsis_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
|
|
|
|
{
|
|
|
|
struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0);
|
|
|
|
|
|
|
|
format->colorspace = V4L2_COLORSPACE_JPEG;
|
|
|
|
format->code = s5pcsis_formats[0].code;
|
|
|
|
format->width = S5PCSIS_DEF_PIX_WIDTH;
|
|
|
|
format->height = S5PCSIS_DEF_PIX_HEIGHT;
|
|
|
|
format->field = V4L2_FIELD_NONE;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct v4l2_subdev_internal_ops s5pcsis_sd_internal_ops = {
|
|
|
|
.open = s5pcsis_open,
|
|
|
|
};
|
|
|
|
|
2011-04-04 20:44:19 +08:00
|
|
|
static struct v4l2_subdev_core_ops s5pcsis_core_ops = {
|
|
|
|
.s_power = s5pcsis_s_power,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
|
|
|
|
.enum_mbus_code = s5pcsis_enum_mbus_code,
|
|
|
|
.get_fmt = s5pcsis_get_fmt,
|
|
|
|
.set_fmt = s5pcsis_set_fmt,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
|
|
|
|
.s_stream = s5pcsis_s_stream,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct v4l2_subdev_ops s5pcsis_subdev_ops = {
|
|
|
|
.core = &s5pcsis_core_ops,
|
|
|
|
.pad = &s5pcsis_pad_ops,
|
|
|
|
.video = &s5pcsis_video_ops,
|
|
|
|
};
|
|
|
|
|
|
|
|
static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct csis_state *state = dev_id;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
/* Just clear the interrupt pending bits. */
|
|
|
|
val = s5pcsis_read(state, S5PCSIS_INTSRC);
|
|
|
|
s5pcsis_write(state, S5PCSIS_INTSRC, val);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __devinit s5pcsis_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct s5p_platform_mipi_csis *pdata;
|
|
|
|
struct resource *mem_res;
|
|
|
|
struct csis_state *state;
|
|
|
|
int ret = -ENOMEM;
|
2011-06-30 00:08:49 +08:00
|
|
|
int i;
|
2011-04-04 20:44:19 +08:00
|
|
|
|
2012-02-15 00:23:46 +08:00
|
|
|
state = devm_kzalloc(&pdev->dev, sizeof(*state), GFP_KERNEL);
|
2011-04-04 20:44:19 +08:00
|
|
|
if (!state)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
mutex_init(&state->lock);
|
|
|
|
state->pdev = pdev;
|
|
|
|
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
|
|
if (pdata == NULL || pdata->phy_enable == NULL) {
|
|
|
|
dev_err(&pdev->dev, "Platform data not fully specified\n");
|
2012-02-15 00:23:46 +08:00
|
|
|
return -EINVAL;
|
2011-04-04 20:44:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if ((pdev->id == 1 && pdata->lanes > CSIS1_MAX_LANES) ||
|
|
|
|
pdata->lanes > CSIS0_MAX_LANES) {
|
|
|
|
dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n",
|
|
|
|
pdata->lanes);
|
2012-02-15 00:23:46 +08:00
|
|
|
return -EINVAL;
|
2011-04-04 20:44:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2012-02-15 00:23:46 +08:00
|
|
|
state->regs = devm_request_and_ioremap(&pdev->dev, mem_res);
|
|
|
|
if (state->regs == NULL) {
|
|
|
|
dev_err(&pdev->dev, "Failed to request and remap io memory\n");
|
|
|
|
return -ENXIO;
|
2011-04-04 20:44:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
state->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (state->irq < 0) {
|
|
|
|
dev_err(&pdev->dev, "Failed to get irq\n");
|
2012-02-15 00:23:46 +08:00
|
|
|
return state->irq;
|
2011-04-04 20:44:19 +08:00
|
|
|
}
|
|
|
|
|
2011-06-30 00:08:49 +08:00
|
|
|
for (i = 0; i < CSIS_NUM_SUPPLIES; i++)
|
|
|
|
state->supplies[i].supply = csis_supply_name[i];
|
|
|
|
|
|
|
|
ret = regulator_bulk_get(&pdev->dev, CSIS_NUM_SUPPLIES,
|
|
|
|
state->supplies);
|
2012-02-15 00:23:46 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = s5pcsis_clk_get(state);
|
2011-06-30 00:08:49 +08:00
|
|
|
if (ret)
|
|
|
|
goto e_clkput;
|
2011-04-04 20:44:19 +08:00
|
|
|
|
2012-02-15 00:23:46 +08:00
|
|
|
clk_enable(state->clock[CSIS_CLK_MUX]);
|
|
|
|
if (pdata->clk_rate)
|
|
|
|
clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate);
|
|
|
|
else
|
|
|
|
dev_WARN(&pdev->dev, "No clock frequency specified!\n");
|
|
|
|
|
|
|
|
ret = devm_request_irq(&pdev->dev, state->irq, s5pcsis_irq_handler,
|
|
|
|
0, dev_name(&pdev->dev), state);
|
2011-04-04 20:44:19 +08:00
|
|
|
if (ret) {
|
2012-02-15 00:23:46 +08:00
|
|
|
dev_err(&pdev->dev, "Interrupt request failed\n");
|
2011-04-04 20:44:19 +08:00
|
|
|
goto e_regput;
|
|
|
|
}
|
|
|
|
|
|
|
|
v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
|
|
|
|
state->sd.owner = THIS_MODULE;
|
|
|
|
strlcpy(state->sd.name, dev_name(&pdev->dev), sizeof(state->sd.name));
|
2011-11-16 02:34:06 +08:00
|
|
|
state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
|
2011-04-04 20:44:19 +08:00
|
|
|
state->csis_fmt = &s5pcsis_formats[0];
|
|
|
|
|
2011-11-16 02:34:06 +08:00
|
|
|
state->format.code = s5pcsis_formats[0].code;
|
|
|
|
state->format.width = S5PCSIS_DEF_PIX_WIDTH;
|
|
|
|
state->format.height = S5PCSIS_DEF_PIX_HEIGHT;
|
|
|
|
|
2011-04-04 20:44:19 +08:00
|
|
|
state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
|
|
|
|
state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
|
|
|
|
ret = media_entity_init(&state->sd.entity,
|
|
|
|
CSIS_PADS_NUM, state->pads, 0);
|
|
|
|
if (ret < 0)
|
2012-02-15 00:23:46 +08:00
|
|
|
goto e_clkput;
|
2011-04-04 20:44:19 +08:00
|
|
|
|
|
|
|
/* This allows to retrieve the platform device id by the host driver */
|
|
|
|
v4l2_set_subdevdata(&state->sd, pdev);
|
|
|
|
|
|
|
|
/* .. and a pointer to the subdev. */
|
|
|
|
platform_set_drvdata(pdev, &state->sd);
|
|
|
|
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
e_regput:
|
2011-06-30 00:08:49 +08:00
|
|
|
regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies);
|
2011-04-04 20:44:19 +08:00
|
|
|
e_clkput:
|
|
|
|
clk_disable(state->clock[CSIS_CLK_MUX]);
|
|
|
|
s5pcsis_clk_put(state);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-07-07 23:13:25 +08:00
|
|
|
static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
|
2011-04-04 20:44:19 +08:00
|
|
|
{
|
|
|
|
struct s5p_platform_mipi_csis *pdata = dev->platform_data;
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
|
|
|
|
struct csis_state *state = sd_to_csis_state(sd);
|
2011-05-18 23:06:40 +08:00
|
|
|
int ret = 0;
|
2011-04-04 20:44:19 +08:00
|
|
|
|
|
|
|
v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
|
|
|
|
__func__, state->flags);
|
|
|
|
|
|
|
|
mutex_lock(&state->lock);
|
|
|
|
if (state->flags & ST_POWERED) {
|
|
|
|
s5pcsis_stop_stream(state);
|
|
|
|
ret = pdata->phy_enable(state->pdev, false);
|
|
|
|
if (ret)
|
|
|
|
goto unlock;
|
2011-06-30 00:08:49 +08:00
|
|
|
ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES,
|
|
|
|
state->supplies);
|
|
|
|
if (ret)
|
|
|
|
goto unlock;
|
2011-04-04 20:44:19 +08:00
|
|
|
clk_disable(state->clock[CSIS_CLK_GATE]);
|
|
|
|
state->flags &= ~ST_POWERED;
|
2011-07-07 23:13:25 +08:00
|
|
|
if (!runtime)
|
|
|
|
state->flags |= ST_SUSPENDED;
|
2011-04-04 20:44:19 +08:00
|
|
|
}
|
|
|
|
unlock:
|
|
|
|
mutex_unlock(&state->lock);
|
|
|
|
return ret ? -EAGAIN : 0;
|
|
|
|
}
|
|
|
|
|
2011-07-07 23:13:25 +08:00
|
|
|
static int s5pcsis_pm_resume(struct device *dev, bool runtime)
|
2011-04-04 20:44:19 +08:00
|
|
|
{
|
|
|
|
struct s5p_platform_mipi_csis *pdata = dev->platform_data;
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
|
|
|
|
struct csis_state *state = sd_to_csis_state(sd);
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
|
|
|
|
__func__, state->flags);
|
|
|
|
|
|
|
|
mutex_lock(&state->lock);
|
2011-07-07 23:13:25 +08:00
|
|
|
if (!runtime && !(state->flags & ST_SUSPENDED))
|
2011-04-04 20:44:19 +08:00
|
|
|
goto unlock;
|
|
|
|
|
|
|
|
if (!(state->flags & ST_POWERED)) {
|
2011-06-30 00:08:49 +08:00
|
|
|
ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES,
|
|
|
|
state->supplies);
|
2011-04-04 20:44:19 +08:00
|
|
|
if (ret)
|
|
|
|
goto unlock;
|
|
|
|
ret = pdata->phy_enable(state->pdev, true);
|
|
|
|
if (!ret) {
|
|
|
|
state->flags |= ST_POWERED;
|
2011-06-30 00:08:49 +08:00
|
|
|
} else {
|
|
|
|
regulator_bulk_disable(CSIS_NUM_SUPPLIES,
|
|
|
|
state->supplies);
|
2011-04-04 20:44:19 +08:00
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
clk_enable(state->clock[CSIS_CLK_GATE]);
|
|
|
|
}
|
|
|
|
if (state->flags & ST_STREAMING)
|
|
|
|
s5pcsis_start_stream(state);
|
|
|
|
|
|
|
|
state->flags &= ~ST_SUSPENDED;
|
|
|
|
unlock:
|
|
|
|
mutex_unlock(&state->lock);
|
|
|
|
return ret ? -EAGAIN : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2011-07-07 23:13:25 +08:00
|
|
|
static int s5pcsis_suspend(struct device *dev)
|
2011-04-04 20:44:19 +08:00
|
|
|
{
|
2011-07-07 23:13:25 +08:00
|
|
|
return s5pcsis_pm_suspend(dev, false);
|
2011-04-04 20:44:19 +08:00
|
|
|
}
|
|
|
|
|
2011-07-07 23:13:25 +08:00
|
|
|
static int s5pcsis_resume(struct device *dev)
|
2011-04-04 20:44:19 +08:00
|
|
|
{
|
2011-07-07 23:13:25 +08:00
|
|
|
return s5pcsis_pm_resume(dev, false);
|
|
|
|
}
|
|
|
|
#endif
|
2011-04-04 20:44:19 +08:00
|
|
|
|
2011-07-07 23:13:25 +08:00
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
|
|
static int s5pcsis_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
return s5pcsis_pm_suspend(dev, true);
|
|
|
|
}
|
2011-04-04 20:44:19 +08:00
|
|
|
|
2011-07-07 23:13:25 +08:00
|
|
|
static int s5pcsis_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
return s5pcsis_pm_resume(dev, true);
|
2011-04-04 20:44:19 +08:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static int __devexit s5pcsis_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
|
|
|
|
struct csis_state *state = sd_to_csis_state(sd);
|
|
|
|
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2012-03-09 19:56:39 +08:00
|
|
|
s5pcsis_pm_suspend(&pdev->dev, false);
|
2011-04-04 20:44:19 +08:00
|
|
|
clk_disable(state->clock[CSIS_CLK_MUX]);
|
|
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
|
|
s5pcsis_clk_put(state);
|
2011-06-30 00:08:49 +08:00
|
|
|
regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies);
|
2011-04-04 20:44:19 +08:00
|
|
|
|
|
|
|
media_entity_cleanup(&state->sd.entity);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dev_pm_ops s5pcsis_pm_ops = {
|
2011-07-07 23:13:25 +08:00
|
|
|
SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume,
|
|
|
|
NULL)
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume)
|
2011-04-04 20:44:19 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_driver s5pcsis_driver = {
|
|
|
|
.probe = s5pcsis_probe,
|
|
|
|
.remove = __devexit_p(s5pcsis_remove),
|
|
|
|
.driver = {
|
|
|
|
.name = CSIS_DRIVER_NAME,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.pm = &s5pcsis_pm_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-03-21 20:58:09 +08:00
|
|
|
module_platform_driver(s5pcsis_driver);
|
2011-04-04 20:44:19 +08:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
|
2012-03-21 20:58:09 +08:00
|
|
|
MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI-CSI2 receiver driver");
|
2011-04-04 20:44:19 +08:00
|
|
|
MODULE_LICENSE("GPL");
|