2008-03-28 02:51:40 +08:00
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/*
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* arch/arm/plat-orion/irq.c
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*
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* Marvell Orion SoC IRQ handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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2012-06-27 19:40:04 +08:00
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#include <linux/irqdomain.h>
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2008-03-28 02:51:40 +08:00
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#include <linux/io.h>
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2012-06-27 19:40:04 +08:00
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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2014-01-16 16:10:31 +08:00
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#include <asm/exception.h>
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2008-08-09 19:44:58 +08:00
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#include <plat/irq.h>
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2012-08-29 23:16:55 +08:00
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#include <plat/orion-gpio.h>
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2014-01-16 16:10:31 +08:00
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#include <mach/bridge-regs.h>
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2008-03-28 02:51:40 +08:00
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void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
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{
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2011-04-15 01:17:57 +08:00
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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2008-03-28 02:51:40 +08:00
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/*
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* Mask all interrupts initially.
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*/
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writel(0, maskaddr);
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2011-04-15 01:17:57 +08:00
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gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
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handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
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2008-03-28 02:51:40 +08:00
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}
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