2018-12-28 16:31:53 +08:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0
|
|
|
|
*
|
2005-04-17 06:20:36 +08:00
|
|
|
* include/asm-sh/cpu-sh4/mmu_context.h
|
|
|
|
*
|
|
|
|
* Copyright (C) 1999 Niibe Yutaka
|
|
|
|
*/
|
|
|
|
#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
|
|
|
|
#define __ASM_CPU_SH4_MMU_CONTEXT_H
|
|
|
|
|
|
|
|
#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
|
|
|
|
#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
|
|
|
|
#define MMU_TTB 0xFF000008 /* Translation table base register */
|
|
|
|
#define MMU_TEA 0xFF00000C /* TLB Exception Address */
|
2009-03-17 16:49:49 +08:00
|
|
|
#define MMU_PTEA 0xFF000034 /* PTE assistance register */
|
|
|
|
#define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#define MMUCR 0xFF000010 /* MMU Control Register */
|
|
|
|
|
2010-03-29 14:24:54 +08:00
|
|
|
#define MMU_TLB_ENTRY_SHIFT 8
|
|
|
|
|
2010-03-22 03:51:43 +08:00
|
|
|
#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
|
|
|
|
#define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
|
2010-03-29 14:24:54 +08:00
|
|
|
#define MMU_ITLB_DATA_ARRAY 0xF3000000
|
|
|
|
#define MMU_ITLB_DATA_ARRAY2 0xF3800000
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
|
2009-03-17 16:49:49 +08:00
|
|
|
#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
|
2010-03-29 14:24:54 +08:00
|
|
|
#define MMU_UTLB_DATA_ARRAY 0xF7000000
|
|
|
|
#define MMU_UTLB_DATA_ARRAY2 0xF7800000
|
2005-04-17 06:20:36 +08:00
|
|
|
#define MMU_PAGE_ASSOC_BIT 0x80
|
|
|
|
|
2010-04-07 16:08:32 +08:00
|
|
|
#ifdef CONFIG_MMU
|
|
|
|
#define MMUCR_AT (1 << 0)
|
|
|
|
#else
|
|
|
|
#define MMUCR_AT (0)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#define MMUCR_TI (1 << 2)
|
2007-11-26 20:32:40 +08:00
|
|
|
|
2009-11-18 05:05:31 +08:00
|
|
|
#define MMUCR_URB 0x00FC0000
|
|
|
|
#define MMUCR_URB_SHIFT 18
|
|
|
|
#define MMUCR_URB_NENTRIES 64
|
2010-03-26 10:37:16 +08:00
|
|
|
#define MMUCR_URC 0x0000FC00
|
|
|
|
#define MMUCR_URC_SHIFT 10
|
2009-11-18 05:05:31 +08:00
|
|
|
|
2007-11-30 16:52:53 +08:00
|
|
|
#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
|
|
|
|
#define MMUCR_SE (1 << 4)
|
|
|
|
#else
|
|
|
|
#define MMUCR_SE (0)
|
|
|
|
#endif
|
|
|
|
|
2009-03-17 16:49:49 +08:00
|
|
|
#ifdef CONFIG_CPU_HAS_PTEAEX
|
|
|
|
#define MMUCR_AEX (1 << 6)
|
|
|
|
#else
|
|
|
|
#define MMUCR_AEX (0)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_X2TLB
|
|
|
|
#define MMUCR_ME (1 << 7)
|
|
|
|
#else
|
|
|
|
#define MMUCR_ME (0)
|
|
|
|
#endif
|
|
|
|
|
2006-02-01 19:06:01 +08:00
|
|
|
#ifdef CONFIG_SH_STORE_QUEUES
|
2007-09-21 10:55:03 +08:00
|
|
|
#define MMUCR_SQMD (1 << 9)
|
2006-02-01 19:06:01 +08:00
|
|
|
#else
|
2007-09-21 10:55:03 +08:00
|
|
|
#define MMUCR_SQMD (0)
|
2006-02-01 19:06:01 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-09-21 10:55:03 +08:00
|
|
|
#define MMU_NTLB_ENTRIES 64
|
2010-04-07 16:08:32 +08:00
|
|
|
#define MMU_CONTROL_INIT (MMUCR_AT | MMUCR_TI | MMUCR_SQMD | \
|
|
|
|
MMUCR_ME | MMUCR_SE | MMUCR_AEX)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-02-01 19:06:01 +08:00
|
|
|
#define TRA 0xff000020
|
|
|
|
#define EXPEVT 0xff000024
|
|
|
|
#define INTEVT 0xff000028
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
|
|
|
|
|