2018-03-20 22:58:05 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_H_
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#define _ICE_H_
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/compiler.h>
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2018-03-20 22:58:09 +08:00
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#include <linux/etherdevice.h>
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2018-03-20 22:58:13 +08:00
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#include <linux/skbuff.h>
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2018-03-20 22:58:11 +08:00
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#include <linux/cpumask.h>
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2018-03-20 22:58:16 +08:00
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#include <linux/rtnetlink.h>
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2018-03-20 22:58:11 +08:00
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#include <linux/if_vlan.h>
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2018-03-20 22:58:13 +08:00
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#include <linux/dma-mapping.h>
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2018-03-20 22:58:05 +08:00
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#include <linux/pci.h>
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2018-03-20 22:58:10 +08:00
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#include <linux/workqueue.h>
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2018-03-20 22:58:05 +08:00
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#include <linux/aer.h>
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2018-03-20 22:58:10 +08:00
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#include <linux/interrupt.h>
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2018-03-20 22:58:16 +08:00
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#include <linux/ethtool.h>
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2018-03-20 22:58:10 +08:00
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#include <linux/timer.h>
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2018-03-20 22:58:06 +08:00
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#include <linux/delay.h>
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2018-03-20 22:58:05 +08:00
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#include <linux/bitmap.h>
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2018-03-20 22:58:11 +08:00
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#include <linux/log2.h>
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2018-03-20 22:58:15 +08:00
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#include <linux/ip.h>
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#include <linux/ipv6.h>
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2018-03-20 22:58:10 +08:00
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#include <linux/if_bridge.h>
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2018-03-20 22:58:15 +08:00
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#include <net/ipv6.h>
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2018-03-20 22:58:05 +08:00
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#include "ice_devids.h"
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#include "ice_type.h"
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2018-03-20 22:58:10 +08:00
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#include "ice_txrx.h"
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ice: Get switch config, scheduler config and device capabilities
This patch adds to the initialization flow by getting switch
configuration, scheduler configuration and device capabilities.
Switch configuration:
On boot, an L2 switch element is created in the firmware per physical
function. Each physical function is also mapped to a port, to which its
switch element is connected. In other words, this switch can be visualized
as an embedded vSwitch that can connect a physical function's virtual
station interfaces (VSIs) to the egress/ingress port. Egress/ingress
filters will be eventually created and applied on this switch element.
As part of the initialization flow, the driver gets configuration data
from this switch element and stores it.
Scheduler configuration:
The Tx scheduler is a subsystem responsible for setting and enforcing QoS.
As part of the initialization flow, the driver queries and stores the
default scheduler configuration for the given physical function.
Device capabilities:
As part of initialization, the driver has to determine what the device is
capable of (ex. max queues, VSIs, etc). This information is obtained from
the firmware and stored by the driver.
CC: Shannon Nelson <shannon.nelson@oracle.com>
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Acked-by: Shannon Nelson <shannon.nelson@oracle.com>
Tested-by: Tony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2018-03-20 22:58:08 +08:00
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#include "ice_switch.h"
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2018-03-20 22:58:07 +08:00
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#include "ice_common.h"
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ice: Get switch config, scheduler config and device capabilities
This patch adds to the initialization flow by getting switch
configuration, scheduler configuration and device capabilities.
Switch configuration:
On boot, an L2 switch element is created in the firmware per physical
function. Each physical function is also mapped to a port, to which its
switch element is connected. In other words, this switch can be visualized
as an embedded vSwitch that can connect a physical function's virtual
station interfaces (VSIs) to the egress/ingress port. Egress/ingress
filters will be eventually created and applied on this switch element.
As part of the initialization flow, the driver gets configuration data
from this switch element and stores it.
Scheduler configuration:
The Tx scheduler is a subsystem responsible for setting and enforcing QoS.
As part of the initialization flow, the driver queries and stores the
default scheduler configuration for the given physical function.
Device capabilities:
As part of initialization, the driver has to determine what the device is
capable of (ex. max queues, VSIs, etc). This information is obtained from
the firmware and stored by the driver.
CC: Shannon Nelson <shannon.nelson@oracle.com>
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Acked-by: Shannon Nelson <shannon.nelson@oracle.com>
Tested-by: Tony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2018-03-20 22:58:08 +08:00
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#include "ice_sched.h"
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2018-03-20 22:58:05 +08:00
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2018-03-20 22:58:16 +08:00
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extern const char ice_drv_ver[];
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2018-03-20 22:58:05 +08:00
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#define ICE_BAR0 0
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#define ICE_DFLT_NUM_DESC 128
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#define ICE_MIN_NUM_DESC 8
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#define ICE_MAX_NUM_DESC 8160
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2018-03-20 22:58:11 +08:00
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#define ICE_REQ_DESC_MULTIPLE 32
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2018-03-20 22:58:17 +08:00
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#define ICE_DFLT_TRAFFIC_CLASS BIT(0)
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2018-03-20 22:58:10 +08:00
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#define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16)
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2018-03-20 22:58:16 +08:00
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#define ICE_ETHTOOL_FWVER_LEN 32
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2018-03-20 22:58:07 +08:00
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#define ICE_AQ_LEN 64
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2018-03-20 22:58:10 +08:00
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#define ICE_MIN_MSIX 2
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2018-03-20 22:58:11 +08:00
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#define ICE_NO_VSI 0xffff
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#define ICE_MAX_VSI_ALLOC 130
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#define ICE_MAX_TXQS 2048
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#define ICE_MAX_RXQS 2048
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#define ICE_VSI_MAP_CONTIG 0
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#define ICE_VSI_MAP_SCATTER 1
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#define ICE_MAX_SCATTER_TXQS 16
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#define ICE_MAX_SCATTER_RXQS 16
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2018-03-20 22:58:13 +08:00
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#define ICE_Q_WAIT_RETRY_LIMIT 10
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#define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT)
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2018-03-20 22:58:15 +08:00
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#define ICE_MAX_LG_RSS_QS 256
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#define ICE_MAX_SMALL_RSS_QS 8
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2018-03-20 22:58:10 +08:00
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#define ICE_RES_VALID_BIT 0x8000
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#define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1)
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#define ICE_INVAL_Q_INDEX 0xffff
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2018-03-20 22:58:05 +08:00
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2018-03-20 22:58:16 +08:00
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#define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4)
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2018-03-20 22:58:05 +08:00
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#define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
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2018-03-20 22:58:11 +08:00
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#define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \
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ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
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#define ICE_UP_TABLE_TRANSLATE(val, i) \
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(((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
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ICE_AQ_VSI_UP_TABLE_UP##i##_M)
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2018-03-20 22:58:14 +08:00
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#define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
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2018-03-20 22:58:13 +08:00
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#define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
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2018-03-20 22:58:15 +08:00
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#define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
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2018-03-20 22:58:13 +08:00
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#define ice_for_each_txq(vsi, i) \
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for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
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#define ice_for_each_rxq(vsi, i) \
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for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
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2018-03-20 22:58:11 +08:00
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struct ice_tc_info {
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u16 qoffset;
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u16 qcount;
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};
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struct ice_tc_cfg {
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u8 numtc; /* Total number of enabled TCs */
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u8 ena_tc; /* TX map */
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struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
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};
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2018-03-20 22:58:10 +08:00
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struct ice_res_tracker {
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u16 num_entries;
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u16 search_hint;
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u16 list[1];
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};
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struct ice_sw {
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struct ice_pf *pf;
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u16 sw_id; /* switch ID for this switch */
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u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */
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};
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2018-03-20 22:58:05 +08:00
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enum ice_state {
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__ICE_DOWN,
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__ICE_PFR_REQ, /* set by driver and peers */
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__ICE_ADMINQ_EVENT_PENDING,
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2018-03-20 22:58:16 +08:00
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__ICE_CFG_BUSY,
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__ICE_SERVICE_SCHED,
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__ICE_STATE_NBITS /* must be last */
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};
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2018-03-20 22:58:10 +08:00
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/* struct that defines a VSI, associated with a dev */
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struct ice_vsi {
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struct net_device *netdev;
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2018-03-20 22:58:11 +08:00
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struct ice_sw *vsw; /* switch this VSI is on */
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struct ice_pf *back; /* back pointer to PF */
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2018-03-20 22:58:10 +08:00
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struct ice_port_info *port_info; /* back pointer to port_info */
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2018-03-20 22:58:11 +08:00
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struct ice_ring **rx_rings; /* rx ring array */
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struct ice_ring **tx_rings; /* tx ring array */
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struct ice_q_vector **q_vectors; /* q_vector array */
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2018-03-20 22:58:13 +08:00
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irqreturn_t (*irq_handler)(int irq, void *data);
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2018-03-20 22:58:16 +08:00
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u64 tx_linearize;
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2018-03-20 22:58:11 +08:00
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DECLARE_BITMAP(state, __ICE_STATE_NBITS);
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2018-03-20 22:58:15 +08:00
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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2018-03-20 22:58:16 +08:00
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u32 tx_restart;
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u32 tx_busy;
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u32 rx_buf_failed;
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u32 rx_page_failed;
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2018-03-20 22:58:11 +08:00
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int num_q_vectors;
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int base_vector;
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enum ice_vsi_type type;
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2018-03-20 22:58:10 +08:00
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u16 vsi_num; /* HW (absolute) index of this VSI */
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u16 idx; /* software index in pf->vsi[] */
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/* Interrupt thresholds */
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u16 work_lmt;
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2018-03-20 22:58:15 +08:00
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/* RSS config */
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u16 rss_table_size; /* HW RSS table size */
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u16 rss_size; /* Allocated RSS queues */
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u8 *rss_hkey_user; /* User configured hash keys */
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u8 *rss_lut_user; /* User configured lookup table entries */
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u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */
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2018-03-20 22:58:13 +08:00
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u16 max_frame;
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u16 rx_buf_len;
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2018-03-20 22:58:11 +08:00
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struct ice_aqc_vsi_props info; /* VSI properties */
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2018-03-20 22:58:16 +08:00
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/* VSI stats */
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struct rtnl_link_stats64 net_stats;
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struct ice_eth_stats eth_stats;
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struct ice_eth_stats eth_stats_prev;
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2018-03-20 22:58:13 +08:00
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bool irqs_ready;
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bool current_isup; /* Sync 'link up' logging */
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2018-03-20 22:58:16 +08:00
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bool stat_offsets_loaded;
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2018-03-20 22:58:13 +08:00
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2018-03-20 22:58:11 +08:00
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/* queue information */
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u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
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u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
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u16 txq_map[ICE_MAX_TXQS]; /* index in pf->avail_txqs */
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u16 rxq_map[ICE_MAX_RXQS]; /* index in pf->avail_rxqs */
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u16 alloc_txq; /* Allocated Tx queues */
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u16 num_txq; /* Used Tx queues */
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u16 alloc_rxq; /* Allocated Rx queues */
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u16 num_rxq; /* Used Rx queues */
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u16 num_desc;
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struct ice_tc_cfg tc_cfg;
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} ____cacheline_internodealigned_in_smp;
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/* struct that defines an interrupt vector */
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struct ice_q_vector {
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struct ice_vsi *vsi;
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cpumask_t affinity_mask;
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struct napi_struct napi;
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struct ice_ring_container rx;
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struct ice_ring_container tx;
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2018-03-20 22:58:13 +08:00
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struct irq_affinity_notify affinity_notify;
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2018-03-20 22:58:11 +08:00
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u16 v_idx; /* index in the vsi->q_vector array. */
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u8 num_ring_tx; /* total number of tx rings in vector */
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u8 num_ring_rx; /* total number of rx rings in vector */
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2018-03-20 22:58:13 +08:00
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char name[ICE_INT_NAME_STR_LEN];
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2018-03-20 22:58:10 +08:00
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} ____cacheline_internodealigned_in_smp;
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enum ice_pf_flags {
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ICE_FLAG_MSIX_ENA,
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ICE_FLAG_FLTR_SYNC,
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ICE_FLAG_RSS_ENA,
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ICE_PF_FLAGS_NBITS /* must be last */
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};
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2018-03-20 22:58:05 +08:00
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struct ice_pf {
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struct pci_dev *pdev;
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2018-03-20 22:58:10 +08:00
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struct msix_entry *msix_entries;
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struct ice_res_tracker *irq_tracker;
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struct ice_vsi **vsi; /* VSIs created by the driver */
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struct ice_sw *first_sw; /* first switch created by firmware */
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2018-03-20 22:58:05 +08:00
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DECLARE_BITMAP(state, __ICE_STATE_NBITS);
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2018-03-20 22:58:10 +08:00
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DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS);
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DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS);
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DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS);
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unsigned long serv_tmr_period;
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unsigned long serv_tmr_prev;
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struct timer_list serv_tmr;
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struct work_struct serv_task;
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struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */
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struct mutex sw_mutex; /* lock for protecting VSI alloc flow */
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2018-03-20 22:58:05 +08:00
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u32 msg_enable;
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2018-03-20 22:58:15 +08:00
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u32 hw_csum_rx_error;
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2018-03-20 22:58:10 +08:00
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u32 oicr_idx; /* Other interrupt cause vector index */
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u32 num_lan_msix; /* Total MSIX vectors for base driver */
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u32 num_avail_msix; /* remaining MSIX vectors left unclaimed */
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u16 num_lan_tx; /* num lan tx queues setup */
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u16 num_lan_rx; /* num lan rx queues setup */
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u16 q_left_tx; /* remaining num tx queues left unclaimed */
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u16 q_left_rx; /* remaining num rx queues left unclaimed */
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u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */
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u16 num_alloc_vsi;
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2018-03-20 22:58:16 +08:00
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struct ice_hw_port_stats stats;
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struct ice_hw_port_stats stats_prev;
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2018-03-20 22:58:05 +08:00
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struct ice_hw hw;
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2018-03-20 22:58:16 +08:00
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bool stat_prev_loaded; /* has previous stats been loaded */
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2018-03-20 22:58:10 +08:00
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char int_name[ICE_INT_NAME_STR_LEN];
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2018-03-20 22:58:05 +08:00
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};
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2018-03-20 22:58:10 +08:00
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2018-03-20 22:58:11 +08:00
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struct ice_netdev_priv {
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struct ice_vsi *vsi;
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};
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2018-03-20 22:58:10 +08:00
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/**
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* ice_irq_dynamic_ena - Enable default interrupt generation settings
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* @hw: pointer to hw struct
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2018-03-20 22:58:13 +08:00
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* @vsi: pointer to vsi struct, can be NULL
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* @q_vector: pointer to q_vector, can be NULL
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2018-03-20 22:58:10 +08:00
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*/
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2018-03-20 22:58:13 +08:00
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static inline void ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,
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struct ice_q_vector *q_vector)
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2018-03-20 22:58:10 +08:00
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{
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2018-03-20 22:58:13 +08:00
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u32 vector = (vsi && q_vector) ? vsi->base_vector + q_vector->v_idx :
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((struct ice_pf *)hw->back)->oicr_idx;
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2018-03-20 22:58:10 +08:00
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int itr = ICE_ITR_NONE;
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u32 val;
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/* clear the PBA here, as this function is meant to clean out all
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* previous interrupts and enable the interrupt
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*/
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val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
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(itr << GLINT_DYN_CTL_ITR_INDX_S);
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2018-03-20 22:58:13 +08:00
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if (vsi)
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if (test_bit(__ICE_DOWN, vsi->state))
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return;
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2018-03-20 22:58:10 +08:00
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wr32(hw, GLINT_DYN_CTL(vector), val);
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}
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2018-03-20 22:58:13 +08:00
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2018-03-20 22:58:17 +08:00
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static inline void ice_vsi_set_tc_cfg(struct ice_vsi *vsi)
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{
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vsi->tc_cfg.ena_tc = ICE_DFLT_TRAFFIC_CLASS;
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vsi->tc_cfg.numtc = 1;
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}
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2018-03-20 22:58:16 +08:00
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void ice_set_ethtool_ops(struct net_device *netdev);
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int ice_up(struct ice_vsi *vsi);
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int ice_down(struct ice_vsi *vsi);
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2018-03-20 22:58:15 +08:00
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int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
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int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
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void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
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2018-03-20 22:58:16 +08:00
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void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
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2018-03-20 22:58:15 +08:00
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2018-03-20 22:58:05 +08:00
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#endif /* _ICE_H_ */
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