2005-09-26 14:04:21 +08:00
|
|
|
/*
|
|
|
|
|
* PowerPC version
|
|
|
|
|
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
|
|
|
|
|
* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
|
|
|
|
|
* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
|
|
|
|
|
* Low-level exception handlers and MMU support
|
|
|
|
|
* rewritten by Paul Mackerras.
|
|
|
|
|
* Copyright (C) 1996 Paul Mackerras.
|
|
|
|
|
* MPC8xx modifications by Dan Malek
|
|
|
|
|
* Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
|
|
|
|
|
*
|
|
|
|
|
* This file contains low-level support and setup for PowerPC 8xx
|
|
|
|
|
* embedded processors, including trap and interrupt dispatch.
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
|
* modify it under the terms of the GNU General Public License
|
|
|
|
|
* as published by the Free Software Foundation; either version
|
|
|
|
|
* 2 of the License, or (at your option) any later version.
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
|
2009-04-26 10:11:05 +08:00
|
|
|
#include <linux/init.h>
|
2005-09-26 14:04:21 +08:00
|
|
|
#include <asm/processor.h>
|
|
|
|
|
#include <asm/page.h>
|
|
|
|
|
#include <asm/mmu.h>
|
|
|
|
|
#include <asm/cache.h>
|
|
|
|
|
#include <asm/pgtable.h>
|
|
|
|
|
#include <asm/cputable.h>
|
|
|
|
|
#include <asm/thread_info.h>
|
|
|
|
|
#include <asm/ppc_asm.h>
|
|
|
|
|
#include <asm/asm-offsets.h>
|
2010-11-18 23:06:17 +08:00
|
|
|
#include <asm/ptrace.h>
|
2016-01-14 12:33:46 +08:00
|
|
|
#include <asm/export.h>
|
2018-10-19 14:55:06 +08:00
|
|
|
#include <asm/code-patching-asm.h>
|
2005-09-26 14:04:21 +08:00
|
|
|
|
2015-04-20 13:54:46 +08:00
|
|
|
#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
|
2017-07-12 18:08:47 +08:00
|
|
|
/* By simply checking Address >= 0x80000000, we know if its a kernel address */
|
|
|
|
|
#define SIMPLE_KERNEL_ADDRESS 1
|
2015-04-20 13:54:46 +08:00
|
|
|
#endif
|
|
|
|
|
|
2017-07-12 18:08:51 +08:00
|
|
|
/*
|
|
|
|
|
* We need an ITLB miss handler for kernel addresses if:
|
|
|
|
|
* - Either we have modules
|
|
|
|
|
* - Or we have not pinned the first 8M
|
|
|
|
|
*/
|
|
|
|
|
#if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
|
|
|
|
|
defined(CONFIG_DEBUG_PAGEALLOC)
|
|
|
|
|
#define ITLB_MISS_KERNEL 1
|
|
|
|
|
#endif
|
2015-04-20 13:54:46 +08:00
|
|
|
|
2014-09-19 16:36:09 +08:00
|
|
|
/*
|
|
|
|
|
* Value for the bits that have fixed value in RPN entries.
|
|
|
|
|
* Also used for tagging DAR for DTLBerror.
|
|
|
|
|
*/
|
|
|
|
|
#define RPN_PATTERN 0x00f0
|
|
|
|
|
|
2016-12-07 15:47:28 +08:00
|
|
|
#define PAGE_SHIFT_512K 19
|
|
|
|
|
#define PAGE_SHIFT_8M 23
|
|
|
|
|
|
2009-04-26 10:11:05 +08:00
|
|
|
__HEAD
|
2007-09-14 04:42:35 +08:00
|
|
|
_ENTRY(_stext);
|
|
|
|
|
_ENTRY(_start);
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* MPC8xx
|
|
|
|
|
* This port was done on an MBX board with an 860. Right now I only
|
|
|
|
|
* support an ELF compressed (zImage) boot from EPPC-Bug because the
|
|
|
|
|
* code there loads up some registers before calling us:
|
|
|
|
|
* r3: ptr to board info data
|
|
|
|
|
* r4: initrd_start or if no initrd then 0
|
|
|
|
|
* r5: initrd_end - unused if r4 is 0
|
|
|
|
|
* r6: Start of command line string
|
|
|
|
|
* r7: End of command line string
|
|
|
|
|
*
|
|
|
|
|
* I decided to use conditional compilation instead of checking PVR and
|
|
|
|
|
* adding more processor specific branches around code I don't need.
|
|
|
|
|
* Since this is an embedded processor, I also appreciate any memory
|
|
|
|
|
* savings I can get.
|
|
|
|
|
*
|
|
|
|
|
* The MPC8xx does not have any BATs, but it supports large page sizes.
|
|
|
|
|
* We first initialize the MMU to support 8M byte pages, then load one
|
|
|
|
|
* entry into each of the instruction and data TLBs to map the first
|
|
|
|
|
* 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
|
|
|
|
|
* the "internal" processor registers before MMU_init is called.
|
|
|
|
|
*
|
|
|
|
|
* -- Dan
|
|
|
|
|
*/
|
|
|
|
|
.globl __start
|
|
|
|
|
__start:
|
2011-07-25 19:29:33 +08:00
|
|
|
mr r31,r3 /* save device tree ptr */
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* We have to turn on the MMU right away so we get cache modes
|
|
|
|
|
* set correctly.
|
|
|
|
|
*/
|
|
|
|
|
bl initial_mmu
|
|
|
|
|
|
|
|
|
|
/* We now have the lower 8 Meg mapped into TLB entries, and the caches
|
|
|
|
|
* ready to work.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
turn_on_mmu:
|
|
|
|
|
mfmsr r0
|
|
|
|
|
ori r0,r0,MSR_DR|MSR_IR
|
|
|
|
|
mtspr SPRN_SRR1,r0
|
|
|
|
|
lis r0,start_here@h
|
|
|
|
|
ori r0,r0,start_here@l
|
|
|
|
|
mtspr SPRN_SRR0,r0
|
|
|
|
|
rfi /* enables MMU */
|
|
|
|
|
|
2018-11-29 22:07:11 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PERF_EVENTS
|
|
|
|
|
.align 4
|
|
|
|
|
|
|
|
|
|
.globl itlb_miss_counter
|
|
|
|
|
itlb_miss_counter:
|
|
|
|
|
.space 4
|
|
|
|
|
|
|
|
|
|
.globl dtlb_miss_counter
|
|
|
|
|
dtlb_miss_counter:
|
|
|
|
|
.space 4
|
|
|
|
|
|
|
|
|
|
.globl instruction_counter
|
|
|
|
|
instruction_counter:
|
|
|
|
|
.space 4
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-09-26 14:04:21 +08:00
|
|
|
/*
|
|
|
|
|
* Exception entry code. This code runs with address translation
|
|
|
|
|
* turned off, i.e. using physical addresses.
|
|
|
|
|
* We assume sprg3 has the physical address of the current
|
|
|
|
|
* task's thread_struct.
|
|
|
|
|
*/
|
|
|
|
|
#define EXCEPTION_PROLOG \
|
2018-01-12 20:45:21 +08:00
|
|
|
mtspr SPRN_SPRG_SCRATCH0, r10; \
|
|
|
|
|
mtspr SPRN_SPRG_SCRATCH1, r11; \
|
2015-04-20 13:54:40 +08:00
|
|
|
mfcr r10; \
|
2005-09-26 14:04:21 +08:00
|
|
|
EXCEPTION_PROLOG_1; \
|
|
|
|
|
EXCEPTION_PROLOG_2
|
|
|
|
|
|
|
|
|
|
#define EXCEPTION_PROLOG_1 \
|
|
|
|
|
mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
|
|
|
|
|
andi. r11,r11,MSR_PR; \
|
|
|
|
|
tophys(r11,r1); /* use tophys(r1) if kernel */ \
|
|
|
|
|
beq 1f; \
|
2009-07-15 04:52:54 +08:00
|
|
|
mfspr r11,SPRN_SPRG_THREAD; \
|
2005-09-26 14:04:21 +08:00
|
|
|
lwz r11,THREAD_INFO-THREAD(r11); \
|
|
|
|
|
addi r11,r11,THREAD_SIZE; \
|
|
|
|
|
tophys(r11,r11); \
|
|
|
|
|
1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#define EXCEPTION_PROLOG_2 \
|
|
|
|
|
stw r10,_CCR(r11); /* save registers */ \
|
|
|
|
|
stw r12,GPR12(r11); \
|
|
|
|
|
stw r9,GPR9(r11); \
|
2009-07-15 04:52:54 +08:00
|
|
|
mfspr r10,SPRN_SPRG_SCRATCH0; \
|
2005-09-26 14:04:21 +08:00
|
|
|
stw r10,GPR10(r11); \
|
2009-07-15 04:52:54 +08:00
|
|
|
mfspr r12,SPRN_SPRG_SCRATCH1; \
|
2005-09-26 14:04:21 +08:00
|
|
|
stw r12,GPR11(r11); \
|
|
|
|
|
mflr r10; \
|
|
|
|
|
stw r10,_LINK(r11); \
|
|
|
|
|
mfspr r12,SPRN_SRR0; \
|
|
|
|
|
mfspr r9,SPRN_SRR1; \
|
|
|
|
|
stw r1,GPR1(r11); \
|
|
|
|
|
stw r1,0(r11); \
|
|
|
|
|
tovirt(r1,r11); /* set new kernel sp */ \
|
|
|
|
|
li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
|
2017-08-08 19:59:02 +08:00
|
|
|
mtmsr r10; \
|
2005-09-26 14:04:21 +08:00
|
|
|
stw r0,GPR0(r11); \
|
|
|
|
|
SAVE_4GPRS(3, r11); \
|
|
|
|
|
SAVE_2GPRS(7, r11)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Note: code which follows this uses cr0.eq (set if from kernel),
|
|
|
|
|
* r11, r12 (SRR0), and r9 (SRR1).
|
|
|
|
|
*
|
|
|
|
|
* Note2: once we have set r1 we are in a position to take exceptions
|
|
|
|
|
* again, and we could thus set MSR:RI at that point.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Exception vectors.
|
|
|
|
|
*/
|
|
|
|
|
#define EXCEPTION(n, label, hdlr, xfer) \
|
|
|
|
|
. = n; \
|
|
|
|
|
label: \
|
|
|
|
|
EXCEPTION_PROLOG; \
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
|
|
|
|
xfer(n, hdlr)
|
|
|
|
|
|
|
|
|
|
#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
|
|
|
|
|
li r10,trap; \
|
2005-10-28 20:45:25 +08:00
|
|
|
stw r10,_TRAP(r11); \
|
2005-09-26 14:04:21 +08:00
|
|
|
li r10,MSR_KERNEL; \
|
|
|
|
|
copyee(r10, r9); \
|
|
|
|
|
bl tfer; \
|
|
|
|
|
i##n: \
|
|
|
|
|
.long hdlr; \
|
|
|
|
|
.long ret
|
|
|
|
|
|
|
|
|
|
#define COPY_EE(d, s) rlwimi d,s,0,16,16
|
|
|
|
|
#define NOCOPY(d, s)
|
|
|
|
|
|
|
|
|
|
#define EXC_XFER_STD(n, hdlr) \
|
|
|
|
|
EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
|
|
|
|
|
ret_from_except_full)
|
|
|
|
|
|
|
|
|
|
#define EXC_XFER_LITE(n, hdlr) \
|
|
|
|
|
EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
|
|
|
|
|
ret_from_except)
|
|
|
|
|
|
|
|
|
|
#define EXC_XFER_EE(n, hdlr) \
|
|
|
|
|
EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
|
|
|
|
|
ret_from_except_full)
|
|
|
|
|
|
|
|
|
|
#define EXC_XFER_EE_LITE(n, hdlr) \
|
|
|
|
|
EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
|
|
|
|
|
ret_from_except)
|
|
|
|
|
|
|
|
|
|
/* System reset */
|
2016-09-05 14:42:31 +08:00
|
|
|
EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* Machine check */
|
|
|
|
|
. = 0x200
|
|
|
|
|
MachineCheck:
|
|
|
|
|
EXCEPTION_PROLOG
|
|
|
|
|
mfspr r4,SPRN_DAR
|
|
|
|
|
stw r4,_DAR(r11)
|
2014-09-19 16:36:09 +08:00
|
|
|
li r5,RPN_PATTERN
|
2009-11-20 08:21:04 +08:00
|
|
|
mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
|
2005-09-26 14:04:21 +08:00
|
|
|
mfspr r5,SPRN_DSISR
|
|
|
|
|
stw r5,_DSISR(r11)
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
2005-10-01 16:43:42 +08:00
|
|
|
EXC_XFER_STD(0x200, machine_check_exception)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* Data access exception.
|
2014-09-19 16:36:07 +08:00
|
|
|
* This is "never generated" by the MPC8xx.
|
2005-09-26 14:04:21 +08:00
|
|
|
*/
|
|
|
|
|
. = 0x300
|
|
|
|
|
DataAccess:
|
|
|
|
|
|
|
|
|
|
/* Instruction access exception.
|
2014-09-19 16:36:06 +08:00
|
|
|
* This is "never generated" by the MPC8xx.
|
2005-09-26 14:04:21 +08:00
|
|
|
*/
|
|
|
|
|
. = 0x400
|
|
|
|
|
InstructionAccess:
|
|
|
|
|
|
|
|
|
|
/* External interrupt */
|
|
|
|
|
EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
|
|
|
|
|
|
|
|
|
|
/* Alignment exception */
|
|
|
|
|
. = 0x600
|
|
|
|
|
Alignment:
|
|
|
|
|
EXCEPTION_PROLOG
|
|
|
|
|
mfspr r4,SPRN_DAR
|
|
|
|
|
stw r4,_DAR(r11)
|
2014-09-19 16:36:09 +08:00
|
|
|
li r5,RPN_PATTERN
|
2009-11-20 08:21:04 +08:00
|
|
|
mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
|
2005-09-26 14:04:21 +08:00
|
|
|
mfspr r5,SPRN_DSISR
|
|
|
|
|
stw r5,_DSISR(r11)
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
2005-10-01 16:43:42 +08:00
|
|
|
EXC_XFER_EE(0x600, alignment_exception)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* Program check exception */
|
2005-10-01 16:43:42 +08:00
|
|
|
EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* No FPU on MPC8xx. This exception is not supposed to happen.
|
|
|
|
|
*/
|
2005-10-01 16:43:42 +08:00
|
|
|
EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* Decrementer */
|
|
|
|
|
EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
|
|
|
|
|
|
2005-10-01 16:43:42 +08:00
|
|
|
EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
|
|
|
|
|
EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* System call */
|
|
|
|
|
. = 0xc00
|
|
|
|
|
SystemCall:
|
|
|
|
|
EXCEPTION_PROLOG
|
|
|
|
|
EXC_XFER_EE_LITE(0xc00, DoSyscall)
|
|
|
|
|
|
|
|
|
|
/* Single step - not used on 601 */
|
2005-10-01 16:43:42 +08:00
|
|
|
EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
|
|
|
|
|
EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
|
|
|
|
|
EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* On the MPC8xx, this is a software emulation interrupt. It occurs
|
|
|
|
|
* for all unimplemented and illegal instructions.
|
|
|
|
|
*/
|
2017-08-08 19:58:44 +08:00
|
|
|
EXCEPTION(0x1000, SoftEmu, program_check_exception, EXC_XFER_STD)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
. = 0x1100
|
|
|
|
|
/*
|
|
|
|
|
* For the MPC8xx, this is a software tablewalk to load the instruction
|
2018-11-29 22:07:15 +08:00
|
|
|
* TLB. The task switch loads the M_TWB register with the pointer to the first
|
2014-09-19 16:36:08 +08:00
|
|
|
* level table.
|
2005-09-26 14:04:21 +08:00
|
|
|
* If we discover there is no second level table (value is zero) or if there
|
|
|
|
|
* is an invalid pte, we load that into the TLB, which causes another fault
|
|
|
|
|
* into the TLB Error interrupt where we can handle such problems.
|
|
|
|
|
* We have to use the MD_xxx registers for the tablewalk because the
|
|
|
|
|
* equivalent MI_xxx registers only perform the attribute functions.
|
|
|
|
|
*/
|
2015-04-20 13:54:38 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_8xx_CPU15
|
|
|
|
|
#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
|
|
|
|
|
addi tmp, addr, PAGE_SIZE; \
|
|
|
|
|
tlbie tmp; \
|
|
|
|
|
addi tmp, addr, -PAGE_SIZE; \
|
|
|
|
|
tlbie tmp
|
|
|
|
|
#else
|
|
|
|
|
#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-09-26 14:04:21 +08:00
|
|
|
InstructionTLBMiss:
|
2018-01-12 20:45:21 +08:00
|
|
|
mtspr SPRN_SPRG_SCRATCH0, r10
|
|
|
|
|
mtspr SPRN_SPRG_SCRATCH1, r11
|
2018-11-29 22:07:13 +08:00
|
|
|
#ifdef ITLB_MISS_KERNEL
|
2018-01-12 20:45:21 +08:00
|
|
|
mtspr SPRN_SPRG_SCRATCH2, r12
|
2005-09-26 14:04:21 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* If we are faulting a kernel address, we have to use the
|
|
|
|
|
* kernel page tables.
|
|
|
|
|
*/
|
2016-09-16 14:42:04 +08:00
|
|
|
mfspr r10, SPRN_SRR0 /* Get effective address of fault */
|
|
|
|
|
INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
|
2018-11-29 22:07:15 +08:00
|
|
|
mtspr SPRN_MD_EPN, r10
|
2010-03-02 13:37:10 +08:00
|
|
|
/* Only modules will cause ITLB Misses as we always
|
|
|
|
|
* pin the first 8MB of kernel memory */
|
2017-07-12 18:08:51 +08:00
|
|
|
#ifdef ITLB_MISS_KERNEL
|
2018-11-29 22:07:13 +08:00
|
|
|
mfcr r12
|
2017-07-12 18:08:51 +08:00
|
|
|
#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
|
2017-07-12 18:08:47 +08:00
|
|
|
andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
|
|
|
|
|
#else
|
|
|
|
|
rlwinm r11, r10, 16, 0xfff8
|
|
|
|
|
cmpli cr0, r11, PAGE_OFFSET@h
|
2017-07-12 18:08:51 +08:00
|
|
|
#ifndef CONFIG_PIN_TLB_TEXT
|
|
|
|
|
/* It is assumed that kernel code fits into the first 8M page */
|
2018-10-19 14:55:06 +08:00
|
|
|
0: cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h
|
|
|
|
|
patch_site 0b, patch__itlbmiss_linmem_top
|
2017-07-12 18:08:51 +08:00
|
|
|
#endif
|
2017-07-12 18:08:47 +08:00
|
|
|
#endif
|
2016-09-16 14:42:04 +08:00
|
|
|
#endif
|
2018-11-29 22:07:15 +08:00
|
|
|
mfspr r11, SPRN_M_TWB /* Get level 1 table */
|
2017-07-12 18:08:51 +08:00
|
|
|
#ifdef ITLB_MISS_KERNEL
|
|
|
|
|
#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
|
2017-07-12 18:08:47 +08:00
|
|
|
beq+ 3f
|
|
|
|
|
#else
|
|
|
|
|
blt+ 3f
|
2017-07-12 18:08:51 +08:00
|
|
|
#endif
|
|
|
|
|
#ifndef CONFIG_PIN_TLB_TEXT
|
|
|
|
|
blt cr7, ITLBMissLinear
|
2017-07-12 18:08:47 +08:00
|
|
|
#endif
|
2018-11-29 22:07:15 +08:00
|
|
|
rlwinm r11, r11, 0, 20, 31
|
|
|
|
|
oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
|
2005-09-26 14:04:21 +08:00
|
|
|
3:
|
2010-03-02 13:37:10 +08:00
|
|
|
#endif
|
2015-01-20 17:57:34 +08:00
|
|
|
lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
|
2005-09-26 14:04:21 +08:00
|
|
|
|
2018-11-29 22:07:15 +08:00
|
|
|
mtspr SPRN_MD_TWC, r11
|
|
|
|
|
mfspr r10, SPRN_MD_TWC
|
2015-04-22 18:06:43 +08:00
|
|
|
lwz r10, 0(r10) /* Get the pte */
|
2018-11-29 22:07:13 +08:00
|
|
|
#ifdef ITLB_MISS_KERNEL
|
2018-01-12 20:45:21 +08:00
|
|
|
mtcr r12
|
2016-12-07 15:47:28 +08:00
|
|
|
#endif
|
2018-01-12 20:45:33 +08:00
|
|
|
/* Load the MI_TWC with the attributes for this "segment." */
|
|
|
|
|
mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
|
|
|
|
|
|
2018-10-19 14:54:54 +08:00
|
|
|
#ifdef CONFIG_SWAP
|
|
|
|
|
rlwinm r11, r10, 32-5, _PAGE_PRESENT
|
|
|
|
|
and r11, r11, r10
|
|
|
|
|
rlwimi r10, r11, 0, _PAGE_PRESENT
|
|
|
|
|
#endif
|
2018-01-12 20:45:31 +08:00
|
|
|
li r11, RPN_PATTERN | 0x200
|
2005-09-26 14:04:21 +08:00
|
|
|
/* The Linux PTE won't go exactly into the MMU TLB.
|
2018-01-12 20:45:31 +08:00
|
|
|
* Software indicator bits 20 and 23 must be clear.
|
|
|
|
|
* Software indicator bits 22, 24, 25, 26, and 27 must be
|
2005-09-26 14:04:21 +08:00
|
|
|
* set. All other Linux PTE bits control the behavior
|
|
|
|
|
* of the MMU.
|
|
|
|
|
*/
|
2018-01-12 20:45:31 +08:00
|
|
|
rlwimi r11, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
|
|
|
|
|
rlwimi r10, r11, 0, 0x0ff0 /* Set 22, 24-27, clear 20,23 */
|
2018-01-12 20:45:19 +08:00
|
|
|
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
|
2005-09-26 14:04:21 +08:00
|
|
|
|
2010-03-02 13:37:12 +08:00
|
|
|
/* Restore registers */
|
2018-10-19 14:55:08 +08:00
|
|
|
0: mfspr r10, SPRN_SPRG_SCRATCH0
|
2018-01-12 20:45:23 +08:00
|
|
|
mfspr r11, SPRN_SPRG_SCRATCH1
|
2018-11-29 22:07:13 +08:00
|
|
|
#ifdef ITLB_MISS_KERNEL
|
2018-01-12 20:45:23 +08:00
|
|
|
mfspr r12, SPRN_SPRG_SCRATCH2
|
|
|
|
|
#endif
|
|
|
|
|
rfi
|
2018-10-19 14:55:08 +08:00
|
|
|
patch_site 0b, patch__itlbmiss_exit_1
|
|
|
|
|
|
2018-01-12 20:45:23 +08:00
|
|
|
#ifdef CONFIG_PERF_EVENTS
|
2018-10-19 14:55:08 +08:00
|
|
|
patch_site 0f, patch__itlbmiss_perf
|
2018-11-29 22:07:11 +08:00
|
|
|
0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
|
|
|
|
|
addi r10, r10, 1
|
|
|
|
|
stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
|
2018-01-12 20:45:21 +08:00
|
|
|
mfspr r10, SPRN_SPRG_SCRATCH0
|
|
|
|
|
mfspr r11, SPRN_SPRG_SCRATCH1
|
2018-11-29 22:07:13 +08:00
|
|
|
#ifdef ITLB_MISS_KERNEL
|
2018-01-12 20:45:21 +08:00
|
|
|
mfspr r12, SPRN_SPRG_SCRATCH2
|
2005-09-26 14:04:21 +08:00
|
|
|
#endif
|
|
|
|
|
rfi
|
2018-11-29 22:07:11 +08:00
|
|
|
#endif
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
. = 0x1200
|
|
|
|
|
DataStoreTLBMiss:
|
2018-01-12 20:45:21 +08:00
|
|
|
mtspr SPRN_SPRG_SCRATCH0, r10
|
|
|
|
|
mtspr SPRN_SPRG_SCRATCH1, r11
|
|
|
|
|
mtspr SPRN_SPRG_SCRATCH2, r12
|
|
|
|
|
mfcr r12
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* If we are faulting a kernel address, we have to use the
|
|
|
|
|
* kernel page tables.
|
|
|
|
|
*/
|
2016-09-16 14:42:08 +08:00
|
|
|
mfspr r10, SPRN_MD_EPN
|
2017-07-12 18:08:57 +08:00
|
|
|
rlwinm r11, r10, 16, 0xfff8
|
|
|
|
|
cmpli cr0, r11, PAGE_OFFSET@h
|
2018-11-29 22:07:15 +08:00
|
|
|
mfspr r11, SPRN_M_TWB /* Get level 1 table */
|
2016-09-16 14:42:08 +08:00
|
|
|
blt+ 3f
|
2017-07-12 18:08:57 +08:00
|
|
|
rlwinm r11, r10, 16, 0xfff8
|
2016-05-17 15:02:56 +08:00
|
|
|
#ifndef CONFIG_PIN_TLB_IMMR
|
2017-07-12 18:08:57 +08:00
|
|
|
cmpli cr0, r11, VIRT_IMMR_BASE@h
|
2016-05-17 15:02:51 +08:00
|
|
|
#endif
|
2018-10-19 14:55:06 +08:00
|
|
|
0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
|
|
|
|
|
patch_site 0b, patch__dtlbmiss_linmem_top
|
2016-05-17 15:02:56 +08:00
|
|
|
#ifndef CONFIG_PIN_TLB_IMMR
|
2018-10-19 14:55:06 +08:00
|
|
|
0: beq- DTLBMissIMMR
|
|
|
|
|
patch_site 0b, patch__dtlbmiss_immr_jmp
|
2016-05-17 15:02:45 +08:00
|
|
|
#endif
|
2016-09-16 14:42:08 +08:00
|
|
|
blt cr7, DTLBMissLinear
|
2018-11-29 22:07:15 +08:00
|
|
|
mfspr r11, SPRN_M_TWB /* Get level 1 table */
|
|
|
|
|
rlwinm r11, r11, 0, 20, 31
|
|
|
|
|
oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
|
2005-09-26 14:04:21 +08:00
|
|
|
3:
|
2015-01-20 17:57:34 +08:00
|
|
|
lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
|
2005-09-26 14:04:21 +08:00
|
|
|
|
2018-11-29 22:07:15 +08:00
|
|
|
mtspr SPRN_MD_TWC, r11
|
|
|
|
|
mfspr r10, SPRN_MD_TWC
|
2005-09-26 14:04:21 +08:00
|
|
|
lwz r10, 0(r10) /* Get the pte */
|
2018-11-29 22:07:15 +08:00
|
|
|
|
2018-01-12 20:45:21 +08:00
|
|
|
mtcr r12
|
2005-09-26 14:04:21 +08:00
|
|
|
|
2018-01-12 20:45:31 +08:00
|
|
|
/* Insert the Guarded flag into the TWC from the Linux PTE.
|
|
|
|
|
* It is bit 27 of both the Linux PTE and the TWC (at least
|
2005-09-26 14:04:21 +08:00
|
|
|
* I got that right :-). It will be better when we can put
|
|
|
|
|
* this into the Linux pgd/pmd and load it in the operation
|
|
|
|
|
* above.
|
|
|
|
|
*/
|
2018-01-12 20:45:31 +08:00
|
|
|
rlwimi r11, r10, 0, _PAGE_GUARDED
|
2018-01-12 20:45:33 +08:00
|
|
|
mtspr SPRN_MD_TWC, r11
|
|
|
|
|
|
2018-10-19 14:54:54 +08:00
|
|
|
/* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
|
|
|
|
|
* We also need to know if the insn is a load/store, so:
|
|
|
|
|
* Clear _PAGE_PRESENT and load that which will
|
|
|
|
|
* trap into DTLB Error with store bit set accordinly.
|
|
|
|
|
*/
|
|
|
|
|
/* PRESENT=0x1, ACCESSED=0x20
|
|
|
|
|
* r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
|
|
|
|
|
* r10 = (r10 & ~PRESENT) | r11;
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_SWAP
|
|
|
|
|
rlwinm r11, r10, 32-5, _PAGE_PRESENT
|
|
|
|
|
and r11, r11, r10
|
|
|
|
|
rlwimi r10, r11, 0, _PAGE_PRESENT
|
|
|
|
|
#endif
|
2005-09-26 14:04:21 +08:00
|
|
|
/* The Linux PTE won't go exactly into the MMU TLB.
|
|
|
|
|
* Software indicator bits 24, 25, 26, and 27 must be
|
|
|
|
|
* set. All other Linux PTE bits control the behavior
|
|
|
|
|
* of the MMU.
|
|
|
|
|
*/
|
2015-01-20 17:57:33 +08:00
|
|
|
li r11, RPN_PATTERN
|
2016-12-07 15:47:28 +08:00
|
|
|
rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
|
2018-01-12 20:45:19 +08:00
|
|
|
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
|
2005-09-26 14:04:21 +08:00
|
|
|
|
2010-03-02 13:37:12 +08:00
|
|
|
/* Restore registers */
|
2014-08-29 17:14:37 +08:00
|
|
|
mtspr SPRN_DAR, r11 /* Tag DAR */
|
2018-10-19 14:55:08 +08:00
|
|
|
|
|
|
|
|
0: mfspr r10, SPRN_SPRG_SCRATCH0
|
2018-01-12 20:45:23 +08:00
|
|
|
mfspr r11, SPRN_SPRG_SCRATCH1
|
|
|
|
|
mfspr r12, SPRN_SPRG_SCRATCH2
|
|
|
|
|
rfi
|
2018-10-19 14:55:08 +08:00
|
|
|
patch_site 0b, patch__dtlbmiss_exit_1
|
|
|
|
|
|
2018-01-12 20:45:23 +08:00
|
|
|
#ifdef CONFIG_PERF_EVENTS
|
2018-10-19 14:55:08 +08:00
|
|
|
patch_site 0f, patch__dtlbmiss_perf
|
2018-11-29 22:07:11 +08:00
|
|
|
0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
|
|
|
|
|
addi r10, r10, 1
|
|
|
|
|
stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
|
2018-01-12 20:45:21 +08:00
|
|
|
mfspr r10, SPRN_SPRG_SCRATCH0
|
|
|
|
|
mfspr r11, SPRN_SPRG_SCRATCH1
|
|
|
|
|
mfspr r12, SPRN_SPRG_SCRATCH2
|
2005-09-26 14:04:21 +08:00
|
|
|
rfi
|
2018-11-29 22:07:11 +08:00
|
|
|
#endif
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* This is an instruction TLB error on the MPC8xx. This could be due
|
|
|
|
|
* to many reasons, such as executing guarded memory or illegal instruction
|
|
|
|
|
* addresses. There is nothing to do but handle a big time error fault.
|
|
|
|
|
*/
|
|
|
|
|
. = 0x1300
|
|
|
|
|
InstructionTLBError:
|
2015-01-20 17:57:33 +08:00
|
|
|
EXCEPTION_PROLOG
|
2014-09-19 16:36:06 +08:00
|
|
|
mr r4,r12
|
2017-07-19 12:49:28 +08:00
|
|
|
andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
|
|
|
|
|
andis. r10,r9,SRR1_ISI_NOPT@h
|
2014-09-19 16:36:10 +08:00
|
|
|
beq+ 1f
|
|
|
|
|
tlbie r4
|
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 16:52:15 +08:00
|
|
|
itlbie:
|
2014-09-19 16:36:06 +08:00
|
|
|
/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
|
2014-09-19 16:36:10 +08:00
|
|
|
1: EXC_XFER_LITE(0x400, handle_page_fault)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* This is the data TLB error on the MPC8xx. This could be due to
|
2014-08-29 17:14:38 +08:00
|
|
|
* many reasons, including a dirty update to a pte. We bail out to
|
|
|
|
|
* a higher level function that can handle it.
|
2005-09-26 14:04:21 +08:00
|
|
|
*/
|
|
|
|
|
. = 0x1400
|
|
|
|
|
DataTLBError:
|
2018-01-12 20:45:21 +08:00
|
|
|
mtspr SPRN_SPRG_SCRATCH0, r10
|
|
|
|
|
mtspr SPRN_SPRG_SCRATCH1, r11
|
2015-04-20 13:54:40 +08:00
|
|
|
mfcr r10
|
2005-09-26 14:04:21 +08:00
|
|
|
|
2014-08-29 17:14:38 +08:00
|
|
|
mfspr r11, SPRN_DAR
|
2014-09-19 16:36:09 +08:00
|
|
|
cmpwi cr0, r11, RPN_PATTERN
|
2009-11-20 08:21:06 +08:00
|
|
|
beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
|
2014-08-29 17:14:37 +08:00
|
|
|
DARFixed:/* Return from dcbx instruction bug workaround */
|
2014-09-19 16:36:08 +08:00
|
|
|
EXCEPTION_PROLOG_1
|
|
|
|
|
EXCEPTION_PROLOG_2
|
2014-09-19 16:36:10 +08:00
|
|
|
mfspr r5,SPRN_DSISR
|
|
|
|
|
stw r5,_DSISR(r11)
|
2014-09-19 16:36:07 +08:00
|
|
|
mfspr r4,SPRN_DAR
|
2017-08-08 19:59:00 +08:00
|
|
|
andis. r10,r5,DSISR_NOHPTE@h
|
2014-09-19 16:36:10 +08:00
|
|
|
beq+ 1f
|
|
|
|
|
tlbie r4
|
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 16:52:15 +08:00
|
|
|
dtlbie:
|
2014-09-19 16:36:10 +08:00
|
|
|
1: li r10,RPN_PATTERN
|
2014-09-19 16:36:07 +08:00
|
|
|
mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
|
|
|
|
|
/* 0x300 is DataAccess exception, needed by bad_page_fault() */
|
|
|
|
|
EXC_XFER_LITE(0x300, handle_page_fault)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
2005-10-01 16:43:42 +08:00
|
|
|
EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
|
|
|
|
|
EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
|
|
|
|
|
EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
|
|
|
|
|
EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
|
|
|
|
|
EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
|
|
|
|
|
EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
|
|
|
|
|
EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* On the MPC8xx, these next four traps are used for development
|
|
|
|
|
* support of breakpoints and such. Someday I will get around to
|
|
|
|
|
* using them.
|
|
|
|
|
*/
|
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 16:52:15 +08:00
|
|
|
. = 0x1c00
|
|
|
|
|
DataBreakpoint:
|
2018-01-12 20:45:21 +08:00
|
|
|
mtspr SPRN_SPRG_SCRATCH0, r10
|
|
|
|
|
mtspr SPRN_SPRG_SCRATCH1, r11
|
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 16:52:15 +08:00
|
|
|
mfcr r10
|
|
|
|
|
mfspr r11, SPRN_SRR0
|
|
|
|
|
cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l
|
|
|
|
|
cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l
|
|
|
|
|
beq- cr0, 11f
|
|
|
|
|
beq- cr7, 11f
|
|
|
|
|
EXCEPTION_PROLOG_1
|
|
|
|
|
EXCEPTION_PROLOG_2
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
mfspr r4,SPRN_BAR
|
|
|
|
|
stw r4,_DAR(r11)
|
|
|
|
|
mfspr r5,SPRN_DSISR
|
|
|
|
|
EXC_XFER_EE(0x1c00, do_break)
|
|
|
|
|
11:
|
|
|
|
|
mtcr r10
|
2018-01-12 20:45:21 +08:00
|
|
|
mfspr r10, SPRN_SPRG_SCRATCH0
|
|
|
|
|
mfspr r11, SPRN_SPRG_SCRATCH1
|
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 16:52:15 +08:00
|
|
|
rfi
|
|
|
|
|
|
2018-01-12 20:45:23 +08:00
|
|
|
#ifdef CONFIG_PERF_EVENTS
|
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 20:42:18 +08:00
|
|
|
. = 0x1d00
|
|
|
|
|
InstructionBreakpoint:
|
2018-01-12 20:45:21 +08:00
|
|
|
mtspr SPRN_SPRG_SCRATCH0, r10
|
2018-11-29 22:07:11 +08:00
|
|
|
lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
|
|
|
|
|
addi r10, r10, -1
|
|
|
|
|
stw r10, (instruction_counter - PAGE_OFFSET)@l(0)
|
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 20:42:18 +08:00
|
|
|
lis r10, 0xffff
|
|
|
|
|
ori r10, r10, 0x01
|
|
|
|
|
mtspr SPRN_COUNTA, r10
|
2018-01-12 20:45:21 +08:00
|
|
|
mfspr r10, SPRN_SPRG_SCRATCH0
|
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 20:42:18 +08:00
|
|
|
rfi
|
|
|
|
|
#else
|
2005-10-01 16:43:42 +08:00
|
|
|
EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
|
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 20:42:18 +08:00
|
|
|
#endif
|
2005-10-01 16:43:42 +08:00
|
|
|
EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
|
|
|
|
|
EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
. = 0x2000
|
|
|
|
|
|
2016-09-16 14:42:06 +08:00
|
|
|
/*
|
|
|
|
|
* Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM.
|
|
|
|
|
* not enough space in the DataStoreTLBMiss area.
|
|
|
|
|
*/
|
|
|
|
|
DTLBMissIMMR:
|
2018-01-12 20:45:21 +08:00
|
|
|
mtcr r12
|
2018-10-19 14:54:54 +08:00
|
|
|
/* Set 512k byte guarded page and mark it valid */
|
|
|
|
|
li r10, MD_PS512K | MD_GUARDED | MD_SVALID
|
2018-01-12 20:45:19 +08:00
|
|
|
mtspr SPRN_MD_TWC, r10
|
2016-09-16 14:42:06 +08:00
|
|
|
mfspr r10, SPRN_IMMR /* Get current IMMR */
|
|
|
|
|
rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
|
2018-10-09 21:52:18 +08:00
|
|
|
ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
|
2016-09-16 14:42:06 +08:00
|
|
|
_PAGE_PRESENT | _PAGE_NO_CACHE
|
2018-01-12 20:45:19 +08:00
|
|
|
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
|
2016-09-16 14:42:06 +08:00
|
|
|
|
|
|
|
|
li r11, RPN_PATTERN
|
|
|
|
|
mtspr SPRN_DAR, r11 /* Tag DAR */
|
2018-10-19 14:55:08 +08:00
|
|
|
|
|
|
|
|
0: mfspr r10, SPRN_SPRG_SCRATCH0
|
2018-01-12 20:45:21 +08:00
|
|
|
mfspr r11, SPRN_SPRG_SCRATCH1
|
|
|
|
|
mfspr r12, SPRN_SPRG_SCRATCH2
|
2016-09-16 14:42:06 +08:00
|
|
|
rfi
|
2018-10-19 14:55:08 +08:00
|
|
|
patch_site 0b, patch__dtlbmiss_exit_2
|
2016-09-16 14:42:06 +08:00
|
|
|
|
|
|
|
|
DTLBMissLinear:
|
2018-01-12 20:45:21 +08:00
|
|
|
mtcr r12
|
2018-10-19 14:54:54 +08:00
|
|
|
/* Set 8M byte page and mark it valid */
|
|
|
|
|
li r11, MD_PS8MEG | MD_SVALID
|
2018-01-12 20:45:19 +08:00
|
|
|
mtspr SPRN_MD_TWC, r11
|
2017-07-12 18:08:57 +08:00
|
|
|
rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
|
2018-10-09 21:52:18 +08:00
|
|
|
ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
|
2016-09-16 14:42:06 +08:00
|
|
|
_PAGE_PRESENT
|
2018-01-12 20:45:19 +08:00
|
|
|
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
|
2016-09-16 14:42:06 +08:00
|
|
|
|
|
|
|
|
li r11, RPN_PATTERN
|
|
|
|
|
mtspr SPRN_DAR, r11 /* Tag DAR */
|
2018-10-19 14:55:08 +08:00
|
|
|
|
|
|
|
|
0: mfspr r10, SPRN_SPRG_SCRATCH0
|
2018-01-12 20:45:21 +08:00
|
|
|
mfspr r11, SPRN_SPRG_SCRATCH1
|
|
|
|
|
mfspr r12, SPRN_SPRG_SCRATCH2
|
2016-09-16 14:42:06 +08:00
|
|
|
rfi
|
2018-10-19 14:55:08 +08:00
|
|
|
patch_site 0b, patch__dtlbmiss_exit_3
|
2016-09-16 14:42:06 +08:00
|
|
|
|
2017-07-12 18:08:51 +08:00
|
|
|
#ifndef CONFIG_PIN_TLB_TEXT
|
|
|
|
|
ITLBMissLinear:
|
2018-01-12 20:45:21 +08:00
|
|
|
mtcr r12
|
2018-10-19 14:54:54 +08:00
|
|
|
/* Set 8M byte page and mark it valid */
|
|
|
|
|
li r11, MI_PS8MEG | MI_SVALID
|
2018-01-12 20:45:19 +08:00
|
|
|
mtspr SPRN_MI_TWC, r11
|
2017-07-12 18:08:51 +08:00
|
|
|
rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
|
2018-10-09 21:52:18 +08:00
|
|
|
ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
|
2017-07-12 18:08:51 +08:00
|
|
|
_PAGE_PRESENT
|
2018-01-12 20:45:19 +08:00
|
|
|
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
|
2017-07-12 18:08:51 +08:00
|
|
|
|
2018-10-19 14:55:08 +08:00
|
|
|
0: mfspr r10, SPRN_SPRG_SCRATCH0
|
2018-01-12 20:45:21 +08:00
|
|
|
mfspr r11, SPRN_SPRG_SCRATCH1
|
|
|
|
|
mfspr r12, SPRN_SPRG_SCRATCH2
|
2017-07-12 18:08:51 +08:00
|
|
|
rfi
|
2018-10-19 14:55:08 +08:00
|
|
|
patch_site 0b, patch__itlbmiss_exit_2
|
2017-07-12 18:08:51 +08:00
|
|
|
#endif
|
|
|
|
|
|
2009-11-20 08:21:06 +08:00
|
|
|
/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
|
|
|
|
|
* by decoding the registers used by the dcbx instruction and adding them.
|
2014-08-29 17:14:37 +08:00
|
|
|
* DAR is set to the calculated address.
|
2009-11-20 08:21:06 +08:00
|
|
|
*/
|
|
|
|
|
/* define if you don't want to use self modifying code */
|
|
|
|
|
#define NO_SELF_MODIFYING_CODE
|
|
|
|
|
FixupDAR:/* Entry point for dcbx workaround. */
|
2014-08-29 17:14:38 +08:00
|
|
|
mtspr SPRN_SPRG_SCRATCH2, r10
|
2009-11-20 08:21:06 +08:00
|
|
|
/* fetch instruction from memory. */
|
|
|
|
|
mfspr r10, SPRN_SRR0
|
2018-11-29 22:07:15 +08:00
|
|
|
mtspr SPRN_MD_EPN, r10
|
2017-07-12 18:08:47 +08:00
|
|
|
rlwinm r11, r10, 16, 0xfff8
|
|
|
|
|
cmpli cr0, r11, PAGE_OFFSET@h
|
2018-11-29 22:07:15 +08:00
|
|
|
mfspr r11, SPRN_M_TWB /* Get level 1 table */
|
2017-07-12 18:08:47 +08:00
|
|
|
blt+ 3f
|
2016-05-17 15:02:51 +08:00
|
|
|
rlwinm r11, r10, 16, 0xfff8
|
2018-10-19 14:55:06 +08:00
|
|
|
|
|
|
|
|
0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
|
|
|
|
|
patch_site 0b, patch__fixupdar_linmem_top
|
|
|
|
|
|
2016-09-16 14:42:08 +08:00
|
|
|
/* create physical page address from effective address */
|
|
|
|
|
tophys(r11, r10)
|
|
|
|
|
blt- cr7, 201f
|
2018-11-29 22:07:15 +08:00
|
|
|
mfspr r11, SPRN_M_TWB /* Get level 1 table */
|
|
|
|
|
rlwinm r11, r11, 0, 20, 31
|
|
|
|
|
oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
|
|
|
|
|
3:
|
2015-01-20 17:57:34 +08:00
|
|
|
lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
|
2018-11-29 22:07:15 +08:00
|
|
|
mtspr SPRN_MD_TWC, r11
|
2016-12-07 15:47:28 +08:00
|
|
|
mtcr r11
|
2018-11-29 22:07:15 +08:00
|
|
|
mfspr r11, SPRN_MD_TWC
|
|
|
|
|
lwz r11, 0(r11) /* Get the pte */
|
2016-12-07 15:47:28 +08:00
|
|
|
bt 28,200f /* bit 28 = Large page (8M) */
|
|
|
|
|
bt 29,202f /* bit 29 = Large page (8M or 512K) */
|
2009-11-20 08:21:06 +08:00
|
|
|
/* concat physical page address(r11) and page offset(r10) */
|
2014-09-19 16:36:09 +08:00
|
|
|
rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
|
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:07:50 +08:00
|
|
|
201: lwz r11,0(r11)
|
2009-11-20 08:21:06 +08:00
|
|
|
/* Check if it really is a dcbx instruction. */
|
|
|
|
|
/* dcbt and dcbtst does not generate DTLB Misses/Errors,
|
|
|
|
|
* no need to include them here */
|
2014-08-29 17:14:38 +08:00
|
|
|
xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
|
|
|
|
|
rlwinm r10, r10, 0, 21, 5
|
2009-11-20 08:21:06 +08:00
|
|
|
cmpwi cr0, r10, 2028 /* Is dcbz? */
|
|
|
|
|
beq+ 142f
|
|
|
|
|
cmpwi cr0, r10, 940 /* Is dcbi? */
|
|
|
|
|
beq+ 142f
|
|
|
|
|
cmpwi cr0, r10, 108 /* Is dcbst? */
|
|
|
|
|
beq+ 144f /* Fix up store bit! */
|
|
|
|
|
cmpwi cr0, r10, 172 /* Is dcbf? */
|
|
|
|
|
beq+ 142f
|
|
|
|
|
cmpwi cr0, r10, 1964 /* Is icbi? */
|
|
|
|
|
beq+ 142f
|
2014-08-29 17:14:38 +08:00
|
|
|
141: mfspr r10,SPRN_SPRG_SCRATCH2
|
|
|
|
|
b DARFixed /* Nope, go back to normal TLB processing */
|
2009-11-20 08:21:06 +08:00
|
|
|
|
2016-12-07 15:47:28 +08:00
|
|
|
200:
|
|
|
|
|
/* concat physical page address(r11) and page offset(r10) */
|
|
|
|
|
rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
|
|
|
|
|
b 201b
|
|
|
|
|
|
|
|
|
|
202:
|
|
|
|
|
/* concat physical page address(r11) and page offset(r10) */
|
|
|
|
|
rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
|
|
|
|
|
b 201b
|
|
|
|
|
|
2009-11-20 08:21:06 +08:00
|
|
|
144: mfspr r10, SPRN_DSISR
|
|
|
|
|
rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
|
|
|
|
|
mtspr SPRN_DSISR, r10
|
|
|
|
|
142: /* continue, it was a dcbx, dcbi instruction. */
|
|
|
|
|
#ifndef NO_SELF_MODIFYING_CODE
|
|
|
|
|
andis. r10,r11,0x1f /* test if reg RA is r0 */
|
|
|
|
|
li r10,modified_instr@l
|
|
|
|
|
dcbtst r0,r10 /* touch for store */
|
|
|
|
|
rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
|
|
|
|
|
oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
|
|
|
|
|
ori r11,r11,532
|
|
|
|
|
stw r11,0(r10) /* store add/and instruction */
|
|
|
|
|
dcbf 0,r10 /* flush new instr. to memory. */
|
|
|
|
|
icbi 0,r10 /* invalidate instr. cache line */
|
2014-08-29 17:14:37 +08:00
|
|
|
mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
|
|
|
|
|
mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
|
2009-11-20 08:21:06 +08:00
|
|
|
isync /* Wait until new instr is loaded from memory */
|
|
|
|
|
modified_instr:
|
|
|
|
|
.space 4 /* this is where the add instr. is stored */
|
|
|
|
|
bne+ 143f
|
|
|
|
|
subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
|
|
|
|
|
143: mtdar r10 /* store faulting EA in DAR */
|
2014-08-29 17:14:38 +08:00
|
|
|
mfspr r10,SPRN_SPRG_SCRATCH2
|
2009-11-20 08:21:06 +08:00
|
|
|
b DARFixed /* Go back to normal TLB handling */
|
|
|
|
|
#else
|
|
|
|
|
mfctr r10
|
|
|
|
|
mtdar r10 /* save ctr reg in DAR */
|
|
|
|
|
rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
|
|
|
|
|
addi r10, r10, 150f@l /* add start of table */
|
|
|
|
|
mtctr r10 /* load ctr with jump address */
|
|
|
|
|
xor r10, r10, r10 /* sum starts at zero */
|
|
|
|
|
bctr /* jump into table */
|
|
|
|
|
150:
|
|
|
|
|
add r10, r10, r0 ;b 151f
|
|
|
|
|
add r10, r10, r1 ;b 151f
|
|
|
|
|
add r10, r10, r2 ;b 151f
|
|
|
|
|
add r10, r10, r3 ;b 151f
|
|
|
|
|
add r10, r10, r4 ;b 151f
|
|
|
|
|
add r10, r10, r5 ;b 151f
|
|
|
|
|
add r10, r10, r6 ;b 151f
|
|
|
|
|
add r10, r10, r7 ;b 151f
|
|
|
|
|
add r10, r10, r8 ;b 151f
|
|
|
|
|
add r10, r10, r9 ;b 151f
|
|
|
|
|
mtctr r11 ;b 154f /* r10 needs special handling */
|
|
|
|
|
mtctr r11 ;b 153f /* r11 needs special handling */
|
|
|
|
|
add r10, r10, r12 ;b 151f
|
|
|
|
|
add r10, r10, r13 ;b 151f
|
|
|
|
|
add r10, r10, r14 ;b 151f
|
|
|
|
|
add r10, r10, r15 ;b 151f
|
|
|
|
|
add r10, r10, r16 ;b 151f
|
|
|
|
|
add r10, r10, r17 ;b 151f
|
|
|
|
|
add r10, r10, r18 ;b 151f
|
|
|
|
|
add r10, r10, r19 ;b 151f
|
|
|
|
|
add r10, r10, r20 ;b 151f
|
|
|
|
|
add r10, r10, r21 ;b 151f
|
|
|
|
|
add r10, r10, r22 ;b 151f
|
|
|
|
|
add r10, r10, r23 ;b 151f
|
|
|
|
|
add r10, r10, r24 ;b 151f
|
|
|
|
|
add r10, r10, r25 ;b 151f
|
|
|
|
|
add r10, r10, r26 ;b 151f
|
|
|
|
|
add r10, r10, r27 ;b 151f
|
|
|
|
|
add r10, r10, r28 ;b 151f
|
|
|
|
|
add r10, r10, r29 ;b 151f
|
|
|
|
|
add r10, r10, r30 ;b 151f
|
|
|
|
|
add r10, r10, r31
|
|
|
|
|
151:
|
|
|
|
|
rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
|
|
|
|
|
beq 152f /* if reg RA is zero, don't add it */
|
|
|
|
|
addi r11, r11, 150b@l /* add start of table */
|
|
|
|
|
mtctr r11 /* load ctr with jump address */
|
|
|
|
|
rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
|
|
|
|
|
bctr /* jump into table */
|
|
|
|
|
152:
|
|
|
|
|
mfdar r11
|
|
|
|
|
mtctr r11 /* restore ctr reg from DAR */
|
|
|
|
|
mtdar r10 /* save fault EA to DAR */
|
2014-08-29 17:14:38 +08:00
|
|
|
mfspr r10,SPRN_SPRG_SCRATCH2
|
2009-11-20 08:21:06 +08:00
|
|
|
b DARFixed /* Go back to normal TLB handling */
|
|
|
|
|
|
|
|
|
|
/* special handling for r10,r11 since these are modified already */
|
2014-08-29 17:14:37 +08:00
|
|
|
153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
|
2014-08-29 17:14:39 +08:00
|
|
|
add r10, r10, r11 /* add it */
|
|
|
|
|
mfctr r11 /* restore r11 */
|
|
|
|
|
b 151b
|
2014-08-29 17:14:37 +08:00
|
|
|
154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
|
2014-08-29 17:14:39 +08:00
|
|
|
add r10, r10, r11 /* add it */
|
2009-11-20 08:21:06 +08:00
|
|
|
mfctr r11 /* restore r11 */
|
|
|
|
|
b 151b
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-09-26 14:04:21 +08:00
|
|
|
/*
|
|
|
|
|
* This is where the main kernel code starts.
|
|
|
|
|
*/
|
|
|
|
|
start_here:
|
|
|
|
|
/* ptr to current */
|
|
|
|
|
lis r2,init_task@h
|
|
|
|
|
ori r2,r2,init_task@l
|
|
|
|
|
|
|
|
|
|
/* ptr to phys current thread */
|
|
|
|
|
tophys(r4,r2)
|
|
|
|
|
addi r4,r4,THREAD /* init task's THREAD */
|
2009-07-15 04:52:54 +08:00
|
|
|
mtspr SPRN_SPRG_THREAD,r4
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* stack */
|
|
|
|
|
lis r1,init_thread_union@ha
|
|
|
|
|
addi r1,r1,init_thread_union@l
|
|
|
|
|
li r0,0
|
|
|
|
|
stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
|
|
|
|
|
|
2018-07-13 21:10:47 +08:00
|
|
|
lis r6, swapper_pg_dir@ha
|
|
|
|
|
tophys(r6,r6)
|
2018-11-29 22:07:15 +08:00
|
|
|
mtspr SPRN_M_TWB, r6
|
2018-07-13 21:10:47 +08:00
|
|
|
|
2005-09-26 14:04:21 +08:00
|
|
|
bl early_init /* We have to do this with MMU on */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Decide what sort of machine this is and initialize the MMU.
|
|
|
|
|
*/
|
2011-07-25 19:29:33 +08:00
|
|
|
li r3,0
|
|
|
|
|
mr r4,r31
|
2005-09-26 14:04:21 +08:00
|
|
|
bl machine_init
|
|
|
|
|
bl MMU_init
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Go back to running unmapped so we can load up new values
|
|
|
|
|
* and change to using our exception vectors.
|
|
|
|
|
* On the 8xx, all we have to do is invalidate the TLB to clear
|
|
|
|
|
* the old 8M byte TLB mappings and load the page table base register.
|
|
|
|
|
*/
|
|
|
|
|
/* The right way to do this would be to track it down through
|
|
|
|
|
* init's THREAD like the context switch code does, but this is
|
|
|
|
|
* easier......until someone changes init's static structures.
|
|
|
|
|
*/
|
|
|
|
|
lis r4,2f@h
|
|
|
|
|
ori r4,r4,2f@l
|
|
|
|
|
tophys(r4,r4)
|
|
|
|
|
li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
|
|
|
|
|
mtspr SPRN_SRR0,r4
|
|
|
|
|
mtspr SPRN_SRR1,r3
|
|
|
|
|
rfi
|
|
|
|
|
/* Load up the kernel context */
|
|
|
|
|
2:
|
|
|
|
|
tlbia /* Clear all TLB entries */
|
|
|
|
|
sync /* wait for tlbia/tlbie to finish */
|
|
|
|
|
|
|
|
|
|
/* set up the PTE pointers for the Abatron bdiGDB.
|
|
|
|
|
*/
|
|
|
|
|
tovirt(r6,r6)
|
|
|
|
|
lis r5, abatron_pteptrs@h
|
|
|
|
|
ori r5, r5, abatron_pteptrs@l
|
2018-05-24 19:02:06 +08:00
|
|
|
stw r5, 0xf0(0) /* Must match your Abatron config file */
|
2005-09-26 14:04:21 +08:00
|
|
|
tophys(r5,r5)
|
|
|
|
|
stw r6, 0(r5)
|
|
|
|
|
|
|
|
|
|
/* Now turn on the MMU for real! */
|
|
|
|
|
li r4,MSR_KERNEL
|
|
|
|
|
lis r3,start_kernel@h
|
|
|
|
|
ori r3,r3,start_kernel@l
|
|
|
|
|
mtspr SPRN_SRR0,r3
|
|
|
|
|
mtspr SPRN_SRR1,r4
|
|
|
|
|
rfi /* enable MMU and jump to start_kernel */
|
|
|
|
|
|
|
|
|
|
/* Set up the initial MMU state so we can do the first level of
|
|
|
|
|
* kernel initialization. This maps the first 8 MBytes of memory 1:1
|
|
|
|
|
* virtual to physical. Also, set the cache mode since that is defined
|
|
|
|
|
* by TLB entries and perform any additional mapping (like of the IMMR).
|
|
|
|
|
* If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
|
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 15:02:43 +08:00
|
|
|
* 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
|
2005-09-26 14:04:21 +08:00
|
|
|
* these mappings is mapped by page tables.
|
|
|
|
|
*/
|
|
|
|
|
initial_mmu:
|
2016-05-17 15:02:49 +08:00
|
|
|
li r8, 0
|
|
|
|
|
mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
|
|
|
|
|
lis r10, MD_RESETVAL@h
|
|
|
|
|
#ifndef CONFIG_8xx_COPYBACK
|
|
|
|
|
oris r10, r10, MD_WTDEF@h
|
|
|
|
|
#endif
|
|
|
|
|
mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
|
|
|
|
|
|
2005-09-26 14:04:21 +08:00
|
|
|
tlbia /* Invalidate all TLB entries */
|
2017-07-12 18:08:51 +08:00
|
|
|
#ifdef CONFIG_PIN_TLB_TEXT
|
2005-09-26 14:04:21 +08:00
|
|
|
lis r8, MI_RSV4I@h
|
|
|
|
|
ori r8, r8, 0x1c00
|
2009-12-29 13:10:58 +08:00
|
|
|
|
2005-09-26 14:04:21 +08:00
|
|
|
mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
|
2017-07-12 18:08:51 +08:00
|
|
|
#endif
|
2005-09-26 14:04:21 +08:00
|
|
|
|
2017-07-12 18:08:51 +08:00
|
|
|
#ifdef CONFIG_PIN_TLB_DATA
|
2016-05-17 15:02:49 +08:00
|
|
|
oris r10, r10, MD_RSV4I@h
|
2005-09-26 14:04:21 +08:00
|
|
|
mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
|
2016-05-17 15:02:49 +08:00
|
|
|
#endif
|
2005-09-26 14:04:21 +08:00
|
|
|
|
2016-05-17 15:02:54 +08:00
|
|
|
/* Now map the lower 8 Meg into the ITLB. */
|
2005-09-26 14:04:21 +08:00
|
|
|
lis r8, KERNELBASE@h /* Create vaddr for TLB */
|
|
|
|
|
ori r8, r8, MI_EVALID /* Mark it valid */
|
|
|
|
|
mtspr SPRN_MI_EPN, r8
|
2018-01-12 20:45:31 +08:00
|
|
|
li r8, MI_PS8MEG /* Set 8M byte page */
|
2018-10-19 14:54:54 +08:00
|
|
|
ori r8, r8, MI_SVALID /* Make it valid */
|
2005-09-26 14:04:21 +08:00
|
|
|
mtspr SPRN_MI_TWC, r8
|
|
|
|
|
li r8, MI_BOOTINIT /* Create RPN for address 0 */
|
|
|
|
|
mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
|
2016-05-17 15:02:54 +08:00
|
|
|
|
2015-04-22 18:06:45 +08:00
|
|
|
lis r8, MI_APG_INIT@h /* Set protection modes */
|
|
|
|
|
ori r8, r8, MI_APG_INIT@l
|
2005-09-26 14:04:21 +08:00
|
|
|
mtspr SPRN_MI_AP, r8
|
2015-04-22 18:06:45 +08:00
|
|
|
lis r8, MD_APG_INIT@h
|
|
|
|
|
ori r8, r8, MD_APG_INIT@l
|
2005-09-26 14:04:21 +08:00
|
|
|
mtspr SPRN_MD_AP, r8
|
|
|
|
|
|
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 15:02:43 +08:00
|
|
|
/* Map a 512k page for the IMMR to get the processor
|
2005-09-26 14:04:21 +08:00
|
|
|
* internal registers (among other things).
|
|
|
|
|
*/
|
2016-05-17 15:02:56 +08:00
|
|
|
#ifdef CONFIG_PIN_TLB_IMMR
|
2017-07-12 18:08:51 +08:00
|
|
|
oris r10, r10, MD_RSV4I@h
|
2016-05-17 15:02:56 +08:00
|
|
|
ori r10, r10, 0x1c00
|
|
|
|
|
mtspr SPRN_MD_CTR, r10
|
|
|
|
|
|
2005-09-26 14:04:21 +08:00
|
|
|
mfspr r9, 638 /* Get current IMMR */
|
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 15:02:43 +08:00
|
|
|
andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
|
2005-09-26 14:04:21 +08:00
|
|
|
|
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 15:02:43 +08:00
|
|
|
lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
|
2005-09-26 14:04:21 +08:00
|
|
|
ori r8, r8, MD_EVALID /* Mark it valid */
|
|
|
|
|
mtspr SPRN_MD_EPN, r8
|
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 15:02:43 +08:00
|
|
|
li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
|
2018-10-19 14:54:54 +08:00
|
|
|
ori r8, r8, MD_SVALID /* Make it valid */
|
2005-09-26 14:04:21 +08:00
|
|
|
mtspr SPRN_MD_TWC, r8
|
|
|
|
|
mr r8, r9 /* Create paddr for TLB */
|
|
|
|
|
ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
|
|
|
|
|
mtspr SPRN_MD_RPN, r8
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Since the cache is enabled according to the information we
|
|
|
|
|
* just loaded into the TLB, invalidate and enable the caches here.
|
|
|
|
|
* We should probably check/set other modes....later.
|
|
|
|
|
*/
|
|
|
|
|
lis r8, IDC_INVALL@h
|
|
|
|
|
mtspr SPRN_IC_CST, r8
|
|
|
|
|
mtspr SPRN_DC_CST, r8
|
|
|
|
|
lis r8, IDC_ENABLE@h
|
|
|
|
|
mtspr SPRN_IC_CST, r8
|
|
|
|
|
#ifdef CONFIG_8xx_COPYBACK
|
|
|
|
|
mtspr SPRN_DC_CST, r8
|
|
|
|
|
#else
|
|
|
|
|
/* For a debug option, I left this here to easily enable
|
|
|
|
|
* the write through cache mode
|
|
|
|
|
*/
|
|
|
|
|
lis r8, DC_SFWT@h
|
|
|
|
|
mtspr SPRN_DC_CST, r8
|
|
|
|
|
lis r8, IDC_ENABLE@h
|
|
|
|
|
mtspr SPRN_DC_CST, r8
|
|
|
|
|
#endif
|
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 20:42:18 +08:00
|
|
|
/* Disable debug mode entry on breakpoints */
|
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 16:52:15 +08:00
|
|
|
mfspr r8, SPRN_DER
|
2018-01-12 20:45:23 +08:00
|
|
|
#ifdef CONFIG_PERF_EVENTS
|
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 20:42:18 +08:00
|
|
|
rlwinm r8, r8, 0, ~0xc
|
|
|
|
|
#else
|
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 16:52:15 +08:00
|
|
|
rlwinm r8, r8, 0, ~0x8
|
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 20:42:18 +08:00
|
|
|
#endif
|
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 16:52:15 +08:00
|
|
|
mtspr SPRN_DER, r8
|
2005-09-26 14:04:21 +08:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We put a few things here that have to be page-aligned.
|
|
|
|
|
* This stuff goes at the beginning of the data segment,
|
|
|
|
|
* which is page-aligned.
|
|
|
|
|
*/
|
|
|
|
|
.data
|
|
|
|
|
.globl sdata
|
|
|
|
|
sdata:
|
|
|
|
|
.globl empty_zero_page
|
2014-09-19 16:36:09 +08:00
|
|
|
.align PAGE_SHIFT
|
2005-09-26 14:04:21 +08:00
|
|
|
empty_zero_page:
|
2014-09-19 16:36:09 +08:00
|
|
|
.space PAGE_SIZE
|
2016-01-14 12:33:46 +08:00
|
|
|
EXPORT_SYMBOL(empty_zero_page)
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
.globl swapper_pg_dir
|
|
|
|
|
swapper_pg_dir:
|
2014-09-19 16:36:09 +08:00
|
|
|
.space PGD_TABLE_SIZE
|
2005-09-26 14:04:21 +08:00
|
|
|
|
|
|
|
|
/* Room for two PTE table poiners, usually the kernel and current user
|
|
|
|
|
* pointer to their respective root page table (pgdir).
|
|
|
|
|
*/
|
|
|
|
|
abatron_pteptrs:
|
|
|
|
|
.space 8
|