2006-09-27 17:09:34 +08:00
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/*
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2008-07-07 20:11:54 +08:00
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* linux/arch/sh/boards/se/7343/irq.c
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2006-09-27 17:09:34 +08:00
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*
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2008-07-07 20:11:54 +08:00
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* Copyright (C) 2008 Yoshihiro Shimoda
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*
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* Based on linux/arch/sh/boards/se/7722/irq.c
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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2006-09-27 17:09:34 +08:00
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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2008-07-07 20:11:54 +08:00
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#include <linux/interrupt.h>
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2008-07-29 20:41:37 +08:00
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#include <linux/io.h>
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#include <mach-se/mach/se7343.h>
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2006-09-27 17:09:34 +08:00
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2010-01-12 12:37:04 +08:00
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unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
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2010-10-27 14:30:07 +08:00
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static void disable_se7343_irq(struct irq_data *data)
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2006-09-27 17:09:34 +08:00
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{
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2010-10-27 14:30:07 +08:00
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unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
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2010-01-26 11:58:40 +08:00
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__raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
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2006-09-27 17:09:34 +08:00
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}
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2010-10-27 14:30:07 +08:00
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static void enable_se7343_irq(struct irq_data *data)
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2006-09-27 17:09:34 +08:00
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{
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2010-10-27 14:30:07 +08:00
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unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
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2010-01-26 11:58:40 +08:00
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__raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
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2006-09-27 17:09:34 +08:00
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}
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2008-07-07 20:11:54 +08:00
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static struct irq_chip se7343_irq_chip __read_mostly = {
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2010-10-27 14:30:07 +08:00
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.name = "SE7343-FPGA",
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.irq_mask = disable_se7343_irq,
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.irq_unmask = enable_se7343_irq,
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2006-09-27 17:09:34 +08:00
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};
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2008-07-07 20:11:54 +08:00
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static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
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2006-09-27 17:09:34 +08:00
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{
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2010-01-26 11:58:40 +08:00
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unsigned short intv = __raw_readw(PA_CPLD_ST);
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2010-01-12 12:37:04 +08:00
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unsigned int ext_irq = 0;
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2008-07-07 20:11:54 +08:00
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intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
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2010-01-12 12:37:04 +08:00
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for (; intv; intv >>= 1, ext_irq++) {
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if (!(intv & 1))
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continue;
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generic_handle_irq(se7343_fpga_irq[ext_irq]);
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2006-09-27 17:09:34 +08:00
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}
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}
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/*
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* Initialize IRQ setting
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*/
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2008-07-07 20:11:54 +08:00
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void __init init_7343se_IRQ(void)
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2006-09-27 17:09:34 +08:00
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{
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2010-01-12 12:37:04 +08:00
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int i, irq;
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2008-07-07 20:11:54 +08:00
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2010-01-26 11:58:40 +08:00
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__raw_writew(0, PA_CPLD_IMSK); /* disable all irqs */
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__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
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2008-07-07 20:11:54 +08:00
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2010-01-12 12:37:04 +08:00
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for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
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irq = create_irq();
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if (irq < 0)
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return;
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se7343_fpga_irq[i] = irq;
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set_irq_chip_and_handler_name(se7343_fpga_irq[i],
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2008-07-07 20:11:54 +08:00
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&se7343_irq_chip,
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handle_level_irq, "level");
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2010-01-12 12:37:04 +08:00
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set_irq_chip_data(se7343_fpga_irq[i], (void *)i);
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}
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2008-07-07 20:11:54 +08:00
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set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
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set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
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set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
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set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
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set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
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set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
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set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
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2006-09-27 17:09:34 +08:00
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}
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