2005-04-17 06:20:36 +08:00
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/*
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* arch/arm/mach-pxa/time.c
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*
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2007-07-21 10:39:36 +08:00
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* PXA clocksource, clockevents, and OST interrupt handlers.
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* Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
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*
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* Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
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* by MontaVista Software, Inc. (Nico, your code rocks!)
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2005-04-17 06:20:36 +08:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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2014-07-15 00:52:02 +08:00
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#include <linux/clk.h>
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2007-07-21 10:39:36 +08:00
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#include <linux/clockchips.h>
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2014-07-15 00:52:02 +08:00
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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2013-06-02 14:39:40 +08:00
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#include <linux/sched_clock.h>
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2007-07-21 10:39:36 +08:00
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2007-08-17 23:55:22 +08:00
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#include <asm/div64.h>
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2014-07-15 00:52:02 +08:00
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#define OSMR0 0x00 /* OS Timer 0 Match Register */
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#define OSMR1 0x04 /* OS Timer 1 Match Register */
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#define OSMR2 0x08 /* OS Timer 2 Match Register */
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#define OSMR3 0x0C /* OS Timer 3 Match Register */
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#define OSCR 0x10 /* OS Timer Counter Register */
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#define OSSR 0x14 /* OS Timer Status Register */
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#define OWER 0x18 /* OS Timer Watchdog Enable Register */
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#define OIER 0x1C /* OS Timer Interrupt Enable Register */
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#define OSSR_M3 (1 << 3) /* Match status channel 3 */
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#define OSSR_M2 (1 << 2) /* Match status channel 2 */
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#define OSSR_M1 (1 << 1) /* Match status channel 1 */
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#define OSSR_M0 (1 << 0) /* Match status channel 0 */
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#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
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2005-04-17 06:20:36 +08:00
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2007-08-17 23:55:22 +08:00
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/*
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* This is PXA's sched_clock implementation. This has a resolution
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* of at least 308 ns and a maximum value of 208 days.
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*
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* The return value is guaranteed to be monotonic in that range as
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* long as there is always less than 582 seconds between successive
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* calls to sched_clock() which should always be the case in practice.
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*/
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2014-07-15 00:52:02 +08:00
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#define timer_readl(reg) readl_relaxed(timer_base + (reg))
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#define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))
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static void __iomem *timer_base;
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2013-11-16 07:26:19 +08:00
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static u64 notrace pxa_read_sched_clock(void)
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2007-08-17 23:55:22 +08:00
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{
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2014-07-15 00:52:02 +08:00
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return timer_readl(OSCR);
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2007-08-17 23:55:22 +08:00
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}
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2007-11-13 06:45:16 +08:00
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#define MIN_OSCR_DELTA 16
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2005-04-17 06:20:36 +08:00
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static irqreturn_t
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2007-07-21 10:39:36 +08:00
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pxa_ost0_interrupt(int irq, void *dev_id)
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2005-04-17 06:20:36 +08:00
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{
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2007-07-21 10:39:36 +08:00
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struct clock_event_device *c = dev_id;
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2007-11-13 06:45:16 +08:00
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/* Disarm the compare/match, signal the event. */
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2014-07-15 00:52:02 +08:00
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timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
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timer_writel(OSSR_M0, OSSR);
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2007-11-13 06:45:16 +08:00
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c->event_handler(c);
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2005-04-17 06:20:36 +08:00
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return IRQ_HANDLED;
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}
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2007-07-21 10:39:36 +08:00
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static int
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pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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2009-12-17 19:43:29 +08:00
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unsigned long next, oscr;
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2007-07-21 10:39:36 +08:00
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2014-07-15 00:52:02 +08:00
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timer_writel(timer_readl(OIER) | OIER_E0, OIER);
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next = timer_readl(OSCR) + delta;
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timer_writel(next, OSMR0);
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oscr = timer_readl(OSCR);
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2007-11-09 07:35:46 +08:00
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return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
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2007-07-21 10:39:36 +08:00
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}
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2015-06-18 18:54:30 +08:00
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static int pxa_osmr0_shutdown(struct clock_event_device *evt)
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2007-07-21 10:39:36 +08:00
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{
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2015-06-18 18:54:30 +08:00
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/* initializing, released, or preparing for suspend */
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timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
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timer_writel(OSSR_M0, OSSR);
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return 0;
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2007-07-21 10:39:36 +08:00
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}
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2012-11-08 07:34:13 +08:00
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#ifdef CONFIG_PM
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static unsigned long osmr[4], oier, oscr;
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static void pxa_timer_suspend(struct clock_event_device *cedev)
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{
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2014-07-15 00:52:02 +08:00
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osmr[0] = timer_readl(OSMR0);
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osmr[1] = timer_readl(OSMR1);
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osmr[2] = timer_readl(OSMR2);
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osmr[3] = timer_readl(OSMR3);
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oier = timer_readl(OIER);
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oscr = timer_readl(OSCR);
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2012-11-08 07:34:13 +08:00
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}
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static void pxa_timer_resume(struct clock_event_device *cedev)
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{
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/*
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* Ensure that we have at least MIN_OSCR_DELTA between match
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* register 0 and the OSCR, to guarantee that we will receive
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* the one-shot timer interrupt. We adjust OSMR0 in preference
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* to OSCR to guarantee that OSCR is monotonically incrementing.
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*/
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if (osmr[0] - oscr < MIN_OSCR_DELTA)
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osmr[0] += MIN_OSCR_DELTA;
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2014-07-15 00:52:02 +08:00
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timer_writel(osmr[0], OSMR0);
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timer_writel(osmr[1], OSMR1);
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timer_writel(osmr[2], OSMR2);
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timer_writel(osmr[3], OSMR3);
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timer_writel(oier, OIER);
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timer_writel(oscr, OSCR);
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2012-11-08 07:34:13 +08:00
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}
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#else
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#define pxa_timer_suspend NULL
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#define pxa_timer_resume NULL
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#endif
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2007-07-21 10:39:36 +08:00
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static struct clock_event_device ckevt_pxa_osmr0 = {
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2015-06-18 18:54:30 +08:00
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.name = "osmr0",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.set_next_event = pxa_osmr0_set_next_event,
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.set_state_shutdown = pxa_osmr0_shutdown,
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.set_state_oneshot = pxa_osmr0_shutdown,
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.suspend = pxa_timer_suspend,
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.resume = pxa_timer_resume,
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2005-04-17 06:20:36 +08:00
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};
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2007-07-21 10:39:36 +08:00
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static struct irqaction pxa_ost0_irq = {
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.name = "ost0",
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2013-12-09 18:22:22 +08:00
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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2007-07-21 10:39:36 +08:00
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.handler = pxa_ost0_interrupt,
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.dev_id = &ckevt_pxa_osmr0,
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};
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2016-06-06 23:58:27 +08:00
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static int __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
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2005-04-17 06:20:36 +08:00
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{
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2016-06-06 23:58:27 +08:00
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int ret;
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2014-07-15 00:52:02 +08:00
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timer_writel(0, OIER);
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timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
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2005-04-17 06:20:36 +08:00
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2013-11-16 07:26:19 +08:00
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sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate);
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2007-08-17 23:55:22 +08:00
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2008-12-13 18:50:26 +08:00
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ckevt_pxa_osmr0.cpumask = cpumask_of(0);
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2005-04-17 06:20:36 +08:00
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2016-06-06 23:58:27 +08:00
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ret = setup_irq(irq, &pxa_ost0_irq);
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if (ret) {
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pr_err("Failed to setup irq");
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return ret;
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}
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ret = clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200,
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32, clocksource_mmio_readl_up);
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if (ret) {
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pr_err("Failed to init clocksource");
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return ret;
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}
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2005-09-01 19:48:40 +08:00
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2013-01-15 02:20:02 +08:00
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clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
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2014-07-15 00:52:02 +08:00
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MIN_OSCR_DELTA * 2, 0x7fffffff);
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2016-06-06 23:58:27 +08:00
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return 0;
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2014-07-15 00:52:02 +08:00
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}
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2016-06-06 23:58:27 +08:00
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static int __init pxa_timer_dt_init(struct device_node *np)
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2014-07-15 00:52:02 +08:00
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{
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struct clk *clk;
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2016-06-06 23:58:27 +08:00
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int irq, ret;
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2014-07-15 00:52:02 +08:00
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/* timer registers are shared with watchdog timer */
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timer_base = of_iomap(np, 0);
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2016-06-06 23:58:27 +08:00
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if (!timer_base) {
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pr_err("%s: unable to map resource\n", np->name);
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return -ENXIO;
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}
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2014-07-15 00:52:02 +08:00
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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pr_crit("%s: unable to get clk\n", np->name);
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2016-06-06 23:58:27 +08:00
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_crit("Failed to prepare clock");
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return ret;
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2014-07-15 00:52:02 +08:00
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}
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/* we are only interested in OS-timer0 irq */
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irq = irq_of_parse_and_map(np, 0);
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if (irq <= 0) {
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pr_crit("%s: unable to parse OS-timer0 irq\n", np->name);
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2016-06-06 23:58:27 +08:00
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return -EINVAL;
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2014-07-15 00:52:02 +08:00
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}
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2016-06-06 23:58:27 +08:00
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return pxa_timer_common_init(irq, clk_get_rate(clk));
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2014-07-15 00:52:02 +08:00
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}
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2016-06-07 06:27:44 +08:00
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CLOCKSOURCE_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);
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2014-07-15 00:52:02 +08:00
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/*
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* Legacy timer init for non device-tree boards.
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*/
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void __init pxa_timer_nodt_init(int irq, void __iomem *base,
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unsigned long clock_tick_rate)
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{
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struct clk *clk;
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timer_base = base;
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clk = clk_get(NULL, "OSTIMER0");
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if (clk && !IS_ERR(clk))
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clk_prepare_enable(clk);
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else
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pr_crit("%s: unable to get clk\n", __func__);
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pxa_timer_common_init(irq, clock_tick_rate);
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2005-09-01 19:48:40 +08:00
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}
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