2011-11-09 04:43:47 +08:00
|
|
|
* Synopsys DesignWare I2C
|
|
|
|
|
|
|
|
Required properties :
|
|
|
|
|
|
|
|
- compatible : should be "snps,designware-i2c"
|
|
|
|
- reg : Offset and length of the register set for the device
|
|
|
|
- interrupts : <IRQ> where IRQ is the interrupt number.
|
|
|
|
|
|
|
|
Recommended properties :
|
|
|
|
|
|
|
|
- clock-frequency : desired I2C bus clock frequency in Hz.
|
|
|
|
|
2013-06-26 16:55:06 +08:00
|
|
|
Optional properties :
|
|
|
|
- i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
|
|
|
|
This option is only supported in hardware blocks version 1.11a or newer.
|
|
|
|
|
2014-12-06 02:49:39 +08:00
|
|
|
- i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds.
|
2014-01-21 00:43:43 +08:00
|
|
|
This value which is by default 300ns is used to compute the tLOW period.
|
|
|
|
|
2014-12-06 02:49:39 +08:00
|
|
|
- i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.
|
2014-01-21 00:43:43 +08:00
|
|
|
This value which is by default 300ns is used to compute the tHIGH period.
|
|
|
|
|
2011-11-09 04:43:47 +08:00
|
|
|
Example :
|
|
|
|
|
|
|
|
i2c@f0000 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
compatible = "snps,designware-i2c";
|
|
|
|
reg = <0xf0000 0x1000>;
|
|
|
|
interrupts = <11>;
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
};
|
2013-06-26 16:55:06 +08:00
|
|
|
|
|
|
|
i2c@1120000 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
compatible = "snps,designware-i2c";
|
|
|
|
reg = <0x1120000 0x1000>;
|
|
|
|
interrupt-parent = <&ictl>;
|
|
|
|
interrupts = <12 1>;
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
i2c-sda-hold-time-ns = <300>;
|
2014-01-21 00:43:43 +08:00
|
|
|
i2c-sda-falling-time-ns = <300>;
|
|
|
|
i2c-scl-falling-time-ns = <300>;
|
2013-06-26 16:55:06 +08:00
|
|
|
};
|