2009-02-05 13:18:13 +08:00
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/**
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* AMCC SoC PPC4xx Crypto Driver
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*
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* Copyright (c) 2008 Applied Micro Circuits Corporation.
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* All rights reserved. James Hsiao <jhsiao@amcc.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This file implements AMCC crypto offload Linux device driver for use with
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* Linux CryptoAPI.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock_types.h>
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#include <linux/random.h>
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#include <linux/scatterlist.h>
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#include <linux/crypto.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/init.h>
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2013-11-11 13:19:08 +08:00
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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2009-02-05 13:18:13 +08:00
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#include <linux/of_platform.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2009-02-05 13:18:13 +08:00
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#include <asm/dcr.h>
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#include <asm/dcr-regs.h>
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#include <asm/cacheflush.h>
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#include <crypto/aes.h>
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2017-08-25 21:47:21 +08:00
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#include <crypto/ctr.h>
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2009-02-05 13:18:13 +08:00
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#include <crypto/sha.h>
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2017-08-25 21:47:22 +08:00
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#include <crypto/scatterwalk.h>
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2009-02-05 13:18:13 +08:00
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#include "crypto4xx_reg_def.h"
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#include "crypto4xx_core.h"
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#include "crypto4xx_sa.h"
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2016-04-18 18:57:41 +08:00
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#include "crypto4xx_trng.h"
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2009-02-05 13:18:13 +08:00
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#define PPC4XX_SEC_VERSION_STR "0.5"
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/**
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* PPC4xx Crypto Engine Initialization Routine
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*/
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static void crypto4xx_hw_init(struct crypto4xx_device *dev)
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{
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union ce_ring_size ring_size;
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2017-04-21 19:13:49 +08:00
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union ce_ring_control ring_ctrl;
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2009-02-05 13:18:13 +08:00
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union ce_part_ring_size part_ring_size;
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union ce_io_threshold io_threshold;
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u32 rand_num;
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union ce_pe_dma_cfg pe_dma_cfg;
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2011-06-27 15:39:07 +08:00
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u32 device_ctrl;
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2009-02-05 13:18:13 +08:00
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writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
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/* setup pe dma, include reset sg, pdr and pe, then release reset */
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pe_dma_cfg.w = 0;
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pe_dma_cfg.bf.bo_sgpd_en = 1;
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pe_dma_cfg.bf.bo_data_en = 0;
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pe_dma_cfg.bf.bo_sa_en = 1;
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pe_dma_cfg.bf.bo_pd_en = 1;
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pe_dma_cfg.bf.dynamic_sa_en = 1;
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pe_dma_cfg.bf.reset_sg = 1;
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pe_dma_cfg.bf.reset_pdr = 1;
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pe_dma_cfg.bf.reset_pe = 1;
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writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
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/* un reset pe,sg and pdr */
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pe_dma_cfg.bf.pe_mode = 0;
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pe_dma_cfg.bf.reset_sg = 0;
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pe_dma_cfg.bf.reset_pdr = 0;
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pe_dma_cfg.bf.reset_pe = 0;
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pe_dma_cfg.bf.bo_td_en = 0;
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writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
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writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE);
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writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE);
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writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL);
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get_random_bytes(&rand_num, sizeof(rand_num));
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writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L);
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get_random_bytes(&rand_num, sizeof(rand_num));
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writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H);
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ring_size.w = 0;
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ring_size.bf.ring_offset = PPC4XX_PD_SIZE;
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ring_size.bf.ring_size = PPC4XX_NUM_PD;
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writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
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ring_ctrl.w = 0;
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writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
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2011-06-27 15:39:07 +08:00
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device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
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device_ctrl |= PPC4XX_DC_3DES_EN;
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writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
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2009-02-05 13:18:13 +08:00
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writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
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writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
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part_ring_size.w = 0;
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part_ring_size.bf.sdr_size = PPC4XX_SDR_SIZE;
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part_ring_size.bf.gdr_size = PPC4XX_GDR_SIZE;
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writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE);
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writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG);
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io_threshold.w = 0;
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io_threshold.bf.output_threshold = PPC4XX_OUTPUT_THRESHOLD;
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io_threshold.bf.input_threshold = PPC4XX_INPUT_THRESHOLD;
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writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD);
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writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR);
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writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR);
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writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR);
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writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR);
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writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR);
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writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR);
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writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR);
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/* un reset pe,sg and pdr */
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pe_dma_cfg.bf.pe_mode = 1;
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pe_dma_cfg.bf.reset_sg = 0;
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pe_dma_cfg.bf.reset_pdr = 0;
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pe_dma_cfg.bf.reset_pe = 0;
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pe_dma_cfg.bf.bo_td_en = 0;
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writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
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/*clear all pending interrupt*/
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writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR);
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writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
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writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
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writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG);
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writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
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}
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int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size)
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{
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ctx->sa_in = dma_alloc_coherent(ctx->dev->core_dev->device, size * 4,
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&ctx->sa_in_dma_addr, GFP_ATOMIC);
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if (ctx->sa_in == NULL)
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return -ENOMEM;
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ctx->sa_out = dma_alloc_coherent(ctx->dev->core_dev->device, size * 4,
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&ctx->sa_out_dma_addr, GFP_ATOMIC);
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if (ctx->sa_out == NULL) {
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crypto: crypto4xx - Fix size used in dma_free_coherent()
The size used in 'dma_free_coherent()' looks un-initialized here.
ctx->sa_len is set a few lines below and is apparently not set by the
caller.
So use 'size' as in the corresponding 'dma_alloc_coherent()' a few lines
above.
This has been spotted with coccinelle, using the following script:
////////////////////
@r@
expression x0, x1, y0, y1, z0, z1, t0, t1, ret;
@@
* ret = dma_alloc_coherent(x0, y0, z0, t0);
...
* dma_free_coherent(x1, y1, ret, t1);
@script:python@
y0 << r.y0;
y1 << r.y1;
@@
if y1.find(y0) == -1:
print "WARNING: sizes look different: '%s' vs '%s'" % (y0, y1)
////////////////////
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-10-08 04:36:20 +08:00
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dma_free_coherent(ctx->dev->core_dev->device, size * 4,
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2009-02-05 13:18:13 +08:00
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ctx->sa_in, ctx->sa_in_dma_addr);
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return -ENOMEM;
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}
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memset(ctx->sa_in, 0, size * 4);
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memset(ctx->sa_out, 0, size * 4);
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ctx->sa_len = size;
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return 0;
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}
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void crypto4xx_free_sa(struct crypto4xx_ctx *ctx)
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{
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if (ctx->sa_in != NULL)
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dma_free_coherent(ctx->dev->core_dev->device, ctx->sa_len * 4,
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ctx->sa_in, ctx->sa_in_dma_addr);
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if (ctx->sa_out != NULL)
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dma_free_coherent(ctx->dev->core_dev->device, ctx->sa_len * 4,
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ctx->sa_out, ctx->sa_out_dma_addr);
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ctx->sa_in_dma_addr = 0;
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ctx->sa_out_dma_addr = 0;
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ctx->sa_len = 0;
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}
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u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx)
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{
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ctx->state_record = dma_alloc_coherent(ctx->dev->core_dev->device,
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sizeof(struct sa_state_record),
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&ctx->state_record_dma_addr, GFP_ATOMIC);
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if (!ctx->state_record_dma_addr)
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return -ENOMEM;
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memset(ctx->state_record, 0, sizeof(struct sa_state_record));
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return 0;
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}
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void crypto4xx_free_state_record(struct crypto4xx_ctx *ctx)
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{
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if (ctx->state_record != NULL)
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dma_free_coherent(ctx->dev->core_dev->device,
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sizeof(struct sa_state_record),
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ctx->state_record,
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ctx->state_record_dma_addr);
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ctx->state_record_dma_addr = 0;
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}
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/**
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* alloc memory for the gather ring
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* no need to alloc buf for the ring
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* gdr_tail, gdr_head and gdr_count are initialized by this function
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*/
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static u32 crypto4xx_build_pdr(struct crypto4xx_device *dev)
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{
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int i;
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struct pd_uinfo *pd_uinfo;
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dev->pdr = dma_alloc_coherent(dev->core_dev->device,
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sizeof(struct ce_pd) * PPC4XX_NUM_PD,
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&dev->pdr_pa, GFP_ATOMIC);
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if (!dev->pdr)
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return -ENOMEM;
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dev->pdr_uinfo = kzalloc(sizeof(struct pd_uinfo) * PPC4XX_NUM_PD,
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GFP_KERNEL);
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if (!dev->pdr_uinfo) {
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dma_free_coherent(dev->core_dev->device,
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sizeof(struct ce_pd) * PPC4XX_NUM_PD,
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dev->pdr,
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dev->pdr_pa);
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return -ENOMEM;
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}
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2017-08-25 21:47:24 +08:00
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memset(dev->pdr, 0, sizeof(struct ce_pd) * PPC4XX_NUM_PD);
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2009-02-05 13:18:13 +08:00
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dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device,
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256 * PPC4XX_NUM_PD,
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&dev->shadow_sa_pool_pa,
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GFP_ATOMIC);
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if (!dev->shadow_sa_pool)
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return -ENOMEM;
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dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device,
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sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
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&dev->shadow_sr_pool_pa, GFP_ATOMIC);
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if (!dev->shadow_sr_pool)
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return -ENOMEM;
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for (i = 0; i < PPC4XX_NUM_PD; i++) {
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pd_uinfo = (struct pd_uinfo *) (dev->pdr_uinfo +
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sizeof(struct pd_uinfo) * i);
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/* alloc 256 bytes which is enough for any kind of dynamic sa */
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pd_uinfo->sa_va = dev->shadow_sa_pool + 256 * i;
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pd_uinfo->sa_pa = dev->shadow_sa_pool_pa + 256 * i;
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/* alloc state record */
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pd_uinfo->sr_va = dev->shadow_sr_pool +
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sizeof(struct sa_state_record) * i;
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pd_uinfo->sr_pa = dev->shadow_sr_pool_pa +
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sizeof(struct sa_state_record) * i;
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}
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return 0;
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}
|
|
|
|
|
|
|
|
static void crypto4xx_destroy_pdr(struct crypto4xx_device *dev)
|
|
|
|
{
|
2017-08-25 21:47:24 +08:00
|
|
|
if (dev->pdr)
|
2009-02-05 13:18:13 +08:00
|
|
|
dma_free_coherent(dev->core_dev->device,
|
|
|
|
sizeof(struct ce_pd) * PPC4XX_NUM_PD,
|
|
|
|
dev->pdr, dev->pdr_pa);
|
2017-08-25 21:47:24 +08:00
|
|
|
|
2009-02-05 13:18:13 +08:00
|
|
|
if (dev->shadow_sa_pool)
|
|
|
|
dma_free_coherent(dev->core_dev->device, 256 * PPC4XX_NUM_PD,
|
|
|
|
dev->shadow_sa_pool, dev->shadow_sa_pool_pa);
|
2017-08-25 21:47:24 +08:00
|
|
|
|
2009-02-05 13:18:13 +08:00
|
|
|
if (dev->shadow_sr_pool)
|
|
|
|
dma_free_coherent(dev->core_dev->device,
|
|
|
|
sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
|
|
|
|
dev->shadow_sr_pool, dev->shadow_sr_pool_pa);
|
|
|
|
|
|
|
|
kfree(dev->pdr_uinfo);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 crypto4xx_get_pd_from_pdr_nolock(struct crypto4xx_device *dev)
|
|
|
|
{
|
|
|
|
u32 retval;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
retval = dev->pdr_head;
|
|
|
|
tmp = (dev->pdr_head + 1) % PPC4XX_NUM_PD;
|
|
|
|
|
|
|
|
if (tmp == dev->pdr_tail)
|
|
|
|
return ERING_WAS_FULL;
|
|
|
|
|
|
|
|
dev->pdr_head = tmp;
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx)
|
|
|
|
{
|
|
|
|
struct pd_uinfo *pd_uinfo;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
pd_uinfo = (struct pd_uinfo *)(dev->pdr_uinfo +
|
|
|
|
sizeof(struct pd_uinfo) * idx);
|
|
|
|
spin_lock_irqsave(&dev->core_dev->lock, flags);
|
|
|
|
if (dev->pdr_tail != PPC4XX_LAST_PD)
|
|
|
|
dev->pdr_tail++;
|
|
|
|
else
|
|
|
|
dev->pdr_tail = 0;
|
|
|
|
pd_uinfo->state = PD_ENTRY_FREE;
|
|
|
|
spin_unlock_irqrestore(&dev->core_dev->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ce_pd *crypto4xx_get_pdp(struct crypto4xx_device *dev,
|
|
|
|
dma_addr_t *pd_dma, u32 idx)
|
|
|
|
{
|
|
|
|
*pd_dma = dev->pdr_pa + sizeof(struct ce_pd) * idx;
|
|
|
|
|
|
|
|
return dev->pdr + sizeof(struct ce_pd) * idx;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* alloc memory for the gather ring
|
|
|
|
* no need to alloc buf for the ring
|
|
|
|
* gdr_tail, gdr_head and gdr_count are initialized by this function
|
|
|
|
*/
|
|
|
|
static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev)
|
|
|
|
{
|
|
|
|
dev->gdr = dma_alloc_coherent(dev->core_dev->device,
|
|
|
|
sizeof(struct ce_gd) * PPC4XX_NUM_GD,
|
|
|
|
&dev->gdr_pa, GFP_ATOMIC);
|
|
|
|
if (!dev->gdr)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
memset(dev->gdr, 0, sizeof(struct ce_gd) * PPC4XX_NUM_GD);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev)
|
|
|
|
{
|
|
|
|
dma_free_coherent(dev->core_dev->device,
|
|
|
|
sizeof(struct ce_gd) * PPC4XX_NUM_GD,
|
|
|
|
dev->gdr, dev->gdr_pa);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* when this function is called.
|
|
|
|
* preemption or interrupt must be disabled
|
|
|
|
*/
|
|
|
|
u32 crypto4xx_get_n_gd(struct crypto4xx_device *dev, int n)
|
|
|
|
{
|
|
|
|
u32 retval;
|
|
|
|
u32 tmp;
|
|
|
|
if (n >= PPC4XX_NUM_GD)
|
|
|
|
return ERING_WAS_FULL;
|
|
|
|
|
|
|
|
retval = dev->gdr_head;
|
|
|
|
tmp = (dev->gdr_head + n) % PPC4XX_NUM_GD;
|
|
|
|
if (dev->gdr_head > dev->gdr_tail) {
|
|
|
|
if (tmp < dev->gdr_head && tmp >= dev->gdr_tail)
|
|
|
|
return ERING_WAS_FULL;
|
|
|
|
} else if (dev->gdr_head < dev->gdr_tail) {
|
|
|
|
if (tmp < dev->gdr_head || tmp >= dev->gdr_tail)
|
|
|
|
return ERING_WAS_FULL;
|
|
|
|
}
|
|
|
|
dev->gdr_head = tmp;
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 crypto4xx_put_gd_to_gdr(struct crypto4xx_device *dev)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->core_dev->lock, flags);
|
|
|
|
if (dev->gdr_tail == dev->gdr_head) {
|
|
|
|
spin_unlock_irqrestore(&dev->core_dev->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->gdr_tail != PPC4XX_LAST_GD)
|
|
|
|
dev->gdr_tail++;
|
|
|
|
else
|
|
|
|
dev->gdr_tail = 0;
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev->core_dev->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct ce_gd *crypto4xx_get_gdp(struct crypto4xx_device *dev,
|
|
|
|
dma_addr_t *gd_dma, u32 idx)
|
|
|
|
{
|
|
|
|
*gd_dma = dev->gdr_pa + sizeof(struct ce_gd) * idx;
|
|
|
|
|
|
|
|
return (struct ce_gd *) (dev->gdr + sizeof(struct ce_gd) * idx);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* alloc memory for the scatter ring
|
|
|
|
* need to alloc buf for the ring
|
|
|
|
* sdr_tail, sdr_head and sdr_count are initialized by this function
|
|
|
|
*/
|
|
|
|
static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct ce_sd *sd_array;
|
|
|
|
|
|
|
|
/* alloc memory for scatter descriptor ring */
|
|
|
|
dev->sdr = dma_alloc_coherent(dev->core_dev->device,
|
|
|
|
sizeof(struct ce_sd) * PPC4XX_NUM_SD,
|
|
|
|
&dev->sdr_pa, GFP_ATOMIC);
|
|
|
|
if (!dev->sdr)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
dev->scatter_buffer_va =
|
|
|
|
dma_alloc_coherent(dev->core_dev->device,
|
2017-08-25 21:47:23 +08:00
|
|
|
PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD,
|
2009-02-05 13:18:13 +08:00
|
|
|
&dev->scatter_buffer_pa, GFP_ATOMIC);
|
|
|
|
if (!dev->scatter_buffer_va) {
|
|
|
|
dma_free_coherent(dev->core_dev->device,
|
|
|
|
sizeof(struct ce_sd) * PPC4XX_NUM_SD,
|
|
|
|
dev->sdr, dev->sdr_pa);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
sd_array = dev->sdr;
|
|
|
|
|
|
|
|
for (i = 0; i < PPC4XX_NUM_SD; i++) {
|
|
|
|
sd_array[i].ptr = dev->scatter_buffer_pa +
|
2017-08-25 21:47:23 +08:00
|
|
|
PPC4XX_SD_BUFFER_SIZE * i;
|
2009-02-05 13:18:13 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void crypto4xx_destroy_sdr(struct crypto4xx_device *dev)
|
|
|
|
{
|
2017-08-25 21:47:24 +08:00
|
|
|
if (dev->sdr)
|
2009-02-05 13:18:13 +08:00
|
|
|
dma_free_coherent(dev->core_dev->device,
|
|
|
|
sizeof(struct ce_sd) * PPC4XX_NUM_SD,
|
|
|
|
dev->sdr, dev->sdr_pa);
|
|
|
|
|
2017-08-25 21:47:24 +08:00
|
|
|
if (dev->scatter_buffer_va)
|
2009-02-05 13:18:13 +08:00
|
|
|
dma_free_coherent(dev->core_dev->device,
|
2017-08-25 21:47:23 +08:00
|
|
|
PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD,
|
2009-02-05 13:18:13 +08:00
|
|
|
dev->scatter_buffer_va,
|
|
|
|
dev->scatter_buffer_pa);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* when this function is called.
|
|
|
|
* preemption or interrupt must be disabled
|
|
|
|
*/
|
|
|
|
static u32 crypto4xx_get_n_sd(struct crypto4xx_device *dev, int n)
|
|
|
|
{
|
|
|
|
u32 retval;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
if (n >= PPC4XX_NUM_SD)
|
|
|
|
return ERING_WAS_FULL;
|
|
|
|
|
|
|
|
retval = dev->sdr_head;
|
|
|
|
tmp = (dev->sdr_head + n) % PPC4XX_NUM_SD;
|
|
|
|
if (dev->sdr_head > dev->gdr_tail) {
|
|
|
|
if (tmp < dev->sdr_head && tmp >= dev->sdr_tail)
|
|
|
|
return ERING_WAS_FULL;
|
|
|
|
} else if (dev->sdr_head < dev->sdr_tail) {
|
|
|
|
if (tmp < dev->sdr_head || tmp >= dev->sdr_tail)
|
|
|
|
return ERING_WAS_FULL;
|
|
|
|
} /* the head = tail, or empty case is already take cared */
|
|
|
|
dev->sdr_head = tmp;
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 crypto4xx_put_sd_to_sdr(struct crypto4xx_device *dev)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->core_dev->lock, flags);
|
|
|
|
if (dev->sdr_tail == dev->sdr_head) {
|
|
|
|
spin_unlock_irqrestore(&dev->core_dev->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if (dev->sdr_tail != PPC4XX_LAST_SD)
|
|
|
|
dev->sdr_tail++;
|
|
|
|
else
|
|
|
|
dev->sdr_tail = 0;
|
|
|
|
spin_unlock_irqrestore(&dev->core_dev->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct ce_sd *crypto4xx_get_sdp(struct crypto4xx_device *dev,
|
|
|
|
dma_addr_t *sd_dma, u32 idx)
|
|
|
|
{
|
|
|
|
*sd_dma = dev->sdr_pa + sizeof(struct ce_sd) * idx;
|
|
|
|
|
|
|
|
return (struct ce_sd *)(dev->sdr + sizeof(struct ce_sd) * idx);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev,
|
|
|
|
struct ce_pd *pd,
|
|
|
|
struct pd_uinfo *pd_uinfo,
|
|
|
|
u32 nbytes,
|
|
|
|
struct scatterlist *dst)
|
|
|
|
{
|
2017-08-25 21:47:22 +08:00
|
|
|
unsigned int first_sd = pd_uinfo->first_sd;
|
|
|
|
unsigned int last_sd;
|
|
|
|
unsigned int overflow = 0;
|
|
|
|
unsigned int to_copy;
|
|
|
|
unsigned int dst_start = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Because the scatter buffers are all neatly organized in one
|
|
|
|
* big continuous ringbuffer; scatterwalk_map_and_copy() can
|
|
|
|
* be instructed to copy a range of buffers in one go.
|
|
|
|
*/
|
|
|
|
|
|
|
|
last_sd = (first_sd + pd_uinfo->num_sd);
|
|
|
|
if (last_sd > PPC4XX_LAST_SD) {
|
|
|
|
last_sd = PPC4XX_LAST_SD;
|
|
|
|
overflow = last_sd % PPC4XX_NUM_SD;
|
|
|
|
}
|
2009-02-05 13:18:13 +08:00
|
|
|
|
|
|
|
while (nbytes) {
|
2017-08-25 21:47:22 +08:00
|
|
|
void *buf = dev->scatter_buffer_va +
|
|
|
|
first_sd * PPC4XX_SD_BUFFER_SIZE;
|
|
|
|
|
|
|
|
to_copy = min(nbytes, PPC4XX_SD_BUFFER_SIZE *
|
|
|
|
(1 + last_sd - first_sd));
|
|
|
|
scatterwalk_map_and_copy(buf, dst, dst_start, to_copy, 1);
|
|
|
|
nbytes -= to_copy;
|
|
|
|
|
|
|
|
if (overflow) {
|
|
|
|
first_sd = 0;
|
|
|
|
last_sd = overflow;
|
|
|
|
dst_start += to_copy;
|
|
|
|
overflow = 0;
|
2009-02-05 13:18:13 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 crypto4xx_copy_digest_to_dst(struct pd_uinfo *pd_uinfo,
|
|
|
|
struct crypto4xx_ctx *ctx)
|
|
|
|
{
|
|
|
|
struct dynamic_sa_ctl *sa = (struct dynamic_sa_ctl *) ctx->sa_in;
|
|
|
|
struct sa_state_record *state_record =
|
|
|
|
(struct sa_state_record *) pd_uinfo->sr_va;
|
|
|
|
|
|
|
|
if (sa->sa_command_0.bf.hash_alg == SA_HASH_ALG_SHA1) {
|
|
|
|
memcpy((void *) pd_uinfo->dest_va, state_record->save_digest,
|
|
|
|
SA_HASH_ALG_SHA1_DIGEST_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void crypto4xx_ret_sg_desc(struct crypto4xx_device *dev,
|
|
|
|
struct pd_uinfo *pd_uinfo)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
if (pd_uinfo->num_gd) {
|
|
|
|
for (i = 0; i < pd_uinfo->num_gd; i++)
|
|
|
|
crypto4xx_put_gd_to_gdr(dev);
|
|
|
|
pd_uinfo->first_gd = 0xffffffff;
|
|
|
|
pd_uinfo->num_gd = 0;
|
|
|
|
}
|
|
|
|
if (pd_uinfo->num_sd) {
|
|
|
|
for (i = 0; i < pd_uinfo->num_sd; i++)
|
|
|
|
crypto4xx_put_sd_to_sdr(dev);
|
|
|
|
|
|
|
|
pd_uinfo->first_sd = 0xffffffff;
|
|
|
|
pd_uinfo->num_sd = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 crypto4xx_ablkcipher_done(struct crypto4xx_device *dev,
|
|
|
|
struct pd_uinfo *pd_uinfo,
|
|
|
|
struct ce_pd *pd)
|
|
|
|
{
|
|
|
|
struct crypto4xx_ctx *ctx;
|
|
|
|
struct ablkcipher_request *ablk_req;
|
|
|
|
struct scatterlist *dst;
|
|
|
|
dma_addr_t addr;
|
|
|
|
|
|
|
|
ablk_req = ablkcipher_request_cast(pd_uinfo->async_req);
|
|
|
|
ctx = crypto_tfm_ctx(ablk_req->base.tfm);
|
|
|
|
|
|
|
|
if (pd_uinfo->using_sd) {
|
|
|
|
crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo, ablk_req->nbytes,
|
|
|
|
ablk_req->dst);
|
|
|
|
} else {
|
|
|
|
dst = pd_uinfo->dest_va;
|
|
|
|
addr = dma_map_page(dev->core_dev->device, sg_page(dst),
|
|
|
|
dst->offset, dst->length, DMA_FROM_DEVICE);
|
|
|
|
}
|
|
|
|
crypto4xx_ret_sg_desc(dev, pd_uinfo);
|
|
|
|
if (ablk_req->base.complete != NULL)
|
|
|
|
ablk_req->base.complete(&ablk_req->base, 0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 crypto4xx_ahash_done(struct crypto4xx_device *dev,
|
|
|
|
struct pd_uinfo *pd_uinfo)
|
|
|
|
{
|
|
|
|
struct crypto4xx_ctx *ctx;
|
|
|
|
struct ahash_request *ahash_req;
|
|
|
|
|
|
|
|
ahash_req = ahash_request_cast(pd_uinfo->async_req);
|
|
|
|
ctx = crypto_tfm_ctx(ahash_req->base.tfm);
|
|
|
|
|
|
|
|
crypto4xx_copy_digest_to_dst(pd_uinfo,
|
|
|
|
crypto_tfm_ctx(ahash_req->base.tfm));
|
|
|
|
crypto4xx_ret_sg_desc(dev, pd_uinfo);
|
|
|
|
/* call user provided callback function x */
|
|
|
|
if (ahash_req->base.complete != NULL)
|
|
|
|
ahash_req->base.complete(&ahash_req->base, 0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
|
|
|
|
{
|
|
|
|
struct ce_pd *pd;
|
|
|
|
struct pd_uinfo *pd_uinfo;
|
|
|
|
|
|
|
|
pd = dev->pdr + sizeof(struct ce_pd)*idx;
|
|
|
|
pd_uinfo = dev->pdr_uinfo + sizeof(struct pd_uinfo)*idx;
|
|
|
|
if (crypto_tfm_alg_type(pd_uinfo->async_req->tfm) ==
|
|
|
|
CRYPTO_ALG_TYPE_ABLKCIPHER)
|
|
|
|
return crypto4xx_ablkcipher_done(dev, pd_uinfo, pd);
|
|
|
|
else
|
|
|
|
return crypto4xx_ahash_done(dev, pd_uinfo);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Note: Only use this function to copy items that is word aligned.
|
|
|
|
*/
|
|
|
|
void crypto4xx_memcpy_le(unsigned int *dst,
|
|
|
|
const unsigned char *buf,
|
|
|
|
int len)
|
|
|
|
{
|
|
|
|
u8 *tmp;
|
|
|
|
for (; len >= 4; buf += 4, len -= 4)
|
|
|
|
*dst++ = cpu_to_le32(*(unsigned int *) buf);
|
|
|
|
|
|
|
|
tmp = (u8 *)dst;
|
|
|
|
switch (len) {
|
|
|
|
case 3:
|
|
|
|
*tmp++ = 0;
|
|
|
|
*tmp++ = *(buf+2);
|
|
|
|
*tmp++ = *(buf+1);
|
|
|
|
*tmp++ = *buf;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
*tmp++ = 0;
|
|
|
|
*tmp++ = 0;
|
|
|
|
*tmp++ = *(buf+1);
|
|
|
|
*tmp++ = *buf;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
*tmp++ = 0;
|
|
|
|
*tmp++ = 0;
|
|
|
|
*tmp++ = 0;
|
|
|
|
*tmp++ = *buf;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void crypto4xx_stop_all(struct crypto4xx_core_device *core_dev)
|
|
|
|
{
|
|
|
|
crypto4xx_destroy_pdr(core_dev->dev);
|
|
|
|
crypto4xx_destroy_gdr(core_dev->dev);
|
|
|
|
crypto4xx_destroy_sdr(core_dev->dev);
|
|
|
|
iounmap(core_dev->dev->ce_base);
|
|
|
|
kfree(core_dev->dev);
|
|
|
|
kfree(core_dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
void crypto4xx_return_pd(struct crypto4xx_device *dev,
|
|
|
|
u32 pd_entry, struct ce_pd *pd,
|
|
|
|
struct pd_uinfo *pd_uinfo)
|
|
|
|
{
|
|
|
|
/* irq should be already disabled */
|
|
|
|
dev->pdr_head = pd_entry;
|
|
|
|
pd->pd_ctl.w = 0;
|
|
|
|
pd->pd_ctl_len.w = 0;
|
|
|
|
pd_uinfo->state = PD_ENTRY_FREE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 get_next_gd(u32 current)
|
|
|
|
{
|
|
|
|
if (current != PPC4XX_LAST_GD)
|
|
|
|
return current + 1;
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 get_next_sd(u32 current)
|
|
|
|
{
|
|
|
|
if (current != PPC4XX_LAST_SD)
|
|
|
|
return current + 1;
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 crypto4xx_build_pd(struct crypto_async_request *req,
|
|
|
|
struct crypto4xx_ctx *ctx,
|
|
|
|
struct scatterlist *src,
|
|
|
|
struct scatterlist *dst,
|
|
|
|
unsigned int datalen,
|
|
|
|
void *iv, u32 iv_len)
|
|
|
|
{
|
|
|
|
struct crypto4xx_device *dev = ctx->dev;
|
|
|
|
dma_addr_t addr, pd_dma, sd_dma, gd_dma;
|
|
|
|
struct dynamic_sa_ctl *sa;
|
|
|
|
struct scatterlist *sg;
|
|
|
|
struct ce_gd *gd;
|
|
|
|
struct ce_pd *pd;
|
|
|
|
u32 num_gd, num_sd;
|
|
|
|
u32 fst_gd = 0xffffffff;
|
|
|
|
u32 fst_sd = 0xffffffff;
|
|
|
|
u32 pd_entry;
|
|
|
|
unsigned long flags;
|
|
|
|
struct pd_uinfo *pd_uinfo = NULL;
|
|
|
|
unsigned int nbytes = datalen, idx;
|
|
|
|
unsigned int ivlen = 0;
|
|
|
|
u32 gd_idx = 0;
|
|
|
|
|
|
|
|
/* figure how many gd is needed */
|
2015-09-18 20:57:10 +08:00
|
|
|
num_gd = sg_nents_for_len(src, datalen);
|
2015-11-05 04:13:39 +08:00
|
|
|
if ((int)num_gd < 0) {
|
|
|
|
dev_err(dev->core_dev->device, "Invalid number of src SG.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2009-02-05 13:18:13 +08:00
|
|
|
if (num_gd == 1)
|
|
|
|
num_gd = 0;
|
|
|
|
|
|
|
|
/* figure how many sd is needed */
|
|
|
|
if (sg_is_last(dst) || ctx->is_hash) {
|
|
|
|
num_sd = 0;
|
|
|
|
} else {
|
|
|
|
if (datalen > PPC4XX_SD_BUFFER_SIZE) {
|
|
|
|
num_sd = datalen / PPC4XX_SD_BUFFER_SIZE;
|
|
|
|
if (datalen % PPC4XX_SD_BUFFER_SIZE)
|
|
|
|
num_sd++;
|
|
|
|
} else {
|
|
|
|
num_sd = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The follow section of code needs to be protected
|
|
|
|
* The gather ring and scatter ring needs to be consecutive
|
|
|
|
* In case of run out of any kind of descriptor, the descriptor
|
|
|
|
* already got must be return the original place.
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&dev->core_dev->lock, flags);
|
|
|
|
if (num_gd) {
|
|
|
|
fst_gd = crypto4xx_get_n_gd(dev, num_gd);
|
|
|
|
if (fst_gd == ERING_WAS_FULL) {
|
|
|
|
spin_unlock_irqrestore(&dev->core_dev->lock, flags);
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (num_sd) {
|
|
|
|
fst_sd = crypto4xx_get_n_sd(dev, num_sd);
|
|
|
|
if (fst_sd == ERING_WAS_FULL) {
|
|
|
|
if (num_gd)
|
|
|
|
dev->gdr_head = fst_gd;
|
|
|
|
spin_unlock_irqrestore(&dev->core_dev->lock, flags);
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
pd_entry = crypto4xx_get_pd_from_pdr_nolock(dev);
|
|
|
|
if (pd_entry == ERING_WAS_FULL) {
|
|
|
|
if (num_gd)
|
|
|
|
dev->gdr_head = fst_gd;
|
|
|
|
if (num_sd)
|
|
|
|
dev->sdr_head = fst_sd;
|
|
|
|
spin_unlock_irqrestore(&dev->core_dev->lock, flags);
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev->core_dev->lock, flags);
|
|
|
|
|
|
|
|
pd_uinfo = (struct pd_uinfo *)(dev->pdr_uinfo +
|
|
|
|
sizeof(struct pd_uinfo) * pd_entry);
|
|
|
|
pd = crypto4xx_get_pdp(dev, &pd_dma, pd_entry);
|
|
|
|
pd_uinfo->async_req = req;
|
|
|
|
pd_uinfo->num_gd = num_gd;
|
|
|
|
pd_uinfo->num_sd = num_sd;
|
|
|
|
|
|
|
|
if (iv_len || ctx->is_hash) {
|
|
|
|
ivlen = iv_len;
|
|
|
|
pd->sa = pd_uinfo->sa_pa;
|
|
|
|
sa = (struct dynamic_sa_ctl *) pd_uinfo->sa_va;
|
|
|
|
if (ctx->direction == DIR_INBOUND)
|
|
|
|
memcpy(sa, ctx->sa_in, ctx->sa_len * 4);
|
|
|
|
else
|
|
|
|
memcpy(sa, ctx->sa_out, ctx->sa_len * 4);
|
|
|
|
|
|
|
|
memcpy((void *) sa + ctx->offset_to_sr_ptr,
|
|
|
|
&pd_uinfo->sr_pa, 4);
|
|
|
|
|
|
|
|
if (iv_len)
|
|
|
|
crypto4xx_memcpy_le(pd_uinfo->sr_va, iv, iv_len);
|
|
|
|
} else {
|
|
|
|
if (ctx->direction == DIR_INBOUND) {
|
|
|
|
pd->sa = ctx->sa_in_dma_addr;
|
|
|
|
sa = (struct dynamic_sa_ctl *) ctx->sa_in;
|
|
|
|
} else {
|
|
|
|
pd->sa = ctx->sa_out_dma_addr;
|
|
|
|
sa = (struct dynamic_sa_ctl *) ctx->sa_out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
pd->sa_len = ctx->sa_len;
|
|
|
|
if (num_gd) {
|
|
|
|
/* get first gd we are going to use */
|
|
|
|
gd_idx = fst_gd;
|
|
|
|
pd_uinfo->first_gd = fst_gd;
|
|
|
|
pd_uinfo->num_gd = num_gd;
|
|
|
|
gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
|
|
|
|
pd->src = gd_dma;
|
|
|
|
/* enable gather */
|
|
|
|
sa->sa_command_0.bf.gather = 1;
|
|
|
|
idx = 0;
|
|
|
|
src = &src[0];
|
|
|
|
/* walk the sg, and setup gather array */
|
|
|
|
while (nbytes) {
|
|
|
|
sg = &src[idx];
|
|
|
|
addr = dma_map_page(dev->core_dev->device, sg_page(sg),
|
|
|
|
sg->offset, sg->length, DMA_TO_DEVICE);
|
|
|
|
gd->ptr = addr;
|
|
|
|
gd->ctl_len.len = sg->length;
|
|
|
|
gd->ctl_len.done = 0;
|
|
|
|
gd->ctl_len.ready = 1;
|
|
|
|
if (sg->length >= nbytes)
|
|
|
|
break;
|
|
|
|
nbytes -= sg->length;
|
|
|
|
gd_idx = get_next_gd(gd_idx);
|
|
|
|
gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
|
|
|
|
idx++;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
pd->src = (u32)dma_map_page(dev->core_dev->device, sg_page(src),
|
|
|
|
src->offset, src->length, DMA_TO_DEVICE);
|
|
|
|
/*
|
|
|
|
* Disable gather in sa command
|
|
|
|
*/
|
|
|
|
sa->sa_command_0.bf.gather = 0;
|
|
|
|
/*
|
|
|
|
* Indicate gather array is not used
|
|
|
|
*/
|
|
|
|
pd_uinfo->first_gd = 0xffffffff;
|
|
|
|
pd_uinfo->num_gd = 0;
|
|
|
|
}
|
|
|
|
if (ctx->is_hash || sg_is_last(dst)) {
|
|
|
|
/*
|
|
|
|
* we know application give us dst a whole piece of memory
|
|
|
|
* no need to use scatter ring.
|
|
|
|
* In case of is_hash, the icv is always at end of src data.
|
|
|
|
*/
|
|
|
|
pd_uinfo->using_sd = 0;
|
|
|
|
pd_uinfo->first_sd = 0xffffffff;
|
|
|
|
pd_uinfo->num_sd = 0;
|
|
|
|
pd_uinfo->dest_va = dst;
|
|
|
|
sa->sa_command_0.bf.scatter = 0;
|
|
|
|
if (ctx->is_hash)
|
|
|
|
pd->dest = virt_to_phys((void *)dst);
|
|
|
|
else
|
|
|
|
pd->dest = (u32)dma_map_page(dev->core_dev->device,
|
|
|
|
sg_page(dst), dst->offset,
|
|
|
|
dst->length, DMA_TO_DEVICE);
|
|
|
|
} else {
|
|
|
|
struct ce_sd *sd = NULL;
|
|
|
|
u32 sd_idx = fst_sd;
|
|
|
|
nbytes = datalen;
|
|
|
|
sa->sa_command_0.bf.scatter = 1;
|
|
|
|
pd_uinfo->using_sd = 1;
|
|
|
|
pd_uinfo->dest_va = dst;
|
|
|
|
pd_uinfo->first_sd = fst_sd;
|
|
|
|
pd_uinfo->num_sd = num_sd;
|
|
|
|
sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
|
|
|
|
pd->dest = sd_dma;
|
|
|
|
/* setup scatter descriptor */
|
|
|
|
sd->ctl.done = 0;
|
|
|
|
sd->ctl.rdy = 1;
|
|
|
|
/* sd->ptr should be setup by sd_init routine*/
|
|
|
|
idx = 0;
|
|
|
|
if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
|
|
|
|
nbytes -= PPC4XX_SD_BUFFER_SIZE;
|
|
|
|
else
|
|
|
|
nbytes = 0;
|
|
|
|
while (nbytes) {
|
|
|
|
sd_idx = get_next_sd(sd_idx);
|
|
|
|
sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
|
|
|
|
/* setup scatter descriptor */
|
|
|
|
sd->ctl.done = 0;
|
|
|
|
sd->ctl.rdy = 1;
|
|
|
|
if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
|
|
|
|
nbytes -= PPC4XX_SD_BUFFER_SIZE;
|
|
|
|
else
|
|
|
|
/*
|
|
|
|
* SD entry can hold PPC4XX_SD_BUFFER_SIZE,
|
|
|
|
* which is more than nbytes, so done.
|
|
|
|
*/
|
|
|
|
nbytes = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
sa->sa_command_1.bf.hash_crypto_offset = 0;
|
|
|
|
pd->pd_ctl.w = ctx->pd_ctl;
|
2017-08-25 21:47:15 +08:00
|
|
|
pd->pd_ctl_len.w = 0x00400000 | datalen;
|
2009-02-05 13:18:13 +08:00
|
|
|
pd_uinfo->state = PD_ENTRY_INUSE;
|
|
|
|
wmb();
|
|
|
|
/* write any value to push engine to read a pd */
|
|
|
|
writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
|
|
|
|
return -EINPROGRESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Algorithm Registration Functions
|
|
|
|
*/
|
|
|
|
static int crypto4xx_alg_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct crypto_alg *alg = tfm->__crt_alg;
|
|
|
|
struct crypto4xx_alg *amcc_alg = crypto_alg_to_crypto4xx_alg(alg);
|
|
|
|
struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
|
|
|
|
ctx->dev = amcc_alg->dev;
|
|
|
|
ctx->sa_in = NULL;
|
|
|
|
ctx->sa_out = NULL;
|
|
|
|
ctx->sa_in_dma_addr = 0;
|
|
|
|
ctx->sa_out_dma_addr = 0;
|
|
|
|
ctx->sa_len = 0;
|
|
|
|
|
2009-07-14 20:21:46 +08:00
|
|
|
switch (alg->cra_flags & CRYPTO_ALG_TYPE_MASK) {
|
|
|
|
default:
|
2009-02-05 13:18:13 +08:00
|
|
|
tfm->crt_ablkcipher.reqsize = sizeof(struct crypto4xx_ctx);
|
2009-07-14 20:21:46 +08:00
|
|
|
break;
|
|
|
|
case CRYPTO_ALG_TYPE_AHASH:
|
2009-07-12 23:08:28 +08:00
|
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
|
|
|
sizeof(struct crypto4xx_ctx));
|
2009-07-14 20:21:46 +08:00
|
|
|
break;
|
|
|
|
}
|
2009-02-05 13:18:13 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void crypto4xx_alg_exit(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
|
|
|
|
crypto4xx_free_sa(ctx);
|
|
|
|
crypto4xx_free_state_record(ctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
int crypto4xx_register_alg(struct crypto4xx_device *sec_dev,
|
2009-07-14 20:21:46 +08:00
|
|
|
struct crypto4xx_alg_common *crypto_alg,
|
|
|
|
int array_size)
|
2009-02-05 13:18:13 +08:00
|
|
|
{
|
|
|
|
struct crypto4xx_alg *alg;
|
|
|
|
int i;
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < array_size; i++) {
|
|
|
|
alg = kzalloc(sizeof(struct crypto4xx_alg), GFP_KERNEL);
|
|
|
|
if (!alg)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
alg->alg = crypto_alg[i];
|
|
|
|
alg->dev = sec_dev;
|
2009-07-14 20:21:46 +08:00
|
|
|
|
|
|
|
switch (alg->alg.type) {
|
|
|
|
case CRYPTO_ALG_TYPE_AHASH:
|
|
|
|
rc = crypto_register_ahash(&alg->alg.u.hash);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
rc = crypto_register_alg(&alg->alg.u.cipher);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-08-25 21:47:14 +08:00
|
|
|
if (rc)
|
2009-02-05 13:18:13 +08:00
|
|
|
kfree(alg);
|
2017-08-25 21:47:14 +08:00
|
|
|
else
|
2009-02-05 13:18:13 +08:00
|
|
|
list_add_tail(&alg->entry, &sec_dev->alg_list);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void crypto4xx_unregister_alg(struct crypto4xx_device *sec_dev)
|
|
|
|
{
|
|
|
|
struct crypto4xx_alg *alg, *tmp;
|
|
|
|
|
|
|
|
list_for_each_entry_safe(alg, tmp, &sec_dev->alg_list, entry) {
|
|
|
|
list_del(&alg->entry);
|
2009-07-14 20:21:46 +08:00
|
|
|
switch (alg->alg.type) {
|
|
|
|
case CRYPTO_ALG_TYPE_AHASH:
|
|
|
|
crypto_unregister_ahash(&alg->alg.u.hash);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
crypto_unregister_alg(&alg->alg.u.cipher);
|
|
|
|
}
|
2009-02-05 13:18:13 +08:00
|
|
|
kfree(alg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void crypto4xx_bh_tasklet_cb(unsigned long data)
|
|
|
|
{
|
|
|
|
struct device *dev = (struct device *)data;
|
|
|
|
struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
|
|
|
|
struct pd_uinfo *pd_uinfo;
|
|
|
|
struct ce_pd *pd;
|
|
|
|
u32 tail;
|
|
|
|
|
|
|
|
while (core_dev->dev->pdr_head != core_dev->dev->pdr_tail) {
|
|
|
|
tail = core_dev->dev->pdr_tail;
|
|
|
|
pd_uinfo = core_dev->dev->pdr_uinfo +
|
|
|
|
sizeof(struct pd_uinfo)*tail;
|
|
|
|
pd = core_dev->dev->pdr + sizeof(struct ce_pd) * tail;
|
|
|
|
if ((pd_uinfo->state == PD_ENTRY_INUSE) &&
|
|
|
|
pd->pd_ctl.bf.pe_done &&
|
|
|
|
!pd->pd_ctl.bf.host_ready) {
|
|
|
|
pd->pd_ctl.bf.pe_done = 0;
|
|
|
|
crypto4xx_pd_done(core_dev->dev, tail);
|
|
|
|
crypto4xx_put_pd_to_pdr(core_dev->dev, tail);
|
|
|
|
} else {
|
|
|
|
/* if tail not done, break */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Top Half of isr.
|
|
|
|
*/
|
|
|
|
static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct device *dev = (struct device *)data;
|
|
|
|
struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
|
|
|
|
|
2015-08-14 11:09:29 +08:00
|
|
|
if (!core_dev->dev->ce_base)
|
2009-02-05 13:18:13 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
writel(PPC4XX_INTERRUPT_CLR,
|
|
|
|
core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
|
|
|
|
tasklet_schedule(&core_dev->tasklet);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Supported Crypto Algorithms
|
|
|
|
*/
|
2009-07-14 20:21:46 +08:00
|
|
|
struct crypto4xx_alg_common crypto4xx_alg[] = {
|
2009-02-05 13:18:13 +08:00
|
|
|
/* Crypto AES modes */
|
2009-07-14 20:21:46 +08:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = {
|
2009-02-05 13:18:13 +08:00
|
|
|
.cra_name = "cbc(aes)",
|
|
|
|
.cra_driver_name = "cbc-aes-ppc4xx",
|
|
|
|
.cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
|
2017-08-25 21:47:16 +08:00
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
|
|
CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
2009-02-05 13:18:13 +08:00
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct crypto4xx_ctx),
|
|
|
|
.cra_type = &crypto_ablkcipher_type,
|
2009-07-14 20:21:46 +08:00
|
|
|
.cra_init = crypto4xx_alg_init,
|
|
|
|
.cra_exit = crypto4xx_alg_exit,
|
2009-02-05 13:18:13 +08:00
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_u = {
|
|
|
|
.ablkcipher = {
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_IV_SIZE,
|
|
|
|
.setkey = crypto4xx_setkey_aes_cbc,
|
|
|
|
.encrypt = crypto4xx_encrypt,
|
|
|
|
.decrypt = crypto4xx_decrypt,
|
|
|
|
}
|
|
|
|
}
|
2009-07-14 20:21:46 +08:00
|
|
|
}},
|
2017-08-25 21:47:21 +08:00
|
|
|
{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = {
|
|
|
|
.cra_name = "cfb(aes)",
|
|
|
|
.cra_driver_name = "cfb-aes-ppc4xx",
|
|
|
|
.cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
|
|
CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct crypto4xx_ctx),
|
|
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
|
|
.cra_init = crypto4xx_alg_init,
|
|
|
|
.cra_exit = crypto4xx_alg_exit,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_u = {
|
|
|
|
.ablkcipher = {
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_IV_SIZE,
|
|
|
|
.setkey = crypto4xx_setkey_aes_cfb,
|
|
|
|
.encrypt = crypto4xx_encrypt,
|
|
|
|
.decrypt = crypto4xx_decrypt,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} },
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = {
|
|
|
|
.cra_name = "rfc3686(ctr(aes))",
|
|
|
|
.cra_driver_name = "rfc3686-ctr-aes-ppc4xx",
|
|
|
|
.cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
|
|
CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct crypto4xx_ctx),
|
|
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
|
|
.cra_init = crypto4xx_alg_init,
|
|
|
|
.cra_exit = crypto4xx_alg_exit,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_u = {
|
|
|
|
.ablkcipher = {
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE +
|
|
|
|
CTR_RFC3686_NONCE_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE +
|
|
|
|
CTR_RFC3686_NONCE_SIZE,
|
|
|
|
.ivsize = CTR_RFC3686_IV_SIZE,
|
|
|
|
.setkey = crypto4xx_setkey_rfc3686,
|
|
|
|
.encrypt = crypto4xx_rfc3686_encrypt,
|
|
|
|
.decrypt = crypto4xx_rfc3686_decrypt,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} },
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = {
|
|
|
|
.cra_name = "ecb(aes)",
|
|
|
|
.cra_driver_name = "ecb-aes-ppc4xx",
|
|
|
|
.cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
|
|
CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct crypto4xx_ctx),
|
|
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
|
|
.cra_init = crypto4xx_alg_init,
|
|
|
|
.cra_exit = crypto4xx_alg_exit,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_u = {
|
|
|
|
.ablkcipher = {
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.setkey = crypto4xx_setkey_aes_ecb,
|
|
|
|
.encrypt = crypto4xx_encrypt,
|
|
|
|
.decrypt = crypto4xx_decrypt,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} },
|
|
|
|
{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = {
|
|
|
|
.cra_name = "ofb(aes)",
|
|
|
|
.cra_driver_name = "ofb-aes-ppc4xx",
|
|
|
|
.cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
|
|
CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct crypto4xx_ctx),
|
|
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
|
|
.cra_init = crypto4xx_alg_init,
|
|
|
|
.cra_exit = crypto4xx_alg_exit,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_u = {
|
|
|
|
.ablkcipher = {
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_IV_SIZE,
|
|
|
|
.setkey = crypto4xx_setkey_aes_cbc,
|
|
|
|
.encrypt = crypto4xx_encrypt,
|
|
|
|
.decrypt = crypto4xx_decrypt,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} },
|
2009-02-05 13:18:13 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Module Initialization Routine
|
|
|
|
*/
|
2015-03-10 04:35:39 +08:00
|
|
|
static int crypto4xx_probe(struct platform_device *ofdev)
|
2009-02-05 13:18:13 +08:00
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
struct resource res;
|
|
|
|
struct device *dev = &ofdev->dev;
|
|
|
|
struct crypto4xx_core_device *core_dev;
|
|
|
|
|
2010-06-03 08:53:18 +08:00
|
|
|
rc = of_address_to_resource(ofdev->dev.of_node, 0, &res);
|
2009-02-05 13:18:13 +08:00
|
|
|
if (rc)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
if (of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto")) {
|
|
|
|
mtdcri(SDR0, PPC460EX_SDR0_SRST,
|
|
|
|
mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET);
|
|
|
|
mtdcri(SDR0, PPC460EX_SDR0_SRST,
|
|
|
|
mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET);
|
|
|
|
} else if (of_find_compatible_node(NULL, NULL,
|
|
|
|
"amcc,ppc405ex-crypto")) {
|
|
|
|
mtdcri(SDR0, PPC405EX_SDR0_SRST,
|
|
|
|
mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET);
|
|
|
|
mtdcri(SDR0, PPC405EX_SDR0_SRST,
|
|
|
|
mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET);
|
|
|
|
} else if (of_find_compatible_node(NULL, NULL,
|
|
|
|
"amcc,ppc460sx-crypto")) {
|
|
|
|
mtdcri(SDR0, PPC460SX_SDR0_SRST,
|
|
|
|
mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET);
|
|
|
|
mtdcri(SDR0, PPC460SX_SDR0_SRST,
|
|
|
|
mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET);
|
|
|
|
} else {
|
|
|
|
printk(KERN_ERR "Crypto Function Not supported!\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
core_dev = kzalloc(sizeof(struct crypto4xx_core_device), GFP_KERNEL);
|
|
|
|
if (!core_dev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
dev_set_drvdata(dev, core_dev);
|
|
|
|
core_dev->ofdev = ofdev;
|
|
|
|
core_dev->dev = kzalloc(sizeof(struct crypto4xx_device), GFP_KERNEL);
|
2017-06-10 20:54:33 +08:00
|
|
|
rc = -ENOMEM;
|
2009-02-05 13:18:13 +08:00
|
|
|
if (!core_dev->dev)
|
|
|
|
goto err_alloc_dev;
|
|
|
|
|
|
|
|
core_dev->dev->core_dev = core_dev;
|
|
|
|
core_dev->device = dev;
|
|
|
|
spin_lock_init(&core_dev->lock);
|
|
|
|
INIT_LIST_HEAD(&core_dev->dev->alg_list);
|
|
|
|
rc = crypto4xx_build_pdr(core_dev->dev);
|
|
|
|
if (rc)
|
|
|
|
goto err_build_pdr;
|
|
|
|
|
|
|
|
rc = crypto4xx_build_gdr(core_dev->dev);
|
|
|
|
if (rc)
|
2017-08-25 21:47:24 +08:00
|
|
|
goto err_build_pdr;
|
2009-02-05 13:18:13 +08:00
|
|
|
|
|
|
|
rc = crypto4xx_build_sdr(core_dev->dev);
|
|
|
|
if (rc)
|
|
|
|
goto err_build_sdr;
|
|
|
|
|
|
|
|
/* Init tasklet for bottom half processing */
|
|
|
|
tasklet_init(&core_dev->tasklet, crypto4xx_bh_tasklet_cb,
|
|
|
|
(unsigned long) dev);
|
|
|
|
|
|
|
|
/* Register for Crypto isr, Crypto Engine IRQ */
|
2010-06-03 08:53:18 +08:00
|
|
|
core_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
|
2009-02-05 13:18:13 +08:00
|
|
|
rc = request_irq(core_dev->irq, crypto4xx_ce_interrupt_handler, 0,
|
|
|
|
core_dev->dev->name, dev);
|
|
|
|
if (rc)
|
|
|
|
goto err_request_irq;
|
|
|
|
|
2010-06-03 08:53:18 +08:00
|
|
|
core_dev->dev->ce_base = of_iomap(ofdev->dev.of_node, 0);
|
2009-02-05 13:18:13 +08:00
|
|
|
if (!core_dev->dev->ce_base) {
|
|
|
|
dev_err(dev, "failed to of_iomap\n");
|
2012-09-18 01:28:27 +08:00
|
|
|
rc = -ENOMEM;
|
2009-02-05 13:18:13 +08:00
|
|
|
goto err_iomap;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* need to setup pdr, rdr, gdr and sdr before this */
|
|
|
|
crypto4xx_hw_init(core_dev->dev);
|
|
|
|
|
|
|
|
/* Register security algorithms with Linux CryptoAPI */
|
|
|
|
rc = crypto4xx_register_alg(core_dev->dev, crypto4xx_alg,
|
|
|
|
ARRAY_SIZE(crypto4xx_alg));
|
|
|
|
if (rc)
|
|
|
|
goto err_start_dev;
|
|
|
|
|
2016-04-18 18:57:41 +08:00
|
|
|
ppc4xx_trng_probe(core_dev);
|
2009-02-05 13:18:13 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_start_dev:
|
|
|
|
iounmap(core_dev->dev->ce_base);
|
|
|
|
err_iomap:
|
|
|
|
free_irq(core_dev->irq, dev);
|
2012-04-15 04:48:41 +08:00
|
|
|
err_request_irq:
|
2009-02-05 13:18:13 +08:00
|
|
|
irq_dispose_mapping(core_dev->irq);
|
|
|
|
tasklet_kill(&core_dev->tasklet);
|
|
|
|
err_build_sdr:
|
2017-08-25 21:47:24 +08:00
|
|
|
crypto4xx_destroy_sdr(core_dev->dev);
|
2009-02-05 13:18:13 +08:00
|
|
|
crypto4xx_destroy_gdr(core_dev->dev);
|
|
|
|
err_build_pdr:
|
2017-08-25 21:47:24 +08:00
|
|
|
crypto4xx_destroy_pdr(core_dev->dev);
|
2009-02-05 13:18:13 +08:00
|
|
|
kfree(core_dev->dev);
|
|
|
|
err_alloc_dev:
|
|
|
|
kfree(core_dev);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2015-03-10 04:35:39 +08:00
|
|
|
static int crypto4xx_remove(struct platform_device *ofdev)
|
2009-02-05 13:18:13 +08:00
|
|
|
{
|
|
|
|
struct device *dev = &ofdev->dev;
|
|
|
|
struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
|
|
|
|
|
2016-04-18 18:57:41 +08:00
|
|
|
ppc4xx_trng_remove(core_dev);
|
|
|
|
|
2009-02-05 13:18:13 +08:00
|
|
|
free_irq(core_dev->irq, dev);
|
|
|
|
irq_dispose_mapping(core_dev->irq);
|
|
|
|
|
|
|
|
tasklet_kill(&core_dev->tasklet);
|
|
|
|
/* Un-register with Linux CryptoAPI */
|
|
|
|
crypto4xx_unregister_alg(core_dev->dev);
|
|
|
|
/* Free all allocated memory */
|
|
|
|
crypto4xx_stop_all(core_dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-01-17 18:54:01 +08:00
|
|
|
static const struct of_device_id crypto4xx_match[] = {
|
2009-02-05 13:18:13 +08:00
|
|
|
{ .compatible = "amcc,ppc4xx-crypto",},
|
|
|
|
{ },
|
|
|
|
};
|
2015-08-29 00:43:24 +08:00
|
|
|
MODULE_DEVICE_TABLE(of, crypto4xx_match);
|
2009-02-05 13:18:13 +08:00
|
|
|
|
2011-02-23 10:59:54 +08:00
|
|
|
static struct platform_driver crypto4xx_driver = {
|
2010-04-14 07:13:02 +08:00
|
|
|
.driver = {
|
2016-04-18 18:57:41 +08:00
|
|
|
.name = MODULE_NAME,
|
2010-04-14 07:13:02 +08:00
|
|
|
.of_match_table = crypto4xx_match,
|
|
|
|
},
|
2009-02-05 13:18:13 +08:00
|
|
|
.probe = crypto4xx_probe,
|
2015-03-10 04:35:39 +08:00
|
|
|
.remove = crypto4xx_remove,
|
2009-02-05 13:18:13 +08:00
|
|
|
};
|
|
|
|
|
2011-11-26 21:26:19 +08:00
|
|
|
module_platform_driver(crypto4xx_driver);
|
2009-02-05 13:18:13 +08:00
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("James Hsiao <jhsiao@amcc.com>");
|
|
|
|
MODULE_DESCRIPTION("Driver for AMCC PPC4xx crypto accelerator");
|