2006-12-08 01:51:35 +08:00
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/*
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* arch/ia64/kernel/relocate_kernel.S
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*
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* Relocate kexec'able kernel and start it
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*
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* Copyright (C) 2005 Hewlett-Packard Development Company, L.P.
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* Copyright (C) 2005 Khalid Aziz <khalid.aziz@hp.com>
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* Copyright (C) 2005 Intel Corp, Zou Nan hai <nanhai.zou@intel.com>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 2. See the file COPYING for more details.
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*/
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#include <asm/asmmacro.h>
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#include <asm/kregs.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/mca_asm.h>
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/* Must be relocatable PIC code callable as a C function
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*/
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GLOBAL_ENTRY(relocate_new_kernel)
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.prologue
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alloc r31=ar.pfs,4,0,0,0
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.body
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.reloc_entry:
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{
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rsm psr.i| psr.ic
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mov r2=ip
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}
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;;
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{
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flushrs // must be first insn in group
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srlz.i
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}
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;;
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dep r2=0,r2,61,3 //to physical address
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;;
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//first switch to physical mode
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add r3=1f-.reloc_entry, r2
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movl r16 = IA64_PSR_AC|IA64_PSR_BN|IA64_PSR_IC
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mov ar.rsc=0 // put RSE in enforced lazy mode
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;;
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add sp=(memory_stack_end - 16 - .reloc_entry),r2
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add r8=(register_stack - .reloc_entry),r2
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;;
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mov r18=ar.rnat
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mov ar.bspstore=r8
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;;
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mov cr.ipsr=r16
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mov cr.iip=r3
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mov cr.ifs=r0
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srlz.i
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;;
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mov ar.rnat=r18
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[IA64] kdump: Mask INIT first in panic-kdump path
Summary:
Asserting INIT might block kdump if the system is already going to
start kdump via panic.
Description:
INIT can interrupt anywhere in panic path, so it can interrupt in
middle of kdump kicked by panic. Therefore there is a race if kdump
is kicked concurrently, via Panic and via INIT.
INIT could fail to invoke kdump if the system is already going to
start kdump via panic. It could not restart kdump from INIT handler
if some of cpus are already playing dead with INIT masked. It also
means that INIT could block kdump's progress if no monarch is entered
in the INIT rendezvous.
Panic+INIT is a rare, but possible situation since it can be assumed
that the kernel or an internal agent decides to panic the unstable
system while another external agent decides to send an INIT to the
system at same time.
How to reproduce:
Assert INIT just after panic, before all other cpus have frozen
Expected results:
continue kdump invoked by panic, or restart kdump from INIT
Actual results:
might be hang, crashdump not retrieved
Proposed Fix:
This patch masks INIT first in panic path to take the initiative on
kdump, and reuse atomic value kdump_in_progress to make sure there is
only one initiator of kdump. All INITs asserted later should be used
only for freezing all other cpus.
This mask will be removed soon by rfi in relocate_kernel.S, before jump
into kdump kernel, after all cpus are frozen and no-op INIT handler is
registered. So if INIT was in the interval while it is masked, it will
pend on the system and will received just after the rfi, and handled by
the no-op handler.
If there was a MCA event while psr.mc is 1, in theory the event will
pend on the system and will received just after the rfi same as above.
MCA handler is unregistered here at the time, so received MCA will not
reach to OS_MCA and will result in warmboot by SAL.
Note that codes in this masked interval are relatively simpler than
that in MCA/INIT handler which also executed with the mask. So it can
be said that probability of error in this interval is supposed not so
higher than that in MCA/INIT handler.
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Cc: Vivek Goyal <vgoyal@redhat.com>
Cc: Haren Myneni <hbabu@us.ibm.com>
Cc: kexec@lists.infradead.org
Acked-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2009-08-07 05:51:57 +08:00
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rfi // note: this unmask MCA/INIT (psr.mc)
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2006-12-08 01:51:35 +08:00
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;;
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1:
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//physical mode code begin
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mov b6=in1
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dep r28=0,in2,61,3 //to physical address
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// purge all TC entries
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#define O(member) IA64_CPUINFO_##member##_OFFSET
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2009-10-29 21:34:14 +08:00
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GET_THIS_PADDR(r2, ia64_cpu_info) // load phys addr of cpu_info into r2
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2006-12-08 01:51:35 +08:00
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;;
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addl r17=O(PTCE_STRIDE),r2
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addl r2=O(PTCE_BASE),r2
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;;
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ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
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ld4 r19=[r2],4 // r19=ptce_count[0]
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ld4 r21=[r17],4 // r21=ptce_stride[0]
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;;
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ld4 r20=[r2] // r20=ptce_count[1]
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ld4 r22=[r17] // r22=ptce_stride[1]
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mov r24=r0
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;;
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adds r20=-1,r20
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;;
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#undef O
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2:
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cmp.ltu p6,p7=r24,r19
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(p7) br.cond.dpnt.few 4f
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mov ar.lc=r20
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3:
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ptc.e r18
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;;
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add r18=r22,r18
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br.cloop.sptk.few 3b
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;;
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add r18=r21,r18
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add r24=1,r24
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;;
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br.sptk.few 2b
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4:
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srlz.i
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;;
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2007-05-09 01:00:28 +08:00
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// purge TR entry for kernel text and data
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2006-12-08 01:51:35 +08:00
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movl r16=KERNEL_START
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mov r18=KERNEL_TR_PAGE_SHIFT<<2
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;;
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ptr.i r16, r18
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ptr.d r16, r18
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;;
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srlz.i
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;;
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// purge TR entry for pal code
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mov r16=in3
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mov r18=IA64_GRANULE_SHIFT<<2
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;;
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ptr.i r16,r18
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;;
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srlz.i
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;;
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// purge TR entry for stack
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mov r16=IA64_KR(CURRENT_STACK)
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;;
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shl r16=r16,IA64_GRANULE_SHIFT
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movl r19=PAGE_OFFSET
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;;
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add r16=r19,r16
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mov r18=IA64_GRANULE_SHIFT<<2
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;;
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ptr.d r16,r18
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;;
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srlz.i
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;;
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//copy segments
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movl r16=PAGE_MASK
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mov r30=in0 // in0 is page_list
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br.sptk.few .dest_page
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;;
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.loop:
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ld8 r30=[in0], 8;;
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.dest_page:
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tbit.z p0, p6=r30, 0;; // 0x1 dest page
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(p6) and r17=r30, r16
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(p6) br.cond.sptk.few .loop;;
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tbit.z p0, p6=r30, 1;; // 0x2 indirect page
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(p6) and in0=r30, r16
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(p6) br.cond.sptk.few .loop;;
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tbit.z p0, p6=r30, 2;; // 0x4 end flag
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(p6) br.cond.sptk.few .end_loop;;
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tbit.z p6, p0=r30, 3;; // 0x8 source page
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(p6) br.cond.sptk.few .loop
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and r18=r30, r16
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// simple copy page, may optimize later
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movl r14=PAGE_SIZE/8 - 1;;
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mov ar.lc=r14;;
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1:
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ld8 r14=[r18], 8;;
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st8 [r17]=r14;;
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fc.i r17
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add r17=8, r17
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br.ctop.sptk.few 1b
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br.sptk.few .loop
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;;
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.end_loop:
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sync.i // for fc.i
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;;
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srlz.i
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;;
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srlz.d
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;;
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br.call.sptk.many b0=b6;;
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.align 32
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memory_stack:
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.fill 8192, 1, 0
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memory_stack_end:
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register_stack:
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.fill 8192, 1, 0
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register_stack_end:
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relocate_new_kernel_end:
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END(relocate_new_kernel)
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.global relocate_new_kernel_size
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relocate_new_kernel_size:
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data8 relocate_new_kernel_end - relocate_new_kernel
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GLOBAL_ENTRY(ia64_dump_cpu_regs)
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.prologue
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alloc loc0=ar.pfs,1,2,0,0
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.body
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mov ar.rsc=0 // put RSE in enforced lazy mode
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add loc1=4*8, in0 // save r4 and r5 first
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;;
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{
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flushrs // flush dirty regs to backing store
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srlz.i
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}
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st8 [loc1]=r4, 8
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;;
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st8 [loc1]=r5, 8
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;;
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add loc1=32*8, in0
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mov r4=ar.rnat
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;;
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st8 [in0]=r0, 8 // r0
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st8 [loc1]=r4, 8 // rnat
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mov r5=pr
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;;
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st8 [in0]=r1, 8 // r1
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st8 [loc1]=r5, 8 // pr
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mov r4=b0
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;;
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st8 [in0]=r2, 8 // r2
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st8 [loc1]=r4, 8 // b0
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mov r5=b1;
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;;
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st8 [in0]=r3, 24 // r3
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st8 [loc1]=r5, 8 // b1
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mov r4=b2
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;;
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st8 [in0]=r6, 8 // r6
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st8 [loc1]=r4, 8 // b2
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mov r5=b3
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;;
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st8 [in0]=r7, 8 // r7
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st8 [loc1]=r5, 8 // b3
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mov r4=b4
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;;
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st8 [in0]=r8, 8 // r8
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st8 [loc1]=r4, 8 // b4
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mov r5=b5
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;;
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st8 [in0]=r9, 8 // r9
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st8 [loc1]=r5, 8 // b5
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mov r4=b6
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;;
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st8 [in0]=r10, 8 // r10
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st8 [loc1]=r5, 8 // b6
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mov r5=b7
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;;
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st8 [in0]=r11, 8 // r11
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st8 [loc1]=r5, 8 // b7
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mov r4=b0
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;;
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st8 [in0]=r12, 8 // r12
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st8 [loc1]=r4, 8 // ip
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mov r5=loc0
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;;
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st8 [in0]=r13, 8 // r13
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extr.u r5=r5, 0, 38 // ar.pfs.pfm
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mov r4=r0 // user mask
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;;
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st8 [in0]=r14, 8 // r14
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st8 [loc1]=r5, 8 // cfm
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;;
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st8 [in0]=r15, 8 // r15
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st8 [loc1]=r4, 8 // user mask
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mov r5=ar.rsc
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;;
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st8 [in0]=r16, 8 // r16
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st8 [loc1]=r5, 8 // ar.rsc
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mov r4=ar.bsp
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;;
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st8 [in0]=r17, 8 // r17
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st8 [loc1]=r4, 8 // ar.bsp
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mov r5=ar.bspstore
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;;
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st8 [in0]=r18, 8 // r18
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st8 [loc1]=r5, 8 // ar.bspstore
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mov r4=ar.rnat
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;;
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st8 [in0]=r19, 8 // r19
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st8 [loc1]=r4, 8 // ar.rnat
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mov r5=ar.ccv
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;;
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st8 [in0]=r20, 8 // r20
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st8 [loc1]=r5, 8 // ar.ccv
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mov r4=ar.unat
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;;
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st8 [in0]=r21, 8 // r21
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st8 [loc1]=r4, 8 // ar.unat
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mov r5 = ar.fpsr
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;;
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st8 [in0]=r22, 8 // r22
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st8 [loc1]=r5, 8 // ar.fpsr
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mov r4 = ar.unat
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;;
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st8 [in0]=r23, 8 // r23
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st8 [loc1]=r4, 8 // unat
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mov r5 = ar.fpsr
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;;
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st8 [in0]=r24, 8 // r24
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st8 [loc1]=r5, 8 // fpsr
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mov r4 = ar.pfs
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;;
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st8 [in0]=r25, 8 // r25
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st8 [loc1]=r4, 8 // ar.pfs
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mov r5 = ar.lc
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;;
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st8 [in0]=r26, 8 // r26
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st8 [loc1]=r5, 8 // ar.lc
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mov r4 = ar.ec
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;;
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st8 [in0]=r27, 8 // r27
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st8 [loc1]=r4, 8 // ar.ec
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mov r5 = ar.csd
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;;
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st8 [in0]=r28, 8 // r28
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st8 [loc1]=r5, 8 // ar.csd
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mov r4 = ar.ssd
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;;
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st8 [in0]=r29, 8 // r29
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st8 [loc1]=r4, 8 // ar.ssd
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;;
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st8 [in0]=r30, 8 // r30
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;;
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st8 [in0]=r31, 8 // r31
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mov ar.pfs=loc0
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;;
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br.ret.sptk.many rp
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END(ia64_dump_cpu_regs)
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