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26 lines
1.3 KiB
Plaintext
26 lines
1.3 KiB
Plaintext
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Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
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===========================================================================
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This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
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Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
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by all cores within a socket. Each slice is exposed as a separate uncore perf
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PMU with device name l3cache_<socket>_<instance>. User space is responsible
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for aggregating across slices.
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The driver provides a description of its available events and configuration
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options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
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the driver also exposes a "cpumask" sysfs attribute which contains a mask
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consisting of one CPU per socket which will be used to handle all the PMU
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events on that socket.
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The hardware implements 32bit event counters and has a flat 8bit event space
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exposed via the "event" format attribute. In addition to the 32bit physical
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counters the driver supports virtual 64bit hardware counters by using hardware
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counter chaining. This feature is exposed via the "lc" (long counter) format
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flag. E.g.:
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perf stat -e l3cache_0_0/read-miss,lc/
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Given that these are uncore PMUs the driver does not support sampling, therefore
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"perf record" will not work. Per-task perf sessions are not supported.
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