2008-02-20 06:51:27 +08:00
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/*
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2008-07-23 03:09:08 +08:00
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* @file op_model_amd.c
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2007-12-19 01:05:58 +08:00
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* athlon / K7 / K8 / Family 10h model-specific MSR operations
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2005-04-17 06:20:36 +08:00
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*
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2008-12-26 00:26:07 +08:00
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* @remark Copyright 2002-2009 OProfile authors
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2005-04-17 06:20:36 +08:00
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* @remark Read the file COPYING
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*
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* @author John Levon
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* @author Philippe Elie
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* @author Graydon Hoare
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2008-07-23 03:08:48 +08:00
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* @author Robert Richter <robert.richter@amd.com>
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2009-07-08 19:49:38 +08:00
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* @author Barry Kasindorf <barry.kasindorf@amd.com>
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* @author Jason Yeh <jason.yeh@amd.com>
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* @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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2008-12-26 00:26:07 +08:00
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*/
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2005-04-17 06:20:36 +08:00
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#include <linux/oprofile.h>
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2008-07-23 03:08:55 +08:00
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#include <linux/device.h>
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#include <linux/pci.h>
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2009-07-08 19:49:38 +08:00
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#include <linux/percpu.h>
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2008-07-23 03:08:55 +08:00
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2005-04-17 06:20:36 +08:00
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#include <asm/ptrace.h>
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#include <asm/msr.h>
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2006-06-26 19:57:01 +08:00
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#include <asm/nmi.h>
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2010-01-29 01:05:26 +08:00
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#include <asm/apic.h>
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2010-02-04 17:57:23 +08:00
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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2008-02-20 06:51:27 +08:00
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2005-04-17 06:20:36 +08:00
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#include "op_x86_model.h"
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#include "op_counter.h"
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2008-09-24 17:08:52 +08:00
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#define NUM_COUNTERS 4
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#define NUM_CONTROLS 4
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2009-07-08 19:49:38 +08:00
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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#define NUM_VIRT_COUNTERS 32
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#define NUM_VIRT_CONTROLS 32
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#else
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#define NUM_VIRT_COUNTERS NUM_COUNTERS
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#define NUM_VIRT_CONTROLS NUM_CONTROLS
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#endif
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2009-05-25 21:10:32 +08:00
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#define OP_EVENT_MASK 0x0FFF
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2009-05-25 23:59:06 +08:00
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#define OP_CTR_OVERFLOW (1ULL<<31)
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2009-05-25 21:10:32 +08:00
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#define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
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2005-04-17 06:20:36 +08:00
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2009-07-08 19:49:38 +08:00
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static unsigned long reset_value[NUM_VIRT_COUNTERS];
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2008-07-23 03:09:06 +08:00
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2008-07-23 03:09:03 +08:00
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/* IbsFetchCtl bits/masks */
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2009-06-04 02:10:39 +08:00
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#define IBS_FETCH_RAND_EN (1ULL<<57)
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#define IBS_FETCH_VAL (1ULL<<49)
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#define IBS_FETCH_ENABLE (1ULL<<48)
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#define IBS_FETCH_CNT_MASK 0xFFFF0000ULL
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2008-07-23 03:08:55 +08:00
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2008-07-23 03:09:03 +08:00
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/*IbsOpCtl bits */
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2009-06-04 02:10:39 +08:00
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#define IBS_OP_CNT_CTL (1ULL<<19)
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#define IBS_OP_VAL (1ULL<<18)
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#define IBS_OP_ENABLE (1ULL<<17)
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2008-07-23 03:08:55 +08:00
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2009-06-04 02:10:39 +08:00
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#define IBS_FETCH_SIZE 6
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#define IBS_OP_SIZE 12
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2008-07-23 03:08:55 +08:00
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2010-02-04 17:57:23 +08:00
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static u32 ibs_caps;
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2008-07-23 03:08:55 +08:00
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struct op_ibs_config {
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unsigned long op_enabled;
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unsigned long fetch_enabled;
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unsigned long max_cnt_fetch;
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unsigned long max_cnt_op;
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unsigned long rand_en;
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unsigned long dispatched_ops;
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};
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static struct op_ibs_config ibs_config;
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2008-02-20 06:51:27 +08:00
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2010-02-04 17:57:23 +08:00
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/*
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* IBS cpuid feature detection
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*/
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#define IBS_CPUID_FEATURES 0x8000001b
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/*
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* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
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* bit 0 is used to indicate the existence of IBS.
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*/
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#define IBS_CAPS_AVAIL (1LL<<0)
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#define IBS_CAPS_OPCNT (1LL<<4)
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static u32 get_ibs_caps(void)
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{
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u32 ibs_caps;
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unsigned int max_level;
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if (!boot_cpu_has(X86_FEATURE_IBS))
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return 0;
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/* check IBS cpuid feature flags */
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max_level = cpuid_eax(0x80000000);
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if (max_level < IBS_CPUID_FEATURES)
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return IBS_CAPS_AVAIL;
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ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
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if (!(ibs_caps & IBS_CAPS_AVAIL))
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/* cpuid flags not valid */
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return IBS_CAPS_AVAIL;
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return ibs_caps;
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}
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2009-07-16 19:09:53 +08:00
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
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2009-07-10 21:47:17 +08:00
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int hw_counter = op_x86_virt_to_phys(i);
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2009-07-16 19:09:53 +08:00
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if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
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else
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msrs->multiplex[i].addr = 0;
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}
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}
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static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!counter_config[virt].enabled)
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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#else
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static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { }
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#endif
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2008-07-23 03:08:50 +08:00
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/* functions for op_amd_spec */
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2008-07-23 03:08:49 +08:00
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2008-07-23 03:08:50 +08:00
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static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
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2005-04-17 06:20:36 +08:00
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{
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2006-09-26 16:52:26 +08:00
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int i;
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2008-02-20 06:51:27 +08:00
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for (i = 0; i < NUM_COUNTERS; i++) {
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2008-09-24 17:08:52 +08:00
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if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
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2006-09-26 16:52:26 +08:00
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else
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msrs->counters[i].addr = 0;
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}
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2008-02-20 06:51:27 +08:00
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for (i = 0; i < NUM_CONTROLS; i++) {
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2008-09-24 17:08:52 +08:00
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if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
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msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
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2006-09-26 16:52:26 +08:00
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else
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msrs->controls[i].addr = 0;
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}
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2009-07-08 19:49:38 +08:00
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2009-07-16 19:09:53 +08:00
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op_mux_fill_in_addresses(msrs);
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2005-04-17 06:20:36 +08:00
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}
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2009-05-26 01:31:44 +08:00
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static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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2005-04-17 06:20:36 +08:00
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{
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2009-05-25 21:10:32 +08:00
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u64 val;
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2005-04-17 06:20:36 +08:00
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int i;
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2008-02-20 06:51:27 +08:00
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2009-07-08 19:49:38 +08:00
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/* setup reset_value */
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for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
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2009-07-16 19:11:16 +08:00
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if (counter_config[i].enabled)
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2009-07-08 19:49:38 +08:00
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reset_value[i] = counter_config[i].count;
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2009-07-16 19:11:16 +08:00
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else
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2009-07-08 19:49:38 +08:00
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reset_value[i] = 0;
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}
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2005-04-17 06:20:36 +08:00
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/* clear all counters */
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2009-07-08 01:25:39 +08:00
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for (i = 0; i < NUM_CONTROLS; ++i) {
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2009-06-04 08:36:44 +08:00
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if (unlikely(!msrs->controls[i].addr))
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2006-09-26 16:52:26 +08:00
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continue;
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2009-05-25 21:10:32 +08:00
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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2005-04-17 06:20:36 +08:00
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}
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2006-09-26 16:52:26 +08:00
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2005-04-17 06:20:36 +08:00
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/* avoid a false detection of ctr overflows in NMI handler */
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2008-09-24 17:08:52 +08:00
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for (i = 0; i < NUM_COUNTERS; ++i) {
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2009-06-04 08:36:44 +08:00
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if (unlikely(!msrs->counters[i].addr))
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2006-09-26 16:52:26 +08:00
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continue;
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2009-05-25 23:38:19 +08:00
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wrmsrl(msrs->counters[i].addr, -1LL);
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2005-04-17 06:20:36 +08:00
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}
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/* enable active counters */
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2008-09-24 17:08:52 +08:00
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for (i = 0; i < NUM_COUNTERS; ++i) {
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2009-07-16 19:04:43 +08:00
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int virt = op_x86_phys_to_virt(i);
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if (!counter_config[virt].enabled)
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continue;
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if (!msrs->counters[i].addr)
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continue;
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/* setup counter registers */
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
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/* setup control registers */
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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2009-07-08 19:49:38 +08:00
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}
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}
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2009-06-24 03:36:08 +08:00
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static inline void
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2008-07-23 03:08:56 +08:00
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op_amd_handle_ibs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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2005-04-17 06:20:36 +08:00
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{
|
2009-06-04 02:10:39 +08:00
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u64 val, ctl;
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2009-01-05 17:35:31 +08:00
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struct op_entry entry;
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2005-04-17 06:20:36 +08:00
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|
2010-02-04 17:57:23 +08:00
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if (!ibs_caps)
|
2009-06-24 03:36:08 +08:00
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return;
|
2005-04-17 06:20:36 +08:00
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|
2008-07-23 03:08:56 +08:00
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if (ibs_config.fetch_enabled) {
|
2009-06-04 02:10:39 +08:00
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rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
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if (ctl & IBS_FETCH_VAL) {
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rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
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oprofile_write_reserve(&entry, regs, val,
|
2009-01-08 04:50:22 +08:00
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IBS_FETCH_CODE, IBS_FETCH_SIZE);
|
2009-06-04 02:54:56 +08:00
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oprofile_add_data64(&entry, val);
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oprofile_add_data64(&entry, ctl);
|
2009-06-04 02:10:39 +08:00
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rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
|
2009-06-04 02:54:56 +08:00
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oprofile_add_data64(&entry, val);
|
2009-01-08 04:50:22 +08:00
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oprofile_write_commit(&entry);
|
2008-07-23 03:08:55 +08:00
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2008-10-20 03:00:09 +08:00
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/* reenable the IRQ */
|
2009-06-04 02:10:39 +08:00
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ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
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ctl |= IBS_FETCH_ENABLE;
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wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
|
2008-07-23 03:08:55 +08:00
|
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|
}
|
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}
|
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|
2008-07-23 03:08:56 +08:00
|
|
|
if (ibs_config.op_enabled) {
|
2009-06-04 02:10:39 +08:00
|
|
|
rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
|
|
|
|
if (ctl & IBS_OP_VAL) {
|
|
|
|
rdmsrl(MSR_AMD64_IBSOPRIP, val);
|
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|
|
oprofile_write_reserve(&entry, regs, val,
|
2009-01-08 04:50:22 +08:00
|
|
|
IBS_OP_CODE, IBS_OP_SIZE);
|
2009-06-04 02:54:56 +08:00
|
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|
oprofile_add_data64(&entry, val);
|
2009-06-04 02:10:39 +08:00
|
|
|
rdmsrl(MSR_AMD64_IBSOPDATA, val);
|
2009-06-04 02:54:56 +08:00
|
|
|
oprofile_add_data64(&entry, val);
|
2009-06-04 02:10:39 +08:00
|
|
|
rdmsrl(MSR_AMD64_IBSOPDATA2, val);
|
2009-06-04 02:54:56 +08:00
|
|
|
oprofile_add_data64(&entry, val);
|
2009-06-04 02:10:39 +08:00
|
|
|
rdmsrl(MSR_AMD64_IBSOPDATA3, val);
|
2009-06-04 02:54:56 +08:00
|
|
|
oprofile_add_data64(&entry, val);
|
2009-06-04 02:10:39 +08:00
|
|
|
rdmsrl(MSR_AMD64_IBSDCLINAD, val);
|
2009-06-04 02:54:56 +08:00
|
|
|
oprofile_add_data64(&entry, val);
|
2009-06-04 02:10:39 +08:00
|
|
|
rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
|
2009-06-04 02:54:56 +08:00
|
|
|
oprofile_add_data64(&entry, val);
|
2009-01-08 04:50:22 +08:00
|
|
|
oprofile_write_commit(&entry);
|
2008-07-23 03:08:55 +08:00
|
|
|
|
|
|
|
/* reenable the IRQ */
|
2009-06-04 02:10:39 +08:00
|
|
|
ctl &= ~IBS_OP_VAL & 0xFFFFFFFF;
|
|
|
|
ctl |= IBS_OP_ENABLE;
|
|
|
|
wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
|
2008-07-23 03:08:55 +08:00
|
|
|
}
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2009-03-11 02:15:57 +08:00
|
|
|
static inline void op_amd_start_ibs(void)
|
|
|
|
{
|
2009-06-04 02:10:39 +08:00
|
|
|
u64 val;
|
2010-02-04 17:57:23 +08:00
|
|
|
|
|
|
|
if (!ibs_caps)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (ibs_config.fetch_enabled) {
|
2009-06-04 02:10:39 +08:00
|
|
|
val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
|
|
|
|
val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
|
|
|
|
val |= IBS_FETCH_ENABLE;
|
|
|
|
wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
|
2009-03-11 02:15:57 +08:00
|
|
|
}
|
|
|
|
|
2010-02-04 17:57:23 +08:00
|
|
|
if (ibs_config.op_enabled) {
|
2009-06-04 02:10:39 +08:00
|
|
|
val = (ibs_config.max_cnt_op >> 4) & 0xFFFF;
|
2010-02-04 17:57:23 +08:00
|
|
|
if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
|
|
|
|
val |= IBS_OP_CNT_CTL;
|
2009-06-04 02:10:39 +08:00
|
|
|
val |= IBS_OP_ENABLE;
|
|
|
|
wrmsrl(MSR_AMD64_IBSOPCTL, val);
|
2009-03-11 02:15:57 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void op_amd_stop_ibs(void)
|
|
|
|
{
|
2010-02-04 17:57:23 +08:00
|
|
|
if (!ibs_caps)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (ibs_config.fetch_enabled)
|
2009-03-11 02:15:57 +08:00
|
|
|
/* clear max count and enable */
|
2009-06-04 02:10:39 +08:00
|
|
|
wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
|
2009-03-11 02:15:57 +08:00
|
|
|
|
2010-02-04 17:57:23 +08:00
|
|
|
if (ibs_config.op_enabled)
|
2009-03-11 02:15:57 +08:00
|
|
|
/* clear max count and enable */
|
2009-06-04 02:10:39 +08:00
|
|
|
wrmsrl(MSR_AMD64_IBSOPCTL, 0);
|
2009-03-11 02:15:57 +08:00
|
|
|
}
|
|
|
|
|
2008-07-23 03:08:56 +08:00
|
|
|
static int op_amd_check_ctrs(struct pt_regs * const regs,
|
|
|
|
struct op_msrs const * const msrs)
|
|
|
|
{
|
2009-05-25 23:59:06 +08:00
|
|
|
u64 val;
|
2008-07-23 03:08:56 +08:00
|
|
|
int i;
|
|
|
|
|
2009-07-08 01:25:39 +08:00
|
|
|
for (i = 0; i < NUM_COUNTERS; ++i) {
|
2009-07-16 19:04:43 +08:00
|
|
|
int virt = op_x86_phys_to_virt(i);
|
|
|
|
if (!reset_value[virt])
|
2008-07-23 03:08:56 +08:00
|
|
|
continue;
|
2009-05-25 23:59:06 +08:00
|
|
|
rdmsrl(msrs->counters[i].addr, val);
|
|
|
|
/* bit is clear if overflowed: */
|
|
|
|
if (val & OP_CTR_OVERFLOW)
|
|
|
|
continue;
|
2009-07-16 19:04:43 +08:00
|
|
|
oprofile_add_sample(regs, virt);
|
|
|
|
wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
|
2008-07-23 03:08:56 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
op_amd_handle_ibs(regs, msrs);
|
|
|
|
|
|
|
|
/* See op_model_ppro.c */
|
|
|
|
return 1;
|
|
|
|
}
|
2008-02-20 06:51:27 +08:00
|
|
|
|
2008-07-23 03:08:50 +08:00
|
|
|
static void op_amd_start(struct op_msrs const * const msrs)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2009-05-26 00:11:52 +08:00
|
|
|
u64 val;
|
2005-04-17 06:20:36 +08:00
|
|
|
int i;
|
2009-07-08 19:49:38 +08:00
|
|
|
|
2009-07-08 01:25:39 +08:00
|
|
|
for (i = 0; i < NUM_COUNTERS; ++i) {
|
2009-07-16 19:04:43 +08:00
|
|
|
if (!reset_value[op_x86_phys_to_virt(i)])
|
|
|
|
continue;
|
|
|
|
rdmsrl(msrs->controls[i].addr, val);
|
|
|
|
val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
|
|
|
|
wrmsrl(msrs->controls[i].addr, val);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2008-07-23 03:09:06 +08:00
|
|
|
|
2009-03-11 02:15:57 +08:00
|
|
|
op_amd_start_ibs();
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2008-07-23 03:08:50 +08:00
|
|
|
static void op_amd_stop(struct op_msrs const * const msrs)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2009-05-26 00:11:52 +08:00
|
|
|
u64 val;
|
2005-04-17 06:20:36 +08:00
|
|
|
int i;
|
|
|
|
|
2008-10-20 03:00:09 +08:00
|
|
|
/*
|
|
|
|
* Subtle: stop on all counters to avoid race with setting our
|
|
|
|
* pm callback
|
|
|
|
*/
|
2009-07-08 01:25:39 +08:00
|
|
|
for (i = 0; i < NUM_COUNTERS; ++i) {
|
2009-07-16 19:04:43 +08:00
|
|
|
if (!reset_value[op_x86_phys_to_virt(i)])
|
2006-09-26 16:52:26 +08:00
|
|
|
continue;
|
2009-05-26 00:11:52 +08:00
|
|
|
rdmsrl(msrs->controls[i].addr, val);
|
|
|
|
val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
|
|
|
|
wrmsrl(msrs->controls[i].addr, val);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2008-07-23 03:08:55 +08:00
|
|
|
|
2009-03-11 02:15:57 +08:00
|
|
|
op_amd_stop_ibs();
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2008-07-23 03:08:50 +08:00
|
|
|
static void op_amd_shutdown(struct op_msrs const * const msrs)
|
2006-09-26 16:52:26 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2009-07-08 01:25:39 +08:00
|
|
|
for (i = 0; i < NUM_COUNTERS; ++i) {
|
2009-06-04 08:36:44 +08:00
|
|
|
if (msrs->counters[i].addr)
|
2006-09-26 16:52:26 +08:00
|
|
|
release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
|
|
|
|
}
|
2009-07-08 20:54:17 +08:00
|
|
|
for (i = 0; i < NUM_CONTROLS; ++i) {
|
2009-06-04 08:36:44 +08:00
|
|
|
if (msrs->controls[i].addr)
|
2006-09-26 16:52:26 +08:00
|
|
|
release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
|
|
|
|
}
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-07-23 03:08:57 +08:00
|
|
|
static u8 ibs_eilvt_off;
|
|
|
|
|
2008-07-23 03:08:55 +08:00
|
|
|
static inline void apic_init_ibs_nmi_per_cpu(void *arg)
|
|
|
|
{
|
2008-07-23 03:08:57 +08:00
|
|
|
ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
|
2008-07-23 03:08:55 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
|
|
|
|
{
|
|
|
|
setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
|
|
|
|
}
|
|
|
|
|
2008-11-24 21:58:03 +08:00
|
|
|
static int init_ibs_nmi(void)
|
2008-07-23 03:08:57 +08:00
|
|
|
{
|
|
|
|
#define IBSCTL_LVTOFFSETVAL (1 << 8)
|
|
|
|
#define IBSCTL 0x1cc
|
|
|
|
struct pci_dev *cpu_cfg;
|
|
|
|
int nodes;
|
|
|
|
u32 value = 0;
|
|
|
|
|
|
|
|
/* per CPU setup */
|
2008-07-23 03:08:59 +08:00
|
|
|
on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
|
2008-07-23 03:08:57 +08:00
|
|
|
|
|
|
|
nodes = 0;
|
|
|
|
cpu_cfg = NULL;
|
|
|
|
do {
|
|
|
|
cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
|
|
|
|
PCI_DEVICE_ID_AMD_10H_NB_MISC,
|
|
|
|
cpu_cfg);
|
|
|
|
if (!cpu_cfg)
|
|
|
|
break;
|
|
|
|
++nodes;
|
|
|
|
pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
|
|
|
|
| IBSCTL_LVTOFFSETVAL);
|
|
|
|
pci_read_config_dword(cpu_cfg, IBSCTL, &value);
|
|
|
|
if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
|
2008-12-15 22:09:50 +08:00
|
|
|
pci_dev_put(cpu_cfg);
|
2008-07-23 03:08:57 +08:00
|
|
|
printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
|
|
|
|
"IBSCTL = 0x%08x", value);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
} while (1);
|
|
|
|
|
|
|
|
if (!nodes) {
|
|
|
|
printk(KERN_DEBUG "No CPU node configured for IBS");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-11-24 21:58:03 +08:00
|
|
|
/* uninitialize the APIC for the IBS interrupts if needed */
|
|
|
|
static void clear_ibs_nmi(void)
|
|
|
|
{
|
2010-02-04 17:57:23 +08:00
|
|
|
if (ibs_caps)
|
2008-11-24 21:58:03 +08:00
|
|
|
on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
|
|
|
|
}
|
|
|
|
|
2008-10-20 03:00:09 +08:00
|
|
|
/* initialize the APIC for the IBS interrupts if available */
|
2008-11-24 21:58:03 +08:00
|
|
|
static void ibs_init(void)
|
2008-07-23 03:08:55 +08:00
|
|
|
{
|
2010-02-04 17:57:23 +08:00
|
|
|
ibs_caps = get_ibs_caps();
|
2008-07-23 03:08:55 +08:00
|
|
|
|
2010-02-04 17:57:23 +08:00
|
|
|
if (!ibs_caps)
|
2008-07-23 03:08:55 +08:00
|
|
|
return;
|
|
|
|
|
2008-11-24 21:58:03 +08:00
|
|
|
if (init_ibs_nmi()) {
|
2010-02-04 17:57:23 +08:00
|
|
|
ibs_caps = 0;
|
2008-07-23 03:09:06 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-02-04 17:57:23 +08:00
|
|
|
printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
|
|
|
|
(unsigned)ibs_caps);
|
2008-07-23 03:08:55 +08:00
|
|
|
}
|
|
|
|
|
2008-11-24 21:58:03 +08:00
|
|
|
static void ibs_exit(void)
|
2008-07-23 03:08:55 +08:00
|
|
|
{
|
2010-02-04 17:57:23 +08:00
|
|
|
if (!ibs_caps)
|
2008-11-24 21:58:03 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
clear_ibs_nmi();
|
2008-07-23 03:08:55 +08:00
|
|
|
}
|
|
|
|
|
2008-09-05 23:12:36 +08:00
|
|
|
static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
|
2008-07-23 03:09:01 +08:00
|
|
|
|
2008-09-05 23:12:36 +08:00
|
|
|
static int setup_ibs_files(struct super_block *sb, struct dentry *root)
|
2008-07-23 03:08:55 +08:00
|
|
|
{
|
|
|
|
struct dentry *dir;
|
2008-07-23 03:09:01 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
/* architecture specific files */
|
|
|
|
if (create_arch_files)
|
|
|
|
ret = create_arch_files(sb, root);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2008-07-23 03:08:55 +08:00
|
|
|
|
2010-02-04 17:57:23 +08:00
|
|
|
if (!ibs_caps)
|
2008-07-23 03:09:01 +08:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* model specific files */
|
2008-07-23 03:08:55 +08:00
|
|
|
|
|
|
|
/* setup some reasonable defaults */
|
|
|
|
ibs_config.max_cnt_fetch = 250000;
|
|
|
|
ibs_config.fetch_enabled = 0;
|
|
|
|
ibs_config.max_cnt_op = 250000;
|
|
|
|
ibs_config.op_enabled = 0;
|
2010-02-04 17:57:23 +08:00
|
|
|
ibs_config.dispatched_ops = 0;
|
2008-07-18 23:56:05 +08:00
|
|
|
|
|
|
|
dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
|
2008-07-23 03:08:55 +08:00
|
|
|
oprofilefs_create_ulong(sb, dir, "enable",
|
2008-07-18 23:56:05 +08:00
|
|
|
&ibs_config.fetch_enabled);
|
2008-07-23 03:08:55 +08:00
|
|
|
oprofilefs_create_ulong(sb, dir, "max_count",
|
2008-07-18 23:56:05 +08:00
|
|
|
&ibs_config.max_cnt_fetch);
|
|
|
|
oprofilefs_create_ulong(sb, dir, "rand_enable",
|
|
|
|
&ibs_config.rand_en);
|
|
|
|
|
2008-07-29 22:57:10 +08:00
|
|
|
dir = oprofilefs_mkdir(sb, root, "ibs_op");
|
2008-07-23 03:08:55 +08:00
|
|
|
oprofilefs_create_ulong(sb, dir, "enable",
|
2008-07-18 23:56:05 +08:00
|
|
|
&ibs_config.op_enabled);
|
2008-07-23 03:08:55 +08:00
|
|
|
oprofilefs_create_ulong(sb, dir, "max_count",
|
2008-07-18 23:56:05 +08:00
|
|
|
&ibs_config.max_cnt_op);
|
2010-02-04 17:57:23 +08:00
|
|
|
if (ibs_caps & IBS_CAPS_OPCNT)
|
|
|
|
oprofilefs_create_ulong(sb, dir, "dispatched_ops",
|
|
|
|
&ibs_config.dispatched_ops);
|
2008-07-23 03:09:00 +08:00
|
|
|
|
|
|
|
return 0;
|
2008-07-23 03:08:55 +08:00
|
|
|
}
|
|
|
|
|
2008-07-23 03:08:48 +08:00
|
|
|
static int op_amd_init(struct oprofile_operations *ops)
|
|
|
|
{
|
2008-11-24 21:58:03 +08:00
|
|
|
ibs_init();
|
2008-07-23 03:09:01 +08:00
|
|
|
create_arch_files = ops->create_files;
|
|
|
|
ops->create_files = setup_ibs_files;
|
2008-07-23 03:08:48 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void op_amd_exit(void)
|
|
|
|
{
|
2008-11-24 21:58:03 +08:00
|
|
|
ibs_exit();
|
2008-07-23 03:08:48 +08:00
|
|
|
}
|
|
|
|
|
2009-07-09 21:12:35 +08:00
|
|
|
struct op_x86_model_spec op_amd_spec = {
|
2008-09-05 23:12:36 +08:00
|
|
|
.num_counters = NUM_COUNTERS,
|
|
|
|
.num_controls = NUM_CONTROLS,
|
2009-07-08 19:49:38 +08:00
|
|
|
.num_virt_counters = NUM_VIRT_COUNTERS,
|
2009-05-25 21:10:32 +08:00
|
|
|
.reserved = MSR_AMD_EVENTSEL_RESERVED,
|
|
|
|
.event_mask = OP_EVENT_MASK,
|
|
|
|
.init = op_amd_init,
|
|
|
|
.exit = op_amd_exit,
|
2008-09-05 23:12:36 +08:00
|
|
|
.fill_in_addresses = &op_amd_fill_in_addresses,
|
|
|
|
.setup_ctrs = &op_amd_setup_ctrs,
|
|
|
|
.check_ctrs = &op_amd_check_ctrs,
|
|
|
|
.start = &op_amd_start,
|
|
|
|
.stop = &op_amd_stop,
|
2009-05-25 21:10:32 +08:00
|
|
|
.shutdown = &op_amd_shutdown,
|
2009-07-08 19:49:38 +08:00
|
|
|
#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
|
2009-07-16 19:09:53 +08:00
|
|
|
.switch_ctrl = &op_mux_switch_ctrl,
|
2009-07-08 19:49:38 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|